JP2003152177A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a field effect transistor and its manufacturing method which has a built-in electric field formed in the moving direction of carriers in a channel region. SOLUTION: A first epitaxial grown part 151 bridged between a first active region 101a and a trench-isolated region 105 comprises a first central Si film 102a, a first SiGe film 103a, a first outer Si film 104a, a first Si cap layer 106a, a first thermal oxidation film 107a, and a gate electrode 108. In the grown part 151, a source region 109 and a drain region 110 are provided inside and outside the gate electrode 108, respectively, and a channel region 117 is provided below the gate electrode 108, thus obtaining a semiconductor device having a field effect transistor in which the travel of carriers in the channel is accelerated to provide a high operating speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a field effect transistor (FET) manufactured by epitaxial growth and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, field effect transistors utilizing heterojunction have been attracting attention as next-generation ultrahigh-speed electronic devices. As such an ultra high speed electronic device, G
HEMT (High Ele) with a gate structure of a Schottky junction using a III-V group compound semiconductor such as aAs or InP
Ctron Mobility Transistor) has been actively researched and developed, but recently, field effect transistors using SiGe-based materials, which are IV-IV mixed crystal compounds, have attracted attention as ultra-fast electronic devices. There is. A field effect transistor using a IV-IV group mixed crystal compound can utilize the current Si process for its manufacturing process, and is therefore required for equipment for communication systems such as high frequency circuit devices and baseband circuit devices. Various devices can be formed on the same substrate, and future system
There are great expectations for on-chip implementation.

FIG. 17 shows a MIS (Metal Insulator Semi).
FIG. 7 is a cross-sectional view of a conventional p-channel field effect transistor (SiGe-pMISFET) having a (conductor) type gate structure and using a SiGe layer as a channel. As shown in the figure, the conventional SiGe-pMISFET is
n-type Si substrate 201, Si buffer layer 202 provided on the Si substrate 201, SiGe channel layer 203 provided on the Si buffer layer 202, and Si cap provided on the SiGe channel layer 203 Layer 204
A gate oxide film 205 and a gate electrode 206 provided on the Si cap layer 204, and a source region 207 and a drain region containing high-concentration p-type impurities provided on both sides of the gate electrode 206 in the Si substrate 201. 208
And an element isolation insulating film 209 surrounding the active region. In addition, the source electrode 211 and the drain electrode 212 which penetrate the interlayer insulating film 210 deposited on the substrate and reach the source region 207 and the drain region 208, respectively.
Is provided.

18 (a) and 18 (b) respectively show
FIG. 5 is a diagram showing a Ge composition ratio profile in the depth direction of a conventional SiGe-p MISFET, and an energy band diagram when a gate bias is applied.

As shown in FIG. 18A, a conventional SiG is used.
The Ge composition ratio in the SiGe channel layer 203 of the e-pMISFET is uniform (15%). In addition, FIG.
As shown in (b), a hetero barrier (band offset amount ΔEv) is formed mainly at the valence band edge and almost no hetero barrier is formed at the conduction band edge at the interface between the Si cap layer / SiGe channel layer. So SiG
The e-channel layer 203 is exclusively used as a p-channel through which holes travel. That is, as shown in FIG. 18A, in the state where the gate bias close to the threshold voltage is applied, the highest energy level portion of the SiGe channel layer 203 is higher than the Si cap layer 204 in the vacuum level. Is close to. Therefore,
SiGe channel layer 203 rather than Si cap layer 204
Is more likely to generate holes, so SiGe-pMIS
The FET operates at a lower threshold voltage than a normal Si-pMISFET. Moreover, since the SiGe crystal has a larger lattice constant in the bulk state than the Si crystal,
The SiGe layer grown on the layer contains a compressive strain. Then, due to this compressive strain, the SiGe channel layer 2
Since the degeneracy of the 03 valence band is resolved and band splitting occurs, high-speed operation using a light hole with high mobility becomes possible.

19 (a) and 19 (b) respectively show,
Conventional SiG having a SiGe channel layer 203 having a graded composition in which the Ge composition ratio is changed from 0% to 30%
FIG. 3 is a diagram showing a profile of a Ge composition ratio in the depth direction of an e-pMISFET, and an energy band diagram when a gate bias is applied. FIG. 19B also shows the energy band structure when a gate bias close to the threshold voltage is applied. As shown in the figure, this MISFE
In T, since the structure having the graded composition is such that the band offset amount ΔEv at the interface between the Si cap layer / SiGe channel layer becomes large, the strain equivalent to that shown in FIG. While having the same thermal stability), holes can be more strongly confined in the SiGe layer 203 which is a high-speed channel, and high-speed operation up to a higher voltage can be realized.

As described above, by using the Si / SiGe heterojunction, it is possible to reduce the voltage and increase the speed of the MISFET.

Next, FIGS. 20 (a) to 20 (c) show the above-mentioned conventional SiGe-pM having a sectional structure as shown in FIG.
It is sectional drawing which shows the manufacturing process of ISFET.

First, in the step shown in FIG. 20A, after ion implantation for impurity concentration adjustment for threshold voltage adjustment (not shown) is performed in the Si substrate 201, UHV-
By CVD, the Si buffer layer 202, the SiGe channel layer 203, and the Si cap layer 204 are epitaxially grown in order on the Si substrate 201. Si and G
The source gas for e is Si ₂ H ₆ (disilane), respectively.
And GeH ₄ (German). The thicknesses of the Si buffer layer 202, the SiGe channel layer 203, and the Si cap layer 203 are about 10 nm and about 15 n, respectively.
m, about 15 nm (however, the value when the manufacturing process is completed). The growth temperature is 550 ° C., and no intentional doping is performed. At this time, the SiGe channel layer 20
3 has strain inherent in the difference in lattice constant from the Si buffer layer 202.

Next, in the step shown in FIG. 20B, after an oxide film 209 for element isolation is deposited on the substrate, the well-known photolithography technique and etching technique are used,
The oxide film in the region where the transistor is formed in the oxide film 209 is removed. At this time, first, most of the removed portion of the oxide film 209 is removed by dry etching, and then the Si cap layer 2 is wet-etched so as not to damage the surface portion of the underlying Si cap layer 204.
04 is exposed.

Next, in a step shown in FIG. 20C, a gate oxide film 205 having a thickness of about 8 nm is formed on the exposed portion of the Si cap layer 205 by thermal oxidation. At that time, due to lattice relaxation, the SiGe channel layer 20 is formed.
In order to prevent the distortion of 3 from being eliminated, 75
Oxidation is performed at a low temperature of about 0 ° C. Next, after depositing a 200-nm-thick polycrystalline silicon film for a gate electrode on the substrate, B (boron) ion implantation is performed to make the polycrystalline silicon p-type. Next, after patterning the gate electrode by a known dry etching technique, BF is performed.
Ion implantation of ₂ (boron fluoride) is performed to form high-concentration p-type source and drain regions 207 and 208.

Further, in a cross section different from the cross section shown in FIG. 20C, high-concentration n-type impurity is ion-implanted to form a contact for fixing the substrate potential from the substrate surface side. Next, an interlayer insulating film 210 made of an oxide film having a thickness of 500 nm is deposited on the substrate. After that, heat treatment for activating impurities in the source and drain regions 207 and 208 is performed, and then the interlayer insulating film 21.
Contact holes reaching the source / drain regions 207 and 208 and the gate electrode 206 are formed at 0. Finally, the sputtering method is used, and Al of 800 nm thickness is formed on the substrate.
After depositing the alloy film, a plug and a wiring pattern for filling the contact hole are formed by using a well-known lithography and dry etching technique, and then a sintering process is performed in hydrogen, so that SiGe-
Form a pMISFET.

[0013]

However, in the above-mentioned conventional heterojunction field effect transistor, the band structure control technique using a mixed crystal material is not fully utilized. That is, in the above two conventional SiGe-pMISFETs, the high mobility of the light hole caused by the strain inherent in the SiGe channel layer is utilized. In either case, however, the Ge composition is increased in the traveling direction of the hole. The rate was constant, and the band control technology was not fully utilized in the traveling direction of the carrier.

It is an object of the present invention to positively utilize the facet planes generated during selective crystal growth and to fully utilize the band control technique using a mixed crystal material, so that the current can be generated at a higher speed. A heterojunction field effect transistor having high drivability is provided.

[0015]

A first semiconductor device of the present invention is a field effect transistor having a substrate, a semiconductor layer formed on the substrate, and a gate electrode formed on the semiconductor layer. And the semiconductor layer has a channel region located below the gate electrode, and a source region and a drain region located on both sides of the channel region, the cross section being parallel to the channel direction of the channel region. In, the energy level at the band edge where the carrier travels is inclined in the direction of accelerating the travel of the carrier in the non-biased state.

As a result, the carrier travels in the channel region parallel to the substrate surface and is accelerated by the electric field, so that a semiconductor device having a field effect transistor capable of high speed operation can be obtained.

The source region and the drain region are p-type regions, the channel region functions as a p-channel through which holes travel, and the energy level difference between the valence band edge and the vacuum level in the channel region is: Since the holes are reduced continuously or stepwise in the flowing direction, a semiconductor device including a p-channel field effect transistor capable of high speed operation can be obtained.

The channel region is formed of Si _1-x Ge _x (0
≦ x ≦ 1), and the Ge composition ratio x in the channel region is formed at the valence band edge by increasing continuously or stepwise in the hole flow direction. Holes can be more strongly confined in the hetero barrier, and a semiconductor device including a p-channel field effect transistor having a high current driving force can be obtained.

The source region and the drain region are n-type regions, the channel region functions as an n-channel through which electrons travel, and the energy level difference between the conduction band edge and the vacuum level in the channel region is The semiconductor device including the n-channel field effect transistor capable of high-speed operation can be obtained by increasing continuously or stepwise in the direction in which the current flows.

The channel region is formed by Si _1-y C _y (0 ≦
y <1), and the C composition ratio y in the channel region increases continuously or stepwise in the electron flow direction, so that the hetero barrier formed at the conduction band edge. It is possible to confine electrons more strongly in the semiconductor device, and a semiconductor device including a p-channel field effect transistor having a high current driving force can be obtained. A semiconductor device characterized by:

The channel region also contains a carrier impurity whose concentration changes continuously or stepwise in the direction of carrier flow, so that a semiconductor provided with a field effect transistor that operates at high speed by utilizing a built-in electric field. The device is obtained.

The semiconductor layer has a top surface narrower than the bottom surface,
It is in the shape of a partial cone having an inclined side surface existing between the bottom surface and the upper surface, and one of the source region and the drain region is located at substantially the center of the semiconductor layer, The other of the region and the drain region is located in the peripheral part of the semiconductor layer, and the channel region is located between the central part and the peripheral part, so that the mesa structure is used. A semiconductor device having a highly functional field effect transistor can be obtained.

The contour of the portion where the energy level of the band edge in which the carriers run in the channel region are equal is a slope substantially parallel to the side surface of the semiconductor layer having the shape of a partial cone, so that the epitaxial growth to the side is performed. Can be used to adjust the composition or dopant concentration to generate a built-in electric field.

It is preferable that the field effect transistor is a MIS type field effect transistor further having a gate insulating film interposed between the semiconductor layer and the gate electrode.

A second semiconductor device of the present invention has a substrate, a first semiconductor layer formed on the substrate, and a first gate electrode formed on the first semiconductor layer. A second field effect transistor including a first field effect transistor, the second field effect transistor having a second semiconductor layer formed on the substrate, and a second gate electrode formed on the second semiconductor layer. The first and second semiconductor layers each have a channel region located below the gate electrode, and a source region and a drain region located on both sides of the channel region. In the cross section parallel to the channel direction, the valence band edge is inclined in the direction to accelerate the traveling of holes in the non-biased state, and the conduction band edge is inclined in the direction to accelerate the electron's traveling in the non-biased state.

As a result, in the channel regions functioning as p-channel and n-channel parallel to the substrate surface, the migration of both holes and electrons is accelerated by the built-in electric field, so that a complementary field effect transistor capable of high-speed operation can be obtained. The provided semiconductor device can be obtained.

Each of the above channel regions is formed of Si _1-xy Ge _x.
It has a composition represented by C _y (0 ≦ x ≦ 1, 0 ≦ y <1), and the Ge composition ratio x and the C composition ratio y in each of the channel regions are as follows: The energy level difference from the level decreases continuously or stepwise in the hole flow direction, while the electron affinity at the conduction band edge in the channel region increases continuously or stepwise in the electron flow direction. By this adjustment, holes and electrons can be more strongly confined by utilizing the hetero barrier, and a semiconductor device having a complementary field effect transistor with high current driving capability can be obtained.

An active region provided on the surface of the substrate and an isolation region made of an insulator surrounding the active region are further provided, and one of the source region and the drain region of each of the semiconductor layers is provided with each of the above-mentioned respective regions. The semiconductor layer is located substantially in the center, the other of the source region and the drain region of each semiconductor layer is located in the peripheral portion of each semiconductor layer, and the channel region of each semiconductor layer is Since each is located between the central portion and the peripheral portion,
Similar to the transistor on the I substrate, the effect of reducing the parasitic capacitance can be obtained, so that a semiconductor device including a field effect transistor having a higher operating speed can be obtained.

A third semiconductor device of the present invention comprises a semiconductor substrate, an active region provided on the surface of the semiconductor substrate,
An isolation region formed of an insulator surrounding the active region, and a semiconductor layer formed by epitaxial growth from the active region over a part of the isolation region, the semiconductor layer,
At least a portion of which is interposed between the first impurity diffusion layer located directly above the active region, the second impurity diffusion layer located above the isolation region, and the first and second impurity diffusion layers; At least a portion of the channel region located above the isolation region.

Thus, the field effect transistor is formed by utilizing the semiconductor layer including the portion epitaxially grown from the upper surface of the active region and the portion epitaxially grown to the side of the active region and extending to above the isolation region.
Since at least part of the channel region of this field effect transistor is located on the isolation region, the SOI
Similar to the transistor on the substrate, the effect of reducing the parasitic capacitance with respect to the traveling of carriers of the field effect transistor can be obtained, and the semiconductor device including the field effect transistor having a high operating speed can be obtained.

In the cross section of the channel region parallel to the channel direction, the band edge where carriers travel is inclined in a direction that accelerates the travel of carriers in the non-biased state, so that the field effect transistor operates at a higher speed. A semiconductor device provided with is obtained.

The semiconductor substrate is a Si substrate, and the semiconductor layer is a central Si film epitaxially grown from the upper surface of the active region of the Si substrate and Si _1-x epitaxially grown from the side surfaces of the central Si film. Ge _x
(0 ≦ x ≦ 1), Si _1-y C _y (0 ≦ y <1) and Si
Compound semiconductor film having a composition represented by any one of _1-xy Ge _x C _y (0 ≦ x ≦ 1, 0 ≦ y <1), and outer Si epitaxially grown from the side surface of the compound semiconductor film. By including the film, carriers can be strongly confined in the hetero barrier formed at the valence band edge or the conduction band edge, or both, and a semiconductor including a field effect transistor having a high current driving force. The device is obtained.

The semiconductor layer further includes a Si cap layer epitaxially grown from the upper surface and side surfaces of the central Si film, the compound semiconductor film and the outer Si film, and a gate insulating film formed on the Si cap layer. Since it becomes possible to provide a gate insulating film having good characteristics by utilizing oxidation or oxidization and nitridation of the Si cap layer, a semiconductor device having a field effect transistor having better characteristics can be obtained. .

The method of manufacturing a semiconductor device according to the present invention comprises a step (a) of forming an isolation region made of an insulator surrounding the active region on a surface portion of a semiconductor substrate, and a semiconductor extending from the active region to the isolation region. A step (b) of selectively epitaxially growing the crystal layer, a step (c) of forming a gate electrode on the semiconductor crystal layer, and an impurity implantation into the semiconductor crystal layer using at least the gate electrode as a mask. , And a step (d) of forming first and second impurity diffusion layers.

By this method, a field effect transistor is formed by utilizing a semiconductor crystal layer composed of a portion epitaxially grown from the upper surface of the active region and a portion epitaxially grown laterally of the portion and extending to above the isolation region. Since at least a part of the channel region of this field effect transistor is located on the isolation region, S
Similar to the transistor on the OI substrate, the effect of reducing the parasitic capacitance with respect to the carrier travel of the field effect transistor can be obtained, and the semiconductor device including the field effect transistor having a high operating speed is formed.

The step (b) includes a sub-step (b1) of forming a first semiconductor film by epitaxial growth from the upper surface of the active region and a sub-step (b1) of epitaxial growth from the first semiconductor layer. Sub-step (b2) of forming a second semiconductor film made of a compound semiconductor that changes continuously or stepwise, and sub-step (b3) of forming a third semiconductor film by epitaxial growth from the second semiconductor layer. By including the above, it is possible to form a built-in electric field in the semiconductor crystal layer by utilizing the change in the composition or the impurity concentration, and thus it is possible to easily form the semiconductor device including the field effect transistor that operates at high speed. .

In the step (b), after the sub-step (b3), the upper portions of the entire first to third semiconductor films are removed until the upper surfaces of the first to third semiconductor films are exposed. A sub-step (b4), a sub-step (b5) of depositing a fourth semiconductor film on the upper surface and side surfaces of the planarized first to third semiconductor films, and By further including the sub-step (b6) of forming a gate insulating film on top, it becomes possible to provide a gate insulating film with good characteristics by utilizing oxidation or oxidization and nitridation of the fourth semiconductor film. Therefore, a semiconductor device having a field effect transistor with better characteristics can be obtained.

[0038]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) FIG.
(B) is a plan view showing the structure of a p-type field effect transistor (SiGe-pMISFET) having a SiGe / Si heterojunction, which is arranged in the semiconductor device of the first embodiment of the present invention, and a line Ib-Ib. FIG.

As shown in FIGS. 1A and 1B, a shallow trench isolation region (STI) 105, which divides the surface portion into a plurality of active regions, is formed on the surface portion of the n-type Si substrate 101.
Is provided. Then, the SiGe-p of this embodiment is
The MISFET includes a first quadrangular pyramid-shaped (a shape obtained by cutting an upper portion of a quadrangular pyramid) first epitaxial growth portion 151 (semiconductor layer, semiconductor) formed on two active regions 101 a and 101 b surrounded by a trench isolation region 105. A crystal layer) and a second epitaxial growth portion 152 having a shape of a partial quadrangular pyramid.

The first epitaxial growth portion 151 has a partial central pyramid-shaped first central Si film 102a occupying the central portion thereof.
And a first central Si film 102a formed on the side surface of the first central Si film 102a.
The SiGe film 103a, the first outer Si film 104a formed on the side surface of the first SiGe film 103a, and the first center S
i film 102a, first SiGe film 103a, and first outer side S
The i-film 104a is formed of the first Si cap layer 106a that covers the upper surface and the side surface of the i-film 104a. Each area 102a,
As will be described later, the side surfaces of 103a and 104a are inclined to match the facets during epitaxial growth.

Further, the second epitaxial growth portion 152
Is a partial central pyramid-shaped second central Si film 102b, a second SiGe film 103b formed on a side surface of the second central Si film 102b, and a second SiGe film 103.
a second outer Si film 104b formed on the side surface of b, a second central Si film 102b, a second SiGe film 103b, and a second Si cap layer 106b covering the upper surface and the side surface of the second outer Si film 104b. There is. Each area 1
The side surfaces of 02b, 103b, and 104b are inclined to match the facets during epitaxial growth, as described later.

The side surface and the upper surface of the first epitaxial growth portion 151 are covered with the first thermal oxide film 107a, and the upper surface and the side surface of the second epitaxial growth portion 152 are covered with the second thermal oxide film 107b. Further, an interlayer insulating film 112 is provided to cover the first thermal oxide film 107a and the second thermal oxide film 107b.

In the first epitaxial growth portion 151, a gate electrode 108 made of closed-ring polycrystalline silicon is formed on the first thermal oxide film 107a so as to surround the central Si portion 102a when viewed two-dimensionally. Has been. Then, the first central Si portion 102a and the first SiG
A portion of the e film 103a excluding a region below the gate electrode 108 and the entire first outer Si film 104a are doped with high-concentration p-type impurities (for example, boron). That is, the region of the first epitaxial growth portion 151 located inside the gate electrode 108 is the source region 109.
The region of the first epitaxial growth portion 151 located outside the gate electrode 108 is the drain region 11.
0, which is the gate electrode 1 of the first SiGe film 103a.
A region below 08 and in contact with the first Si cap layer 106a is a channel region 117. Further, a portion of the first thermal oxide film 107a located immediately below the gate electrode 108 functions as a gate insulating film.

Further, the source contact 113a reaching the source region 109 through the interlayer insulating film 112, the source wiring 113 connected to the source contact 113a, and the interlayer insulating film 112.
Drain contact 114a reaching the drain region 110 through the drain and the drain wiring 114 connected to the drain contact 114a
And a gate contact (not shown) that penetrates the interlayer insulating film 112 and reaches the gate electrode 108, and a gate wiring 115 connected to the gate contact. The ends of the wirings 113, 114, 115 are pads 113b, 114b, 115b, respectively. Each pad 113b, 114b, 115b is a connection portion of a plug for connecting the upper wiring layer and the wiring 116.

The entire second epitaxial growth portion 152 is a body contact region 119 for fixing the substrate potential, which contains a high concentration of n-type impurities. And the interlayer insulating film 1
A body contact 116a reaching the body contact region 119 through the second and the second thermal oxide films 107b and a body voltage supply wiring 116 connected to the body contact 116a are provided. Further, the end portion of the body wiring 116 serves as a pad 116b which is a connection portion of a plug for connecting the wiring layer of a higher layer to each wiring 116.

In the SiGe-pMISFET of this embodiment, when a negative bias voltage is applied to the gate electrode 108, the channel region 117, which is a region of the first SiGe film 103a that is in contact with the first Si cap layer 107a.
An inversion layer is formed in the hole, and the hole can travel.
Then, the high potential side voltage is applied to the source region 109,
When a low-potential-side voltage is applied to the drain region 110, the SiGe-pMISFET of the present embodiment has the source region 1
The semiconductor device operates as a p-type field effect transistor in which holes travel at high speed from 09 to the drain region 110.

Although not shown in FIGS. 1A and 1B, in the semiconductor device of this embodiment, SiG is used.
Semiconductor devices other than the e-pMISFET (for example, bipolar transistor, nMISFET, diode, capacitor, resistance element, etc.) are provided. Known structures of devices or structures of other embodiments of the present invention can be applied to these structures.

Here, the SiGe-pMIS of the present embodiment is used.
The FET has the following features in addition to having the mesa structure as described above.

2A and 2B are a plan view and a cross-sectional view (IIb-II) showing changes in the portion of the first epitaxial growth portion 151 excluding the first Si cap layer 107a during growth (IIb-II).
It is a cross section indicated by line b). FIG. 3 is a view showing a Ge composition ratio profile and a band state in the IIb-IIb line cross section of the upper surface portion of the first epitaxial growth portion 151 (excluding the first Si cap layer 107a).

As shown in FIG. 3, the first SiGe film 103 is formed.
In a, the Ge composition ratio is 0 in the portion in contact with the first central Si film 102a, and the Ge composition ratio is 20% in the portion in contact with the outer Si film 104a.
From the portion in contact with the central Si film 102a to the first outer Si film 1
It increases almost continuously up to the portion in contact with 04a. That is, the energy level difference between the valence band edge and the vacuum level in the first SiGe film 103a is the first central Si film 10
A built-in electric field for accelerating the traveling of holes is formed almost continuously from the portion in contact with 2a to the portion in contact with the first outer Si film 104a. In this example, the band offset amount at the valence band edge at the interface between the first SiGe film 103a and the first outer Si film 104a is about 130.
It is meV. In FIG. 3, the Si of the present embodiment is
SiG with the same shape as Ge-pMISFET
The valence band edge of the e film having a uniform Ge composition ratio (20%) is shown by a dotted line. 2 (a) and 2 (b)
The broken line shown in the first SiGe film 103a is a facet at the time of epitaxial growth and exemplifies a surface (contour) drawn by a portion having the same Ge composition ratio.

According to the SiGe-pMISFET of the present embodiment, in the channel region 117 formed in the first SiGe film 103a, the Ge composition ratio is the first central Si film 1
02a from the portion (0%) in contact with the first outer Si film 104
Since it increases almost continuously up to the portion (20%) in contact with a, the change in energy level at the edge of the valence band at the time of applying a bias is smaller than that of the one having a uniform Ge composition (see the dotted line). It becomes steeper, and the effect of accelerating the hole becomes higher. Therefore, a pMISFET with high speed and high driving force can be obtained.

Further, the SiGe-pM in this embodiment is
In the ISFET, the Ge composition ratio in the first SiGe film 103a is changed from 0% to 20% (Ge
The average composition ratio of Si is about 10%), so that the first composition is about the same as a SiGe film having a uniform Ge composition of 10%.
The strain of the entire SiGe film 103a can be reduced.
Therefore, the SiGe-p MISFET in the present embodiment
As a result, the thermal stability can be improved.

Further, as shown in FIG. 1B, the channel region 117 of the SiGe-p MISFET of this embodiment.
Since the drain region 110 and the drain region 110 are formed on the shallow trench isolation region 105, they have an almost SOI structure, and the parasitic capacitance can be reduced to achieve higher speed.

FIG. 4 shows this embodiment and the conventional SiGe-.
It is a figure which shows the simulation result of the current cutoff frequency-gate voltage characteristic of pMISFET. FIG. 5 (a),
(B) shows, in order, the present embodiment and the conventional SiG.
It is a figure which shows the simulation result of the drain current-drain voltage characteristic of e-pMISFET. 4 and 5
In the simulation for obtaining the characteristics shown in (a) and (b), the present embodiment and the conventional SiGe-pMI are used.
It is assumed that the SFETs have the same gate length and gate width. Further, as the conventional SiGe-p MISFET, one having a graded Ge composition shown in FIGS. 19A and 19B is assumed.

As shown in FIG. 4, the SiGe of this embodiment is
-PMISFET is a conventional SiGe-pMISFET
It can be seen that the current cutoff frequency f _T is higher than that of Further, as shown in FIGS. 5A and 5B, the SiGe-pMISFET of the present embodiment is a conventional SiG.
It can be seen that it has a higher current driving force than the e-pMISFET. That is, the SiGe of the present embodiment
-PMISFET is a conventional SiGe-pMISFET
It is possible to exhibit excellent high-frequency characteristics and current driving force as compared with.

Next, SiGe-having the structure shown in FIG.
A method of manufacturing the pMISFET will be described. Figure 6
(A) -FIG.9 (b) are SiGe-PMI of this embodiment.
6A and 6B are a plan view and a cross-sectional view showing the manufacturing process of the SFET.

First, in the steps shown in FIGS. 6 (a) and 6 (b),
The main surface is (0
A trench (not shown) having a depth of about 400 nm is formed in the region where the trench isolation film is to be formed on the n-type Si substrate 101 which is the (01) plane. And CVD and CMP
(Chemical-Mechanical Polishing) is performed to fill the silicon oxide film in the trench to form a trench isolation film 105 surrounding the active region. Here, FIGS. 6A and 6B exemplify a first active region 101a which is a MISFET formation region and a second active region 101b which is a body contact formation region. In the present embodiment, the first active region 101a is a square having a side length of 5 μm, and the second active region 101b is a square having a side length of 2 μm.

Next, in the steps shown in FIGS. 7 (a) and 7 (b),
After cleaning the exposed surface of the Si substrate 101, UH
The first active region 101a is formed on the first active region 101a by the V-CVD method.
Central Si film 102a, first SiGe film 103a and first Si film
The outer Si film 104a and the second central Si film 102b, the second SiGe film 103b, and the second outer Si film 104b are selectively epitaxially grown on the second active region 101b. At this time, by selecting an appropriate crystal growth condition, the single crystal Si is first formed on the first active region 101a and the second active region 101b without forming a polycrystalline Si film on the trench isolation film 105. A film can be formed. The process of crystal growth at that time will be described below.

At the initial stage of epitaxial growth, a single crystal Si film having a (001) plane is grown on the first and second active regions 101a and 101b, and
The single crystal Si film is laterally grown on the trench isolation film 105 from the side surface of the single crystal Si film grown on the first and second active regions 101a and 101b. Then, the side surface of the single crystal Si film is the closest packed {111} plane (facet plane)
And four surfaces inclined to the film surface, (1 1 1)
Plane, (1-1 1) plane, and (-1-1 1) plane (-1 11 1) plane appear. Finally, as shown in FIG. 7B, single crystal Si
The film (first and second central Si films 102a and 102b) is a partial quadrangular pyramid (a shape in which the head of the quadrangular pyramid is cut off) having a substantially flat upper surface and four inclined side surfaces. Single crystal Si
Si ₂ H ₆ (disilane) is supplied as a source gas for film growth at a flow rate of 20 (ml / min), and the growth temperature is 600 ° C. The growth rate of the single crystal Si film is about 8 nm / min in the <001> direction in which the top surface grows, and about 2 nm / m in the <111> direction in which the facet plane grows.
in. First and second central Si films 102a and 102b
Has a thickness of about 20 nm.

Next, when a single crystal SiGe film is epitaxially grown on the partial quadrangular pyramid-shaped single crystal Si films (first and second central Si films 102a and 102b), the upper surface ((001) plane of the partial quadrangular pyramid is formed. ) Has a higher growth rate than the side surface ({111} plane (facet plane)).
The Ge film outline gradually approaches a perfect quadrangular pyramid. Then, on the second active region 101b having a small area, the single crystal SiGe film (second SiGe film 1) whose outer shape is a complete quadrangular pyramid is formed.
03b) is formed. In the present embodiment, the growth of the single crystal SiGe film is stopped while the outer shape of the first SiGe film 103a formed on the first active region 101a is a partial quadrangular pyramid.

The growth of the SiGe films 103a and 103b is
Si 2 and Si ₂ are used as source gases for Si and Ge, respectively.
Using H ₆ (disilane) and GeH ₄ (germane),
The flow ratio of germane to the entire source gas is changed substantially continuously so that the Ge composition ratio changes from 0% to 20% in a substantially linear manner. SiGe with a Ge composition ratio of 20%
When growing the film, Si ₂ H ₆ (disilane) and G
The flow rate of eH ₄ (German) is 20 (ml / m 2) respectively.
in), 40 (ml / min). Therefore, the growth temperature was set to about 600 ° C., and the flow rate of disilane was set to 20 (ml / mi).
n), and set the flow rate of germane to 0 (ml / min)
To 40 (ml / min) almost continuously. At this time, the growth rate of the single crystal SiGe film is about 40 nm / min in the <001> direction in which the upper surface grows, and about 10 nm in the <111> direction in which the facet surface grows.
nm / min. The thickness of the first SiGe film 103a is about 150 nm. The second SiGe film 103
After the outer shape of b becomes a nearly complete quadrangular pyramid, only the facet surface grows. The broken line shown in FIG. 7B indicates the profile of the growth surface of the single crystal SiGe film at each time, that is, the region of the same Ge composition ratio.

Next, the first and second SiGe films 103a, 103
A single crystal Si film is epitaxially grown on 03b. At this time, since the outer shape of the first SiGe film 103a is a partial quadrangular pyramid, the growth proceeds on both the upper surface and the facet surface. Then, finally, on the first SiGe film 103a, a single crystal Si film (first outer S
The i-film 104a) is formed. In contrast, the second SiG
Since the outer shape of the e film 103b is a substantially complete quadrangular pyramid, a single crystal Si film (second outer Si film 104b) having a complete conical contour line due to growth on the facet surface is formed on the second SiGe film 103b. Will grow up. Finally, a substantially complete quadrangular pyramid-shaped single crystal body having a height of about 1 μm is formed on the first active region 101a.

When growing the single crystal Si film and the single crystal SiGe film, it is desirable to add a small amount of Cl ₂ gas in order to enhance the selectivity. In addition, the above single crystal Si
No intentional doping is performed in the epitaxial growth of the film and the single crystal SiGe film.

Next, in the steps shown in FIGS. 8 (a) and 8 (b),
By CMP, the upper portions of the two crystal-grown quadrangular pyramid-shaped single crystals (see FIG. 7B) are removed to form a partial quadrangular pyramid.

After that, by UHV-CVD again, the first
Central Si film 102a, first SiGe film 103a and first Si film
The first Si cap layer 106a having a thickness of about 5 nm that covers the upper surface and the side surface of the partial quadrangular pyramid formed of the outer Si film 104a.
And the second central Si film 102b and the second SiGe film 103b.
And a second Si cap layer 106b having a thickness of about 5 nm, which covers the upper surface and the side surface of the partial quadrangular pyramid made of the second outer Si film 104b, is epitaxially grown. This allows
A relatively large partial pyramidal first epitaxial growth portion 151 is formed on the first active region 101a, and a relatively small partial pyramid second epitaxial growth portion 152 is formed on the second active region 101b. Is formed.

At that time, the first and second Si cap layers 106 are formed.
a and 106b selectively grow only on each partial quadrangular pyramid. In addition, the first and second Si cap layers 106a and 10a
The growth condition of 6b is that the first and second central Si films 102a, 1a
This is the same as the growth condition of 02b.

Next, the first and second Si cap layers 106.
The surface portions of a and 106b are thermally oxidized to form first and second thermal oxide films 107a and 107b, respectively. The oxidation temperature at this time is 750 ° C., and the first and second thermal oxide films 10 are
The film thickness of 7a and 107b is about 5 nm. On the other hand, the first
With the formation of the second thermal oxide films 107a and 107b,
The thickness of the second Si cap layers 106a and 106b is about 3
nm.

Next, in the steps shown in FIGS. 9 (a) and 9 (b),
A polycrystalline silicon film with a thickness of about 200 nm is deposited on the substrate.
After being deposited, boron ions (B₊ )
And then poly-crystallized by dry etching.
By patterning the silicon film, the first thermal oxide film 107a is formed.
Located above the inner end of the first SiGe film 103a
The gate electrode 10 having a substantially square closed ring shape is formed on the region to be formed.
8 is formed. The gate length of the gate electrode 108 is about 0.1.
μm. Next, using the gate electrode 108 as a mask,
First epitaxial growth portion 151 (first central Si film 10
2a, the first SiGe film 103a, and the first outer Si film 10
4a), boron fluoride ion (BF ₂ ⁺)
Pressure is 30 keV, Dose is 4 × 10¹⁵cm^-2Under the conditions
inject. By this ion implantation, the first epitaxial
A source region is formed inside the gate electrode 108 of the growth portion 151.
109 is formed, and the first epitaxial growth portion 151
A drain region 110 is formed outside the gate electrode 108.
To be done.

Next, the first epitaxial growth portion 152
In the (second central Si film 102b, second SiGe film 103b, and second outer Si film 104b), arsenic ions (As
⁺ ), Acceleration voltage is 40 keV, and dose is 4 × 10 ^{15.
Implanted under} the condition of cm ⁻² , the body contact region 119
To form.

After that, an interlayer insulating film 112 having a film thickness of about 500 nm is deposited on the substrate, contact holes are formed through the interlayer insulating film 112, and then the source region 109, the drain region 110 and the body contact region 119 are implanted. Heat treatment is performed to activate the generated impurities. Further, after depositing an Al alloy film (aluminum alloy film) on the substrate, the Al alloy film is patterned by dry etching to form the source contact 113a, the source wiring 113 connected thereto, and the drain contact 114.
a and the source wiring 114 connected to the gate contact 115a and the gate wiring 115 connected to the gate contact 115a
And the body contact 116a and the body voltage supply wiring 116 connected thereto are formed. Finally, by performing sintering in a hydrogen atmosphere, the SiG shown in FIG.
The e-pMISFET is almost completed.

According to the method of manufacturing the SiGe-p MISFET of the present embodiment, the facet formed on the side surface during the epitaxial growth of the crystal is used, as shown in FIG.
As shown in (b), the Ge composition ratio of the first SiGe film 103a can be changed in a direction parallel to the main surface of the Si substrate 101. As a result, the energy level at the valence band edge of the channel region 117 can be made to have an inclination, so that the holes traveling below the gate electrode 108 are accelerated. Therefore, high-speed operation and high drive of the SiGe-p MISFET can be realized.

(Second Embodiment) In this embodiment, an example in which the present invention is applied to a semiconductor device having a SiC-nMISFET will be described.

Also in this embodiment, the SiC-nMIS is used.
The overall shape of the FET is as shown in FIGS. However, the SiC-nMISFE of the present embodiment
At T, the first and second SiGe films 103 shown in FIG.
Instead of a and 103b, the first and second Si _1-y C _y films (0
≦ y <1) is provided. In addition, the Si substrate 101 shown in FIG.
8 and the drain region 109 are doped with high-concentration n-type impurities, and the body contact region 119 is doped with p-type impurities. Also in this embodiment, the gate length is about 0.1 μm.

In the semiconductor device of this embodiment, semiconductor devices other than the SiC-nMISFET (for example, bipolar transistor, pMISFET, diode, capacitor, resistance element, etc.) are provided.
Known structures of devices or structures of other embodiments of the present invention can be applied to these structures.

FIGS. 10A and 10B show S of the present embodiment.
First epitaxial growth portion 16 of iC-nMISFET
3A and 3B are a plan view and a cross-sectional view (cross-section indicated by line Xb-Xb) showing changes during growth of No. 1 (excluding the first Si cap layer). Figure 1
FIG. 1 is a diagram showing a profile of the C composition ratio and a band state in the Xb-Xb line cross section of the upper surface portion of the first epitaxial growth portion 161 (excluding the first Si cap layer).

As shown in FIG. 11, in the first Si _1-y C _y film 163a, the C composition ratio is 0 in the portion in contact with the first central Si film 102a, and the C composition ratio in the portion in contact with the outer Si film 104a. Is 2% and the C composition ratio is from the portion in contact with the first central Si film 102a to the first outer Si film 10
It increases almost continuously up to the portion in contact with 4a. That is, the energy level difference (electron affinity) between the conduction band edge and the vacuum level in the first Si _1-y C _y film 163a is the first
From the portion in contact with the central Si film 102a to the first outer Si film 1
A built-in electric field for accelerating the traveling of electrons is formed almost continuously increasing to the portion in contact with 04a. In this example, the first Si _1-y C _y film 163a and the first outer Si
The band offset amount at the conduction band edge at the interface with the film 104a is about 70 meV. Note that, in FIG. 11, the conduction band edge of the Si _1-y C _y film having a uniform C composition ratio (2%) while having the same shape as the SiC-nMISFET of the present embodiment is shown by a dotted line. In addition, FIG.
The broken lines shown in the first Si _{1- y} C _y film 163a of (a) and (b) are facets at the time of epitaxial growth, and
The surface (outline) drawn by the portions having the same composition ratio is illustrated.

According to the SiC-nMISFET of this embodiment, in the channel region formed in the first Si _1-y C _y film 163a, the C composition ratio is the first central Si film 102a.
From the portion in contact with the first outer Si film 104a (2%) to almost continuously increase.
The change in energy level at the conduction band edge becomes steeper by the built-in electric field as compared with the one having a uniform C composition (see the dotted line), and the effect of accelerating electrons is enhanced. Therefore, an nMISFET that operates at high speed and has a high current driving force can be obtained.

In addition, the SiC-nMI in this embodiment
In the SFET, since the C composition ratio in the _first Si _1-y C _y film 163a is changed from 0% to 2% (the average composition ratio of C is about 1%), the C composition ratio is 1%. composition to the same degree as Si _1-y C y layer having a first 1Si _1-y
The strain of the entire C _y film 163a can be reduced. Therefore, the SiC-nMISFET according to the present embodiment can improve the thermal stability.

Further, similarly to the SiGe-p MISFET of the first embodiment shown in FIG. 1B, the S of the present embodiment is S.
Since the channel region and the drain region of the iC-nMISFET are formed on the shallow trench isolation region, the iC-nMISFET has a substantially SOI structure, and the parasitic capacitance can be reduced to achieve higher speed.

FIG. 12 shows this embodiment and a conventional SiC-
It is a figure which shows the simulation result of the current cutoff frequency-gate voltage characteristic of nMISFET. FIG. 13 (a),
(B) shows the SiC of the present embodiment and the conventional SiC, respectively.
FIG. 7 is a diagram showing a simulation result of drain current-drain voltage characteristics of an nMISFET. 12 and 1
In the simulation for obtaining the characteristics shown in FIGS. 3A and 3B, the present embodiment and the conventional SiC-nMI are used.
It is assumed that the SFETs have the same gate length and gate width. Further, as a conventional SiC-nMISFET, a SiGe-pMISF shown in FIGS.
Similar to ET, one having a graded C composition is assumed.

As shown in FIG. 12, the SiC of this embodiment is
It can be seen that the -nMISFET has a higher current cutoff frequency f _T than the conventional SiC-nMISFET. Further, as shown in FIGS. 13A and 13B, the SiC-nMISFET of the present embodiment is a conventional SiC-nMISFET.
It can be seen that it has a higher current driving force than the nMISFET. That is, the SiC-nM of the present embodiment
The ISFET can exhibit excellent high frequency characteristics and current driving force as compared with the conventional SiC-pMISFET.

Next, the SiC-nMISFE of this embodiment is used.
A method of manufacturing T will be described. SiC- of this embodiment
The nMISFET is the SiGe-pMIS of the first embodiment.
The main difference from the FET is that the Si _1-y C _y film is used as the semiconductor film forming the channel region in place of the SiGe film, so the conditions for forming the Si _1-y C _y film are particularly detailed. explain. The impurities introduced into each part are
However, the specific description thereof will be omitted. Also, the description of the body contact region is omitted.

The exposed surface of the Si substrate was washed.
Then, the first active region is formed on the first active region by the UHV-CVD method.
Central Si film 102a, first Si_1-y C_y The membrane 163a and
Selectively epitaxially grow the first outer Si film 104a
Let At this time, select appropriate crystal growth conditions
As a result, a polycrystalline Si film or a polycrystalline Si film is formed on the trench isolation film.
_1-y C_y Single crystal Si film or single crystal without forming a film
Si_1-y C_y A film can be formed.

The source gas for growing the single crystal Si film and the growth temperature are the same as those in the first embodiment. Also, the first central S
The thickness of the i-film 102a and the first outer Si film 104a is also the first
It is similar to the embodiment.

The growth of the _first Si _1-y C _y film 163a is performed by S
Si ₂ H ₆ was used as the source gas for i and C, respectively.
Using (disilane) and SiH ₃ CH ₃ (monomethylsilane), the flow rate ratio of monomethylsilane to the entire source gas is changed almost continuously so that the C composition ratio changes from 0% to 2% in a substantially linear manner. . C composition ratio is 2
% Of Si _1-y C _y film, the flow rates of Si ₂ H ₆ (disilane) and SiH ₃ CH ₃ (monomethylsilane) are 20 (ml / min) and 4 (ml / min), respectively.
min). Therefore, the growth temperature was fixed at about 500 ° C., the flow rate of disilane was fixed at 20 (ml / min), and the flow rate of monomethylsilane was changed from 0 (ml / min) to 4 (ml).
/ Min) changes almost continuously. At this time, the growth rate of the single crystal Si _{1- y} C _y film is such that the top surface grows <0.
It is about 2 nm / min in the 01> direction and about 0.5 nm / min in the <111> direction in which the facet plane grows. The thickness of the _first Si _1-y C _y film 163a is about 150.
nm. Similar to the single crystal SiGe film (see the broken line in FIG. 7B) in the first embodiment, the single crystal Si _1-y C _y film at each time has a partial quadrangular pyramid shape.

Next, an outer Si film is epitaxially grown on the first Si _1-y C _y film 163a. The growth conditions and the thickness of the outer Si film at this time are the same as those in the first embodiment.

Even in this embodiment, intentional doping is not performed in the epitaxial growth of the single crystal Si film and the single crystal Si _1-y C _y film.

Then, as in the first embodiment, CMP is performed.
Processing, epitaxial growth of a Si cap layer, formation of a gate electrode, and implantation of impurity ions into the source region, drain region and body contact region. Furthermore, after forming the interlayer insulating film, each contact and wiring, sintering is performed in a hydrogen atmosphere, and thereby the SiC-nMISFET of this embodiment is almost completed.

According to the method of manufacturing the SiC-nMISFET of the present embodiment, by utilizing the facets formed on the side faces during the epitaxial growth of the crystal, FIG.
As shown in (b), in the direction parallel to the main surface of the Si substrate,
The C composition ratio of the _first Si _1-y C _y film 163a can be changed. As a result, the energy level at the conduction band edge of the channel region can be made to have a gradient, so that the electrons traveling below the gate electrode are accelerated. Therefore, S
It is possible to realize high-speed operation and high driving of the iC-nMISFET.

(Third Embodiment) In this embodiment, the present invention is applied to SiGeC-pMISFET and SiGeC.
An example applied to a semiconductor device having a SiGeC-cMIS device composed of -nMISFET will be described.

Also in this embodiment, SiGeC-pM is used.
The overall shapes of the ISFET and the SiGeC-nMISFET are as shown in FIGS. 1 (a) and 1 (b). However, the SiGeC-pMISFET and Si of the present embodiment are
In the GeC-nMISFET, the first and the first shown in FIG.
Instead of the second SiGe films 103a and 103b, first and second Si _1-xy Ge _x C _y films (0 ≦ x ≦ 1, 0 ≦ y <1)
Is provided. In addition, SiGeC-pMISFET
Are provided on the n-well in the Si substrate 101 shown in FIG. 1, and the SiGeC-n MISFET is provided on the p-well. The conductivity type of the dopant of each part of the SiGeC-pMISFET is the SiGe-pMI of the first embodiment.
It is similar to the SFET, and the conductivity type of the dopant of each part of the SiGeC-nMISFET is the SiGe of the first embodiment.
-The conductivity type is opposite to that of the dopant in each part of the pMISFET. Also in this embodiment, the gate length is about 0.1.
μm.

In the semiconductor device of this embodiment, semiconductor devices other than the SiGeC-cMIS device (for example, bipolar transistors, diodes, capacitors, resistance elements, etc.) are provided. Known structures of devices can be applied to these structures.

SiGeC has a lattice constant smaller than that of Si by adjusting the Ge composition ratio and the C composition ratio.
It can be subjected to tensile strain on the substrate. In that case, a hetero-barrier capable of confining electrons and holes is formed at both the conduction band edge and the valence band edge.

FIG. 14 shows the Si / SiGeC of this embodiment.
FIG. 4 is an energy band diagram showing a band edge structure in a laminated structure of / Si. As shown in the figure, heterobarriers capable of confining electrons and holes are formed at both the conduction band edge and the valence band edge. Therefore, the first Si _1-xy Ge _x C _y film which is to be replaced with the _first SiGe film 103a shown in FIG.
It can be used as a channel layer of nMISFETs and SiGeC-pMISFETs, which can simplify the structure of SiGeC-cMIS devices using heterojunctions.

FIG. 15 is a diagram showing the dependence of the band offset amount ΔEv at the valence band edge shown in FIG. 14 on the Ge and C composition ratio. In FIG. 15, the broken line shows the range of the Ge and C composition ratios in which the tensile strain and the compressive strain are equal,
The alternate long and short dash line shows the range of Ge and C composition ratios where the band offset amount ΔEv at the valence band edge is equal.

FIG. 16 is a graph showing the dependence of the band offset amount ΔEc at the conduction band edge shown in FIG. 14 on the Ge and C composition ratio. In FIG. 16, the broken line shows the range of the Ge and C composition ratios in which the tensile strain and the compressive strain are the same, and the alternate long and short dash line shows the range of the Ge and C composition ratios in which the band offset amount ΔEc at the conduction band edge is the same.

For example, the Ge and C compositions of the Si _1-xy Ge _x C _y film are represented by the starting points (Ge:
Change from 0%, C: 0%) to the end point (Ge: 5%, C: 3%). That is, in the structure shown in FIG.
The Ge composition ratio and the C composition ratio of the SiGeC film that replaces the SiGe film 103a are set to 0% and 0%, respectively, in the portions in contact with the first central Si film 102a.
The band offset amount ΔEv at the valence edge is 0 meV by setting 5% and 3% respectively in the portions in contact with 4a.
To about 90 meV, the band offset amount ΔEc at the conduction band edge increases from 0 meV to about 50 meV. In other words, as described in the first and second embodiments, both the valence band edge and the conduction band edge have inclinations for accelerating holes and electrons, respectively. Therefore,
With the SiGeC-cMIS device of this embodiment, a cMIS device that operates at high speed and has a high current driving force can be obtained.

Next, the SiGeC-cMIS of this embodiment is used.
A method of manufacturing the device will be described. S of this embodiment
The iGeC-cMIS device is the SiG of the first embodiment.
The main difference from the e-p MISFET is that the semiconductor film forming the channel region is replaced with SiGe film instead of SiGe film.
_{Since the 1-xy} Ge _x C _y film (0 ≦ x ≦ 1, 0 ≦ y <1) is used, the conditions for forming the Si _1-xy Ge _x C _y film will be described in detail. The impurities introduced into each part are the same as those in the first embodiment in SiGeC-pMISFET, and have the opposite conductivity type to those in the first embodiment in SiGeC-nMISFET, but a specific description thereof will be given. Omit it. Also, the description of the body contact region is omitted.

In this embodiment, the n well and the p well are formed by implanting impurity ions into the Si substrate. Then, SiGeC-pMISF is formed on the n-well.
ET is formed, and SiGeC-nMIS is formed on the p-well.
Form the FET.

The exposed surface of the Si substrate was cleaned.
Then, each first active region of each well is processed by the UHV-CVD method.
A first central Si film, a first Si film_1-xy Ge_x C_y film
And selectively epitaxially grow the first outer Si film.
It At this time, by selecting appropriate crystal growth conditions,
A polycrystalline Si film or a polycrystalline Si film on the trench isolation film._1-x-
y Ge_x C_y Without forming a film, a single crystal Si film or a single crystal film is formed.
Crystal Si_1-xy Ge_x C _y A film can be formed.

The source gas for growing the single crystal Si film and the growth temperature are the same as those in the first embodiment. Also, the first central S
The film thicknesses of the i film and the first outer Si film are similar to those in the first embodiment.

Si_1-xy Ge_x C_y The film growth is Si,
Si is used as a source gas for Ge and C, respectively.₂ H
₆ (Disilane), GeH_Four (German) and SiH₃ 
CH ₃ (Monomethylsilane), Ge composition ratio is 0%
From 5% to 5%, the C composition ratio changes from 0%
The whole source gas so that it changes almost linearly up to 3%
The flow ratio of germane and monomethylsilane to
Change continuously. Ge composition ratio is 5% and C composition ratio is 3
% Si_1-xy Ge_x C_y When growing the film, Si₂ 
H₆ (Disilane), GeH_Four (German) and SiH
₃ CH₃ The flow rate of (monomethylsilane) is 20 each.
(Ml / min), 10 (ml / min) and 6 (ml
/ Min). Therefore, the growth temperature is set to about 500 ° C.
Fix the flow rate of disilane to 20 (ml / min) and
Leman flow rate from 0 (ml / min) to 10 (ml / m)
in) to change almost continuously until monomethylsilane
Flow rate from 0 (ml / min) to 6 (ml / min)
Change almost continuously. At this time, single crystal Si_1-xy 
Ge_x C_y The growth rate of the film is such that the top surface grows <001>.
Direction is about 0.4 nm / min, and the facet surface is
About 0.1 nm / min in the growing <111> direction
It 1st Si_1-xy Ge_x C_y The film thickness is about 150n
m.

Next, on the first Si _1-y C _y film, the outside S
The i film is epitaxially grown. The growth conditions and the thickness of the outer Si film at this time are the same as those in the first embodiment.

Also in this embodiment, intentional doping is not performed in the epitaxial growth of the single crystal Si film and the single crystal Si _1-y C _y film.

After that, each MI is the same as in the first embodiment.
In the SFET, processing by CMP, epitaxial growth of a Si cap layer, formation of a gate electrode, and implantation of impurity ions into the source region, drain region and body contact region are performed. Furthermore, an interlayer insulating film,
After forming each contact and wiring, sintering is performed in a hydrogen atmosphere to obtain Si of the present embodiment.
The GeC-cMIS device is almost completed.

According to the method of manufacturing the SiGeC-cMIS device of the present embodiment, by using the facets formed on the side faces during the epitaxial growth of the crystal, S
In the direction parallel to the main surface of the i substrate, the first Si _1-xy Ge _x C
The Ge composition ratio and the C composition ratio of the _y film can be changed. As a result, the energy levels at both the valence band edge and the conduction band edge of the channel region can be made to have an inclination, so that holes and electrons running below the gate electrode are accelerated. Therefore, high-speed operation and high drive of the SiGeC-cMIS device can be realized.

(Other Embodiments) In the first to third embodiments, the first active region which is the transistor formation region is assumed to be square, but the planar shape of the active region in which the MISFET of the present invention is formed is However, the present invention is not limited to such an embodiment. For example, the planar shape may be rectangular or any other shape.

Further, in the first to third embodiments,
The UHV-CVD method was used as the crystal growth method.
An LP-CVD method may be used instead of the V-CVD method.

In the course of crystal growth, a single crystal film (single crystal Si film, single crystal SiGe film, single crystal SiC film,
It does not matter whether the single crystal SiGeC film) is formed in a substantially complete pyramid shape or remains in a partial pyramid shape. Therefore, the single crystal film may be a partial quadrangular pyramid.

Furthermore, the epitaxial growth portions 151, 1
52 does not have to be a cone, and may be, for example, a prism or a cylinder. In each of the above-described embodiments, since the Si substrate whose main surface is the (001) plane is used, the {111} plane which is the facet surface appears, and the epitaxial growth is performed only in a cone shape. That is, even when the epitaxial growth is isotropic,
When growing laterally, the composition of the epitaxial growth portion can be changed in a direction parallel to the substrate surface, and in that case, the same effect as each of the above embodiments can be exhibited.

Further, in each of the embodiments, the entire source region is constituted only by the central Si film, and only the channel region and the drain region (part) have the S composition having the graded composition.
It is composed of an iGe film, a Si _1-y C _y film, or a SiGeC film. However, a SiGe film, a Si _1-y C _y film, or a Si film in which a part of the source region (outer peripheral portion) has a graded composition
It may be composed of a GeC film. In addition, only a part of the channel region (portion in contact with the drain region) has a graded composition SiGe film, Si _1-y C _y film or SiGe film.
It is composed of C film, and the other part of the channel region is central Si.
It may be constituted by a film. in short,
If a built-in accelerating electric field with a graded composition is formed in the channel region, the same effect as each embodiment of the present invention can be obtained.

The change in Ge composition ratio and C composition ratio in the graded composition structure is not necessarily continuous.
Even with a stepwise change, it is possible to obtain the same effects as those of the above embodiments.

[0113] Further, in the first to third embodiments, the channel layer SiGe film, is constituted by Si _1-y C y or SiGeC film, and crystal growth channel layer in Si, in-situ during the By changing the impurity concentration by doping, a built-in accelerating electric field due to the change in impurity concentration can be created in the channel region, and therefore the same effect as each of the above embodiments can be obtained. The acceleration electric field due to the change in the impurity concentration is set to G in the above-described embodiments.
By combining it with a change in the composition ratio of e or C, a more remarkable effect can be obtained.

In each of the above-mentioned embodiments, the gate insulating film is made of a thermal oxide film, but the gate electrode structure may be another structure such as a Schottky structure instead of the structure of each embodiment.

Further, the gate electrode may be composed of a metal film other than the polycrystalline silicon film, a polycide film, or a polymetal film.

MISFET in Each Embodiment of the Present Invention
In the above, the gate electrode does not need to have a closed ring shape, and may have an open ring shape or a linear shape. In that case, for example, the first epitaxial growth portion 151 shown in FIG.
By removing both the upper and lower sides, it is possible to provide two field effect transistors whose main region is the source region in the central Si film 102 in the cross section shown in FIG.

As the semiconductor film to be epitaxially grown, a III-V group compound semiconductor film based on a GaAs substrate, an InP substrate, a GaN substrate or the like is used in addition to the SiGe film, the Si _1-y C _y film and the SiGeC film. Can
Even in that case, the same effect as each of the above-described embodiments can be exhibited by forming the graded composition structure by using the facets that appear during crystal growth.

[0118]

According to the semiconductor device of the present invention, it is provided with a field effect transistor for accelerating carriers by a built-in electric field by inclining the energy level of the valence band edge or the conduction band edge in the direction parallel to the substrate. Therefore, high-speed operation of the field effect transistor can be realized.

[Brief description of drawings]

1A and 1B are a plan view and a cross-sectional view taken along line Ib-Ib showing a structure of a SiGe-p MISFET arranged in the semiconductor device of the first embodiment.

2 (a) and 2 (b) are a plan view and a cross-sectional view taken along line IIb-IIb showing changes in growth of the first epitaxial growth portion (excluding the first Si cap layer).

FIG. 3 is a diagram showing a Ge composition ratio profile and a band state in a IIb-IIb line cross section of an upper surface portion of a first epitaxial growth portion (excluding a first Si cap layer).

FIG. 4 is a first embodiment and a conventional SiGe-pMIS.
It is a figure which shows the simulation result of the current cutoff frequency-gate voltage characteristic of FET.

5A and 5B are diagrams showing simulation results of drain current-drain voltage characteristics of the first embodiment and the conventional SiGe-p MISFET.

6A and 6B are a plan view and a cross-sectional view taken along line VIb-VIb showing a step of forming a trench isolation film in the manufacturing process of the semiconductor device of the first embodiment.

7A and 7B are a plan view and a cross-sectional view taken along the line VIIb-VIIb showing an epitaxial growth step in the manufacturing process of the semiconductor device of the first embodiment.

8A and 8B are a plan view and a cross-sectional view taken along the line VIIIb-VIIIb showing a step of forming a Si cap layer in the manufacturing process of the semiconductor device of the first embodiment.

9A and 9B are a plan view and a cross-sectional view taken along line IXb-IXb showing a step of forming a gate electrode in the manufacturing process of the semiconductor device of the first embodiment.

10A and 10B are SiC of a second embodiment.
-The first epitaxial growth portion of the nMISFET (first S
a plan view showing changes during growth (excluding i-cap layer) and
It is sectional drawing in the Xb-Xb line.

FIG. 11 is a diagram showing a profile and a band state during growth of a C composition ratio in an Xb-Xb line cross section of an upper portion of a first epitaxial growth portion (excluding a first Si cap layer).

FIG. 12 shows a second embodiment and a conventional SiC-nMIS.
It is a figure which shows the simulation result of the current cutoff frequency-gate voltage characteristic of FET.

13A and 13B are diagrams showing simulation results of drain current-drain voltage characteristics of the second embodiment and the conventional SiC-nMISFET.

FIG. 14 is an energy band diagram showing a band-edge structure in the Si / SiGeC / Si laminated structure of the third embodiment.

15 is a diagram showing the dependence of the band offset amount ΔEv at the valence band edge shown in FIG. 14 on the Ge and C composition ratios.

16 is a diagram showing the dependence of the band offset amount ΔEc at the conduction band edge shown in FIG. 14 on the Ge and C composition ratio.

FIG. 17 is a cross-sectional view of a conventional MIS type SiGe-p MISFET.

18 (a) and 18 (b) respectively show a conventional S
FIG. 6 is a diagram showing a Ge composition ratio profile in the depth direction of the iGe-p MISFET and an energy band diagram when a gate bias is applied.

19 (a) and 19 (b) show, respectively, a conventional SiGe-layer provided with a SiGe channel layer having a graded composition.
FIG. 3 is a diagram showing a profile of Ge composition ratio in the depth direction of pMISFET, and an energy band diagram when a gate bias is applied.

20A to 20C are cross-sectional views showing a manufacturing process of the conventional SiGe-p MISFET having the cross-sectional structure shown in FIG.

[Explanation of symbols]

101 Si substrate 102a First central Si film 102b Second central Si film 103a First SiGe film 103b Second SiGe film 104a First outer Si film 104b Second outer Si film 105 Trench isolation region 106a First Si cap layer 106b Second Si cap layer 107a First thermal oxide film 107b Second thermal oxide film 108 Gate electrode 109 Source region 110 Drain region 112 Interlayer insulating film 113 Source wiring 113a Source contact 113b Pad portion 114 Drain wiring 114a Drain contact 114b Pad portion 115 Gate wiring 115b Pad portion 116 Body Voltage supply wiring 116a Body contact 117 Channel region 119 Body contact region 151 First epitaxial growth portion (semiconductor layer, semiconductor crystal layer) 152 Second epitaxial Growth portion (a semiconductor layer, a semiconductor crystal layer) 163a first 1Si _1-y C y film

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 27/092 H01L 29/80 B 29/161 29/78 618B 29/786 29/812 (72) Inventor Tsuyoshi Takagi 1006 Kadoma, Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor Minoru Kubo 1006 Kadoma, Kadoma City, Osaka Prefecture F Term (Reference) 5F045 AA07 AB01 AB02 AB06 AC01 AC08 AD09 AF02 AF03 CA05 DB02 DB04 5F048 AC03 AC10 BA14 BA16 BB05 BC11 BC15 BD01 BD09 5F102 GB01 GC01 GD01 GD10 GJ10 GL02 GL16 GL18 GM02 HC01 HC07 5F110 AA01 AAGGGG GG04 GG04 GG04 GG04 GG04 CC04 DD05 EE02 EE05 EE08 GG22 GG04 GG02 FF02 GG02 HJ13 HJ23 HL03 HM03 NN02 NN71 NN72 NN74 5F140 AA01 AA12 AB01 AB03 AB06 AB07 AB09 AB10 AC01 AC28 BA01 BA02 BA05 BA06 BA07 BA08 BA17 BA20 BB18 BC1 2 BC13 BE07 BF01 BF04 BF05 BF08 BF54 BG32 BG37 BH04 BH06 BH27 BH30 BH43 BJ27 BK13 BK21 CB04 CE07

Claims (19)

[Claims] 1. A field effect transistor having a substrate, a semiconductor layer formed on the substrate, and a gate electrode formed on the semiconductor layer, wherein the semiconductor layer is provided below the gate electrode. It has a channel region located therein and a source region and a drain region located on both sides of the channel region, and in a cross section parallel to the channel direction of the channel region, the energy level at the band edge where carriers travel is equal to the bias level. A semiconductor device, wherein the semiconductor device is inclined in a direction in which carrier travel is accelerated in a non-application state. 2. The semiconductor device according to claim 1, wherein the source region and the drain region are p-type regions, the channel region functions as a p-channel through which holes travel, and a valence band in the channel region is formed. The semiconductor device characterized in that the energy level difference between the edge and the vacuum level decreases continuously or stepwise in the direction in which holes flow. 3. The semiconductor device according to claim 2, wherein the channel region has a composition represented by Si _1-x Ge _x (0 ≦ x ≦ 1), and the Ge composition ratio x in the channel region is 3. Is a semiconductor device characterized in that the holes increase continuously or stepwise in the flowing direction. 4. The semiconductor device according to claim 1, wherein the source region and the drain region are n-type regions, the channel region functions as an n channel through which electrons travel, and a conduction band edge in the channel region. The semiconductor device is characterized in that the energy level difference between the vacuum level and the vacuum level increases continuously or stepwise in the electron flow direction. 5. The semiconductor device according to claim 4, wherein the channel region has a composition represented by Si _1-y C _y (0 ≦ y <1), and a C composition ratio y in the channel region. Is a semiconductor device characterized in that the number of electrons increases continuously or stepwise in the direction in which electrons flow. 6. The semiconductor device according to claim 1, wherein the channel region contains a carrier impurity whose concentration continuously or stepwise changes in a carrier flow direction. A semiconductor device characterized by the above. 7. The semiconductor device according to claim 1, wherein the semiconductor layer has an upper surface that is narrower than a bottom surface and an inclined side surface that exists between the bottom surface and the upper surface. It has a partial cone shape, and one of the source region and the drain region is located substantially in the center of the semiconductor layer, and the other of the source region and the drain region is the periphery of the semiconductor layer. A semiconductor device, wherein the channel region is located between the central portion and the peripheral portion. 8. The semiconductor device according to claim 7, wherein a contour of a portion of the channel region where carriers travel in the band region where the energy levels are equal to each other has a slope substantially parallel to a side surface of the partial cone-shaped semiconductor layer. A semiconductor device characterized by: 9. The semiconductor device according to claim 1, wherein the field effect transistor further includes a gate insulating film interposed between the semiconductor layer and the gate electrode.
A semiconductor device, which is an IS field effect transistor. 10. A first field effect transistor having a substrate, a first semiconductor layer formed on the substrate, and a first gate electrode formed on the first semiconductor layer. A second field effect transistor having a second semiconductor layer formed on the substrate and a second gate electrode formed on the second semiconductor layer, wherein the first and second field effect transistors are provided. The semiconductor layer of has a channel region located below the gate electrode, and a source region and a drain region located on both sides of the channel region, and in a cross section parallel to the channel direction of each channel region, A semiconductor characterized in that the valence band edge is inclined in a direction to accelerate the traveling of holes in the non-biased state, and the conduction band edge is inclined in a direction to accelerate the traveling of electrons in the non-biased state. Location. 11. The semiconductor device according to claim 10, wherein each of the channel regions comprises Si _1-xy Ge _x C _y (0 ≦ x
≦ 1,0 ≦ y <1), and the Ge composition ratio x and the C composition ratio y in each of the channel regions are determined by the energy levels of the valence band edge and the vacuum level in the channel region. The difference is adjusted so that the electron affinity at the conduction band edge in the channel region increases continuously or stepwise while the difference decreases continuously or stepwise in the hole flowing direction. A semiconductor device characterized by: 12. The semiconductor device according to claim 10, further comprising an active region provided on a surface portion of the substrate, and an isolation region made of an insulator surrounding the active region, each semiconductor layer. One of the source region and the drain region of the semiconductor layer is located substantially in the center of each semiconductor layer, and the other of the source region and the drain region of each semiconductor layer is located in the peripheral part of each semiconductor layer. The semiconductor device is characterized in that the channel regions of the respective semiconductor layers are respectively located between the central portion and the peripheral portion. 13. A semiconductor substrate, an active region provided on a surface portion of the semiconductor substrate, an isolation region made of an insulator surrounding the active region, and epitaxial growth over the active region and a part of the isolation region. A semiconductor layer formed, wherein the semiconductor layer has a first impurity diffusion layer at least a portion of which is located immediately above the active region, a second impurity diffusion layer which is located above the isolation region, A semiconductor device having a channel region which is interposed between the first and second impurity diffusion layers and at least a part of which is located above the isolation region. 14. The semiconductor device according to claim 13, wherein, in a cross section of the channel region parallel to the channel direction, a band edge on which carriers travel is inclined in a direction in which carrier travel is accelerated in a bias-free state. A semiconductor device characterized in that. 15. The semiconductor device according to claim 13, wherein the semiconductor substrate is a Si substrate, and the semiconductor layer is a central Si film epitaxially grown from an upper surface of the active region of the Si substrate, S epitaxially grown from the side surface of the central Si film
i _1-x Ge _x (0 ≦ x ≦ 1), Si _1-y C _y (0 ≦ y <
1) and Si _1-xy Ge _x C _y (0 ≦ x ≦ 1, 0 ≦ y <
A semiconductor device comprising a compound semiconductor film having a composition represented by any one of 1) and an outer Si film epitaxially grown from a side surface of the compound semiconductor film. 16. The semiconductor device according to claim 15, wherein the semiconductor layer is a Si cap layer epitaxially grown from upper surfaces and side surfaces of the central Si film, the compound semiconductor film, and the entire outer Si film, and the Si cap layer. And a gate insulating film formed on the semiconductor device. 17. A step (a) of forming an isolation region made of an insulator surrounding an active region on a surface portion of a semiconductor substrate, and selectively epitaxially growing a semiconductor crystal layer from the active region to the isolation region. Step (b), step (c) of forming a gate electrode on the semiconductor crystal layer, and implanting impurities into the semiconductor crystal layer using at least the gate electrode as a mask to form first and second impurities. A method of manufacturing a semiconductor device, comprising the step (d) of forming a diffusion layer. 18. The method of manufacturing a semiconductor device according to claim 17, wherein the step (b) includes a sub-step (b1) of forming a first semiconductor film by epitaxial growth from the upper surface of the active region, By epitaxial growth from the first semiconductor layer,
Substep (b) of forming a second semiconductor film made of a compound semiconductor whose composition or impurity concentration changes continuously or stepwise
2) and a sub-step (b3) of forming a third semiconductor film by epitaxial growth from the second semiconductor layer, which is a method for manufacturing a semiconductor device. 19. The method of manufacturing a semiconductor device according to claim 18, wherein in the step (b), after the sub-step (b3), the upper surfaces of the first to third semiconductor films are exposed. Sub-step (b4) of removing the upper part of the first to third semiconductor films as a whole, and depositing a fourth semiconductor film on the flattened upper surfaces and side surfaces of the first to third semiconductor films. Sub-process (b5)
And a sub-step (b6) of forming a gate insulating film on the fourth semiconductor film, the method of manufacturing a semiconductor device.