JP2007528050A - メモリ・マップされないデバイス・メモリへの直接アクセス方法及びシステム - Google Patents

メモリ・マップされないデバイス・メモリへの直接アクセス方法及びシステム Download PDF

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Publication number
JP2007528050A
JP2007528050A JP2006535566A JP2006535566A JP2007528050A JP 2007528050 A JP2007528050 A JP 2007528050A JP 2006535566 A JP2006535566 A JP 2006535566A JP 2006535566 A JP2006535566 A JP 2006535566A JP 2007528050 A JP2007528050 A JP 2007528050A
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JP
Japan
Prior art keywords
memory
information
bus
template
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006535566A
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English (en)
Japanese (ja)
Other versions
JP2007528050A5 (enExample
Inventor
ヴ，ミュー・ヴイ
マルティネス・ペレス，リカルド
ペルク，オスカー
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NXP USA Inc
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NXP USA Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP USA Inc filed Critical NXP USA Inc
Publication of JP2007528050A publication Critical patent/JP2007528050A/ja
Publication of JP2007528050A5 publication Critical patent/JP2007528050A5/ja
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/404—Coupling between buses using bus bridges with address mapping
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Digital Computer Display Output (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Executing Machine-Instructions (AREA)
JP2006535566A 2003-10-14 2004-10-08 メモリ・マップされないデバイス・メモリへの直接アクセス方法及びシステム Pending JP2007528050A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/685,561 US7293153B2 (en) 2003-10-14 2003-10-14 Method and system for direct access to a non-memory mapped device memory
PCT/US2004/033292 WO2005038585A2 (en) 2003-10-14 2004-10-08 Method and system for direct access to a non-memory mapped device memory

Publications (2)

Publication Number Publication Date
JP2007528050A true JP2007528050A (ja) 2007-10-04
JP2007528050A5 JP2007528050A5 (enExample) 2007-11-22

Family

ID=34423183

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006535566A Pending JP2007528050A (ja) 2003-10-14 2004-10-08 メモリ・マップされないデバイス・メモリへの直接アクセス方法及びシステム

Country Status (7)

Country Link
US (1) US7293153B2 (enExample)
EP (1) EP1676190A4 (enExample)
JP (1) JP2007528050A (enExample)
KR (1) KR20060130033A (enExample)
CN (1) CN101223511A (enExample)
TW (1) TWI345165B (enExample)
WO (1) WO2005038585A2 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7870323B2 (en) * 2007-12-26 2011-01-11 Marvell World Trade Ltd. Bridge circuit for interfacing processor to main memory and peripherals
TWI412932B (zh) * 2008-03-28 2013-10-21 Hon Hai Prec Ind Co Ltd 主設備對從設備之自動定址系統
US8977895B2 (en) * 2012-07-18 2015-03-10 International Business Machines Corporation Multi-core diagnostics and repair using firmware and spare cores
CN103678244B (zh) * 2012-09-12 2017-09-05 周松 一种不使用应用处理器的智能设备
US9377968B2 (en) * 2013-11-13 2016-06-28 Sandisk Technologies Llc Method and system for using templates to communicate with non-volatile memory
GB2554820B (en) * 2015-05-20 2021-05-12 Mitsubishi Electric Corp Remote controller setting device
US11550681B2 (en) 2020-11-02 2023-01-10 Nxp Usa, Inc. System and method for error injection in system-on-chip

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05307512A (ja) * 1992-05-01 1993-11-19 Sharp Corp 通信端末装置
JPH08274814A (ja) * 1994-12-28 1996-10-18 At & T Corp ネットワーク通信カスタマイズのための方法とシステム
JPH11212903A (ja) * 1997-11-06 1999-08-06 Hitachi Ltd データ処理システム、周辺装置及びマイクロコンピュータ
JP2000235542A (ja) * 1999-02-16 2000-08-29 Sony Corp データ処理装置及び記録媒体
JP2002099498A (ja) * 2000-09-25 2002-04-05 Mitsubishi Electric Corp プログラム実行装置およびプログラム開発支援装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0484253A (ja) * 1990-07-26 1992-03-17 Mitsubishi Electric Corp バス幅制御回路
US5546553A (en) * 1990-09-24 1996-08-13 Texas Instruments Incorporated Multifunctional access devices, systems and methods
US5649142A (en) * 1991-10-24 1997-07-15 Intel Corporation Method and apparatus for translating addresses using mask and replacement value registers and for accessing a service routine in response to a page fault
US6088624A (en) * 1996-12-09 2000-07-11 Rockwell Technologies, Llc Industrial controller with flexible data structures
JP3168255B2 (ja) * 1997-02-06 2001-05-21 ファナック株式会社 機械やロボットを駆動制御するプロセッサを備えた制御装置の運転方法
US7493368B2 (en) 2000-12-01 2009-02-17 Sony Corporation System and method for effectively providing user information from a user device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05307512A (ja) * 1992-05-01 1993-11-19 Sharp Corp 通信端末装置
JPH08274814A (ja) * 1994-12-28 1996-10-18 At & T Corp ネットワーク通信カスタマイズのための方法とシステム
JPH11212903A (ja) * 1997-11-06 1999-08-06 Hitachi Ltd データ処理システム、周辺装置及びマイクロコンピュータ
JP2000235542A (ja) * 1999-02-16 2000-08-29 Sony Corp データ処理装置及び記録媒体
JP2002099498A (ja) * 2000-09-25 2002-04-05 Mitsubishi Electric Corp プログラム実行装置およびプログラム開発支援装置

Also Published As

Publication number Publication date
US20050080949A1 (en) 2005-04-14
TWI345165B (en) 2011-07-11
TW200523789A (en) 2005-07-16
EP1676190A4 (en) 2007-08-22
KR20060130033A (ko) 2006-12-18
WO2005038585A2 (en) 2005-04-28
EP1676190A2 (en) 2006-07-05
WO2005038585A3 (en) 2007-01-25
US7293153B2 (en) 2007-11-06
CN101223511A (zh) 2008-07-16

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