TWI345165B - Method and system for direct access to a non-memory mapped device memory - Google Patents

Method and system for direct access to a non-memory mapped device memory Download PDF

Info

Publication number
TWI345165B
TWI345165B TW093131240A TW93131240A TWI345165B TW I345165 B TWI345165 B TW I345165B TW 093131240 A TW093131240 A TW 093131240A TW 93131240 A TW93131240 A TW 93131240A TW I345165 B TWI345165 B TW I345165B
Authority
TW
Taiwan
Prior art keywords
memory
information
bus
address
memory mapping
Prior art date
Application number
TW093131240A
Other languages
English (en)
Chinese (zh)
Other versions
TW200523789A (en
Inventor
Mieu V Vu
Ricardo Martinez Perez
Oskar Pelc
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of TW200523789A publication Critical patent/TW200523789A/zh
Application granted granted Critical
Publication of TWI345165B publication Critical patent/TWI345165B/zh

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4004Coupling between buses
    • G06F13/4027Coupling between buses using bus bridges
    • G06F13/404Coupling between buses using bus bridges with address mapping
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Digital Computer Display Output (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Executing Machine-Instructions (AREA)
TW093131240A 2003-10-14 2004-10-14 Method and system for direct access to a non-memory mapped device memory TWI345165B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/685,561 US7293153B2 (en) 2003-10-14 2003-10-14 Method and system for direct access to a non-memory mapped device memory

Publications (2)

Publication Number Publication Date
TW200523789A TW200523789A (en) 2005-07-16
TWI345165B true TWI345165B (en) 2011-07-11

Family

ID=34423183

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093131240A TWI345165B (en) 2003-10-14 2004-10-14 Method and system for direct access to a non-memory mapped device memory

Country Status (7)

Country Link
US (1) US7293153B2 (enExample)
EP (1) EP1676190A4 (enExample)
JP (1) JP2007528050A (enExample)
KR (1) KR20060130033A (enExample)
CN (1) CN101223511A (enExample)
TW (1) TWI345165B (enExample)
WO (1) WO2005038585A2 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7870323B2 (en) * 2007-12-26 2011-01-11 Marvell World Trade Ltd. Bridge circuit for interfacing processor to main memory and peripherals
TWI412932B (zh) * 2008-03-28 2013-10-21 Hon Hai Prec Ind Co Ltd 主設備對從設備之自動定址系統
US8977895B2 (en) * 2012-07-18 2015-03-10 International Business Machines Corporation Multi-core diagnostics and repair using firmware and spare cores
CN103678244B (zh) * 2012-09-12 2017-09-05 周松 一种不使用应用处理器的智能设备
US9377968B2 (en) * 2013-11-13 2016-06-28 Sandisk Technologies Llc Method and system for using templates to communicate with non-volatile memory
GB2554820B (en) * 2015-05-20 2021-05-12 Mitsubishi Electric Corp Remote controller setting device
US11550681B2 (en) 2020-11-02 2023-01-10 Nxp Usa, Inc. System and method for error injection in system-on-chip

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0484253A (ja) * 1990-07-26 1992-03-17 Mitsubishi Electric Corp バス幅制御回路
US5546553A (en) * 1990-09-24 1996-08-13 Texas Instruments Incorporated Multifunctional access devices, systems and methods
US5649142A (en) * 1991-10-24 1997-07-15 Intel Corporation Method and apparatus for translating addresses using mask and replacement value registers and for accessing a service routine in response to a page fault
JPH05307512A (ja) * 1992-05-01 1993-11-19 Sharp Corp 通信端末装置
US5594721A (en) * 1994-12-28 1997-01-14 Lucent Technologies Inc. Method and system for implementing an application protocol in a communication network
US6088624A (en) * 1996-12-09 2000-07-11 Rockwell Technologies, Llc Industrial controller with flexible data structures
JP3168255B2 (ja) * 1997-02-06 2001-05-21 ファナック株式会社 機械やロボットを駆動制御するプロセッサを備えた制御装置の運転方法
JPH11212903A (ja) * 1997-11-06 1999-08-06 Hitachi Ltd データ処理システム、周辺装置及びマイクロコンピュータ
JP2000235542A (ja) * 1999-02-16 2000-08-29 Sony Corp データ処理装置及び記録媒体
JP2002099498A (ja) * 2000-09-25 2002-04-05 Mitsubishi Electric Corp プログラム実行装置およびプログラム開発支援装置
US7493368B2 (en) 2000-12-01 2009-02-17 Sony Corporation System and method for effectively providing user information from a user device

Also Published As

Publication number Publication date
US20050080949A1 (en) 2005-04-14
TW200523789A (en) 2005-07-16
EP1676190A4 (en) 2007-08-22
KR20060130033A (ko) 2006-12-18
WO2005038585A2 (en) 2005-04-28
EP1676190A2 (en) 2006-07-05
WO2005038585A3 (en) 2007-01-25
US7293153B2 (en) 2007-11-06
CN101223511A (zh) 2008-07-16
JP2007528050A (ja) 2007-10-04

Similar Documents

Publication Publication Date Title
US6233641B1 (en) Apparatus and method of PCI routing in a bridge configuration
US20040107265A1 (en) Shared memory data transfer apparatus
US20060004976A1 (en) Shared memory architecture
CN111651384B (zh) 寄存器的读写方法、芯片、子系统、寄存器组及终端
JP3136257B2 (ja) コンピュータメモリインタフェース装置
US6763448B1 (en) Microcomputer and microcomputer system
US9881680B2 (en) Multi-host power controller (MHPC) of a flash-memory-based storage device
CN108304334B (zh) 应用处理器和包括中断控制器的集成电路
US9632953B2 (en) Providing input/output virtualization (IOV) by mapping transfer requests to shared transfer requests lists by IOV host controllers
US20070055813A1 (en) Accessing external memory from an integrated circuit
TWI345165B (en) Method and system for direct access to a non-memory mapped device memory
JPH08314418A (ja) バースト・ダイレクトメモリアクセスを備えた表示制御装置を有するデータ処理システム
WO2005119465A1 (en) Data processing unit and bus arbitration unit
CN114168503A (zh) 一种接口ip核控制方法、接口ip核、装置及介质
KR20080013138A (ko) 컴퓨팅 시스템, 전자 통신 디바이스, 컴퓨팅 시스템 운영 방법 및 정보 처리 방법
US6097403A (en) Memory including logic for operating upon graphics primitives
CN110795373B (zh) 一种i2c总线到并行总线的转换方法、终端及存储介质
JP2007528050A5 (enExample)
CN101194241A (zh) 用于对网络和存储器进行耦合的存储器控制器和方法
JP2004318877A (ja) 知的な待ち方法
KR100736902B1 (ko) 복수의 프로세서에 의한 메모리 공유 방법 및 장치
US10261700B1 (en) Method and apparatus for streaming buffering to accelerate reads
WO2006004166A1 (en) Data processing unit and compatible processor
JP3959137B2 (ja) データプロセッサ
JP2004013289A (ja) マイクロコントローラのオンチップデバッグ方法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees