JP2007527071A5 - - Google Patents

Download PDF

Info

Publication number
JP2007527071A5
JP2007527071A5 JP2007501776A JP2007501776A JP2007527071A5 JP 2007527071 A5 JP2007527071 A5 JP 2007527071A5 JP 2007501776 A JP2007501776 A JP 2007501776A JP 2007501776 A JP2007501776 A JP 2007501776A JP 2007527071 A5 JP2007527071 A5 JP 2007527071A5
Authority
JP
Japan
Prior art keywords
burst
protocol
error
requested
selection logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2007501776A
Other languages
English (en)
Japanese (ja)
Other versions
JP4652394B2 (ja
JP2007527071A (ja
Filing date
Publication date
Priority claimed from US10/792,591 external-priority patent/US7334059B2/en
Application filed filed Critical
Publication of JP2007527071A publication Critical patent/JP2007527071A/ja
Publication of JP2007527071A5 publication Critical patent/JP2007527071A5/ja
Application granted granted Critical
Publication of JP4652394B2 publication Critical patent/JP4652394B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP2007501776A 2004-03-03 2005-01-21 マルチバーストプロトコルデバイスコントローラ Expired - Fee Related JP4652394B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/792,591 US7334059B2 (en) 2004-03-03 2004-03-03 Multiple burst protocol device controller
PCT/US2005/001776 WO2005096161A1 (en) 2004-03-03 2005-01-21 Multiple burst protocol device controller

Publications (3)

Publication Number Publication Date
JP2007527071A JP2007527071A (ja) 2007-09-20
JP2007527071A5 true JP2007527071A5 (cg-RX-API-DMAC7.html) 2008-03-06
JP4652394B2 JP4652394B2 (ja) 2011-03-16

Family

ID=34911887

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007501776A Expired - Fee Related JP4652394B2 (ja) 2004-03-03 2005-01-21 マルチバーストプロトコルデバイスコントローラ

Country Status (9)

Country Link
US (1) US7334059B2 (cg-RX-API-DMAC7.html)
EP (1) EP1723532B1 (cg-RX-API-DMAC7.html)
JP (1) JP4652394B2 (cg-RX-API-DMAC7.html)
KR (1) KR101036445B1 (cg-RX-API-DMAC7.html)
CN (1) CN100470519C (cg-RX-API-DMAC7.html)
AT (1) ATE461488T1 (cg-RX-API-DMAC7.html)
DE (1) DE602005019985D1 (cg-RX-API-DMAC7.html)
TW (1) TWI358662B (cg-RX-API-DMAC7.html)
WO (1) WO2005096161A1 (cg-RX-API-DMAC7.html)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7496695B2 (en) 2005-09-29 2009-02-24 P.A. Semi, Inc. Unified DMA
WO2008002174A1 (en) * 2006-06-28 2008-01-03 Intel Corporation Modification to meggitt decoder for burst error correction codes
US8572302B1 (en) 2006-10-13 2013-10-29 Marvell International Ltd. Controller for storage device with improved burst efficiency
US9015368B2 (en) * 2006-12-22 2015-04-21 Qualcomm Incorporated Enhanced wireless USB protocol
US8001338B2 (en) * 2007-08-21 2011-08-16 Microsoft Corporation Multi-level DRAM controller to manage access to DRAM
CN101470678B (zh) * 2007-12-29 2011-01-19 中国科学院声学研究所 基于突发乱序的存储器控制器、系统及其访存调度方法
US8180975B2 (en) * 2008-02-26 2012-05-15 Microsoft Corporation Controlling interference in shared memory systems using parallelism-aware batch scheduling
US20090248910A1 (en) * 2008-04-01 2009-10-01 Apple Inc. Central dma with arbitrary processing functions
FR2942331A1 (fr) * 2009-02-18 2010-08-20 Stmicroelectronics Grenoble 2 Systeme et procede de traitement de donnees numeriques
CN105302746A (zh) * 2014-07-04 2016-02-03 Lsi公司 多协议存储控制器
JP6988092B2 (ja) * 2017-01-16 2022-01-05 富士通株式会社 並列処理装置およびバーストエラー再現方法
US10606678B2 (en) * 2017-11-17 2020-03-31 Tesla, Inc. System and method for handling errors in a vehicle neural network processor
CN114609955B (zh) * 2022-05-10 2022-08-12 浙江浙能航天氢能技术有限公司 一种加氢用多功能通用控制器设计及控制方法及装置

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4710916A (en) 1985-08-02 1987-12-01 Gte Laboratories Incorporated Switching apparatus for burst-switching communications system
JPH05204845A (ja) * 1992-01-30 1993-08-13 Fujitsu Ltd データ処理装置及びその制御方法
JPH0844665A (ja) * 1994-07-14 1996-02-16 Fujitsu Ltd 複数のデータ転送サイズ及びプロトコルをサポートするバス
US5548587A (en) 1994-09-12 1996-08-20 Efficient Networks, Inc. Asynchronous transfer mode adapter for desktop applications
US5774683A (en) 1996-10-21 1998-06-30 Advanced Micro Devices, Inc. Interconnect bus configured to implement multiple transfer protocols
US5954839A (en) * 1997-01-14 1999-09-21 Samsung Electronics Co., Ltd. Error protection method for multimedia data
JPH1185673A (ja) * 1997-09-02 1999-03-30 Hitachi Ltd 共有バスの制御方法とその装置
US6195770B1 (en) 1998-03-31 2001-02-27 Emc Corporation Data storage system
US6816829B1 (en) * 2000-01-04 2004-11-09 International Business Machines Corporation System and method to independently verify the execution rate of individual tasks by a device via simulation
US6804310B1 (en) * 2000-11-03 2004-10-12 Koninklijke Philips Electronics N.V. Decision feedback loop apparatus and method for channel estimation and de-rotation using burst pilot bits
JP3462468B2 (ja) 2000-11-27 2003-11-05 松下電器産業株式会社 Ofdm受信装置、ofdm送信装置およびofdm通信方法
US6775727B2 (en) * 2001-06-23 2004-08-10 Freescale Semiconductor, Inc. System and method for controlling bus arbitration during cache memory burst cycles
US7032045B2 (en) 2001-09-18 2006-04-18 Invensys Systems, Inc. Multi-protocol bus device
JP4071117B2 (ja) * 2003-01-23 2008-04-02 シャープ株式会社 送受信回路及び送受信方法並びに送受信装置

Similar Documents

Publication Publication Date Title
JP2007527071A5 (cg-RX-API-DMAC7.html)
JP2009540431A5 (cg-RX-API-DMAC7.html)
KR101693137B1 (ko) 가변적 레이턴시 메모리 동작들을 위한 장치들 및 방법들
JP2011527067A5 (cg-RX-API-DMAC7.html)
WO2007005693A3 (en) Memory controller interface for micro-tiled memory access
JP2004021916A5 (cg-RX-API-DMAC7.html)
JP2006505798A5 (cg-RX-API-DMAC7.html)
JP2008022917A5 (cg-RX-API-DMAC7.html)
KR20150002761A (ko) Dram 당 주소 매김 능력 모드를 위한 방법, 장치 및 시스템
JP2009205698A5 (cg-RX-API-DMAC7.html)
JP2010506301A (ja) Sasエキスパンダなしの改良型sataデバイス対話のための装置および方法
CN105159853B (zh) 基于fpga的dfi标准ddr3控制器
JP2009540681A5 (cg-RX-API-DMAC7.html)
JP2008102706A (ja) メモリ制御回路
JP2006120307A5 (cg-RX-API-DMAC7.html)
JP2004222299A5 (cg-RX-API-DMAC7.html)
JP6493062B2 (ja) メモリコントローラ、メモリシステムおよび情報処理システム
JP2007103009A5 (cg-RX-API-DMAC7.html)
JP2004348953A5 (cg-RX-API-DMAC7.html)
US20070286011A1 (en) Memory device having data input and output ports and memory module and memory system including the same
JP2007500402A5 (cg-RX-API-DMAC7.html)
JP2010157929A5 (cg-RX-API-DMAC7.html)
CN108139993B (zh) 内存装置、内存控制器、数据缓存装置及计算机系统
JP2009064360A5 (cg-RX-API-DMAC7.html)
TWI761655B (zh) 頁面大小感知調度方法和非暫時性電腦可讀記錄媒體