KR101036445B1 - 다중 버스트 프로토콜 장치 제어기 - Google Patents

다중 버스트 프로토콜 장치 제어기 Download PDF

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Publication number
KR101036445B1
KR101036445B1 KR1020067017808A KR20067017808A KR101036445B1 KR 101036445 B1 KR101036445 B1 KR 101036445B1 KR 1020067017808 A KR1020067017808 A KR 1020067017808A KR 20067017808 A KR20067017808 A KR 20067017808A KR 101036445 B1 KR101036445 B1 KR 101036445B1
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South Korea
Prior art keywords
burst
protocol
error
master
requested
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KR1020067017808A
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English (en)
Korean (ko)
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KR20060126580A (ko
Inventor
윌리암 씨. 모이어
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프리스케일 세미컨덕터, 인크.
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Computer Hardware Design (AREA)
  • Communication Control (AREA)
  • Debugging And Monitoring (AREA)
  • Bus Control (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Information Transfer Systems (AREA)
KR1020067017808A 2004-03-03 2005-01-21 다중 버스트 프로토콜 장치 제어기 Expired - Fee Related KR101036445B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/792,591 2004-03-03
US10/792,591 US7334059B2 (en) 2004-03-03 2004-03-03 Multiple burst protocol device controller

Publications (2)

Publication Number Publication Date
KR20060126580A KR20060126580A (ko) 2006-12-07
KR101036445B1 true KR101036445B1 (ko) 2011-05-24

Family

ID=34911887

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020067017808A Expired - Fee Related KR101036445B1 (ko) 2004-03-03 2005-01-21 다중 버스트 프로토콜 장치 제어기

Country Status (9)

Country Link
US (1) US7334059B2 (cg-RX-API-DMAC7.html)
EP (1) EP1723532B1 (cg-RX-API-DMAC7.html)
JP (1) JP4652394B2 (cg-RX-API-DMAC7.html)
KR (1) KR101036445B1 (cg-RX-API-DMAC7.html)
CN (1) CN100470519C (cg-RX-API-DMAC7.html)
AT (1) ATE461488T1 (cg-RX-API-DMAC7.html)
DE (1) DE602005019985D1 (cg-RX-API-DMAC7.html)
TW (1) TWI358662B (cg-RX-API-DMAC7.html)
WO (1) WO2005096161A1 (cg-RX-API-DMAC7.html)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7496695B2 (en) 2005-09-29 2009-02-24 P.A. Semi, Inc. Unified DMA
WO2008002174A1 (en) * 2006-06-28 2008-01-03 Intel Corporation Modification to meggitt decoder for burst error correction codes
US8572302B1 (en) 2006-10-13 2013-10-29 Marvell International Ltd. Controller for storage device with improved burst efficiency
US9015368B2 (en) * 2006-12-22 2015-04-21 Qualcomm Incorporated Enhanced wireless USB protocol
US8001338B2 (en) * 2007-08-21 2011-08-16 Microsoft Corporation Multi-level DRAM controller to manage access to DRAM
CN101470678B (zh) * 2007-12-29 2011-01-19 中国科学院声学研究所 基于突发乱序的存储器控制器、系统及其访存调度方法
US8180975B2 (en) * 2008-02-26 2012-05-15 Microsoft Corporation Controlling interference in shared memory systems using parallelism-aware batch scheduling
US20090248910A1 (en) * 2008-04-01 2009-10-01 Apple Inc. Central dma with arbitrary processing functions
FR2942331A1 (fr) * 2009-02-18 2010-08-20 Stmicroelectronics Grenoble 2 Systeme et procede de traitement de donnees numeriques
CN105302746A (zh) * 2014-07-04 2016-02-03 Lsi公司 多协议存储控制器
JP6988092B2 (ja) * 2017-01-16 2022-01-05 富士通株式会社 並列処理装置およびバーストエラー再現方法
US10606678B2 (en) * 2017-11-17 2020-03-31 Tesla, Inc. System and method for handling errors in a vehicle neural network processor
CN114609955B (zh) * 2022-05-10 2022-08-12 浙江浙能航天氢能技术有限公司 一种加氢用多功能通用控制器设计及控制方法及装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6816829B1 (en) 2000-01-04 2004-11-09 International Business Machines Corporation System and method to independently verify the execution rate of individual tasks by a device via simulation

Family Cites Families (13)

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US4710916A (en) 1985-08-02 1987-12-01 Gte Laboratories Incorporated Switching apparatus for burst-switching communications system
JPH05204845A (ja) * 1992-01-30 1993-08-13 Fujitsu Ltd データ処理装置及びその制御方法
JPH0844665A (ja) * 1994-07-14 1996-02-16 Fujitsu Ltd 複数のデータ転送サイズ及びプロトコルをサポートするバス
US5548587A (en) 1994-09-12 1996-08-20 Efficient Networks, Inc. Asynchronous transfer mode adapter for desktop applications
US5774683A (en) 1996-10-21 1998-06-30 Advanced Micro Devices, Inc. Interconnect bus configured to implement multiple transfer protocols
US5954839A (en) * 1997-01-14 1999-09-21 Samsung Electronics Co., Ltd. Error protection method for multimedia data
JPH1185673A (ja) * 1997-09-02 1999-03-30 Hitachi Ltd 共有バスの制御方法とその装置
US6195770B1 (en) 1998-03-31 2001-02-27 Emc Corporation Data storage system
US6804310B1 (en) * 2000-11-03 2004-10-12 Koninklijke Philips Electronics N.V. Decision feedback loop apparatus and method for channel estimation and de-rotation using burst pilot bits
JP3462468B2 (ja) 2000-11-27 2003-11-05 松下電器産業株式会社 Ｏｆｄｍ受信装置、ｏｆｄｍ送信装置およびｏｆｄｍ通信方法
US6775727B2 (en) * 2001-06-23 2004-08-10 Freescale Semiconductor, Inc. System and method for controlling bus arbitration during cache memory burst cycles
US7032045B2 (en) 2001-09-18 2006-04-18 Invensys Systems, Inc. Multi-protocol bus device
JP4071117B2 (ja) * 2003-01-23 2008-04-02 シャープ株式会社 送受信回路及び送受信方法並びに送受信装置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6816829B1 (en) 2000-01-04 2004-11-09 International Business Machines Corporation System and method to independently verify the execution rate of individual tasks by a device via simulation

Also Published As

Publication number Publication date
KR20060126580A (ko) 2006-12-07
CN100470519C (zh) 2009-03-18
TW200535690A (en) 2005-11-01
ATE461488T1 (de) 2010-04-15
US7334059B2 (en) 2008-02-19
EP1723532B1 (en) 2010-03-17
JP4652394B2 (ja) 2011-03-16
EP1723532A1 (en) 2006-11-22
DE602005019985D1 (cg-RX-API-DMAC7.html) 2010-04-29
TWI358662B (en) 2012-02-21
US20050198413A1 (en) 2005-09-08
JP2007527071A (ja) 2007-09-20
CN1926525A (zh) 2007-03-07
WO2005096161A1 (en) 2005-10-13
EP1723532A4 (en) 2007-08-22

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