JP2007522571A5 - - Google Patents
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- JP2007522571A5 JP2007522571A5 JP2006552599A JP2006552599A JP2007522571A5 JP 2007522571 A5 JP2007522571 A5 JP 2007522571A5 JP 2006552599 A JP2006552599 A JP 2006552599A JP 2006552599 A JP2006552599 A JP 2006552599A JP 2007522571 A5 JP2007522571 A5 JP 2007522571A5
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- 238000003860 storage Methods 0.000 claims description 61
- 238000000034 method Methods 0.000 claims description 11
- 230000007246 mechanism Effects 0.000 claims description 3
- 230000006870 function Effects 0.000 description 70
- 210000004027 cell Anatomy 0.000 description 40
- 230000036961 partial effect Effects 0.000 description 16
- 238000004422 calculation algorithm Methods 0.000 description 9
- 238000004891 communication Methods 0.000 description 7
- 230000008901 benefit Effects 0.000 description 6
- 238000004364 calculation method Methods 0.000 description 5
- 239000013598 vector Substances 0.000 description 5
- 230000001413 cellular effect Effects 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 238000012546 transfer Methods 0.000 description 4
- 230000001419 dependent effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000013507 mapping Methods 0.000 description 3
- 210000000352 storage cell Anatomy 0.000 description 3
- 230000006399 behavior Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005094 computer simulation Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000011156 evaluation Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000004549 pulsed laser deposition Methods 0.000 description 2
- 238000003786 synthesis reaction Methods 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000008568 cell cell communication Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000004807 localization Effects 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
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- 230000002093 peripheral effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 238000013519 translation Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE102004007232 | 2004-02-13 | ||
| DE102004007232.9 | 2004-02-13 | ||
| PCT/EP2005/050500 WO2005078599A1 (de) | 2004-02-13 | 2005-02-07 | Rekonfigurierbares schaltwerk zur parallelen berechung beliebiger algorithmen |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2011241298A Division JP2012074051A (ja) | 2004-02-13 | 2011-11-02 | 任意のアルゴリズムを並列計算するための再構成可能な論理回路装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2007522571A JP2007522571A (ja) | 2007-08-09 |
| JP2007522571A5 true JP2007522571A5 (https=) | 2012-01-05 |
| JP5027515B2 JP5027515B2 (ja) | 2012-09-19 |
Family
ID=34832667
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006552599A Expired - Fee Related JP5027515B2 (ja) | 2004-02-13 | 2005-02-07 | 任意のアルゴリズムを並列計算するための再構成可能な論理回路装置 |
| JP2011241298A Pending JP2012074051A (ja) | 2004-02-13 | 2011-11-02 | 任意のアルゴリズムを並列計算するための再構成可能な論理回路装置 |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2011241298A Pending JP2012074051A (ja) | 2004-02-13 | 2011-11-02 | 任意のアルゴリズムを並列計算するための再構成可能な論理回路装置 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US7352205B2 (https=) |
| JP (2) | JP5027515B2 (https=) |
| CN (1) | CN100388264C (https=) |
| DE (1) | DE102005005073B4 (https=) |
| WO (1) | WO2005078599A1 (https=) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7509479B2 (en) * | 2004-09-16 | 2009-03-24 | Siemens Aktiengesellschaft | Reconfigurable global cellular automaton with RAM blocks coupled to input and output feedback crossbar switches receiving clock counter value from sequence control unit |
| US7801835B2 (en) * | 2005-06-15 | 2010-09-21 | International Business Machines Corporation | Method for constructing autonomic advisors and learning procedural knowledge from scored examples |
| CN101325559B (zh) * | 2008-07-28 | 2010-08-18 | 腾讯科技（深圳）有限公司 | 一种推荐游戏房间的方法、系统和游戏服务器 |
| KR101274115B1 (ko) * | 2009-10-06 | 2013-06-13 | 한국전자통신연구원 | 스크램블 장치 및 이의 동작 방법 |
| US11275568B2 (en) | 2019-01-14 | 2022-03-15 | Microsoft Technology Licensing, Llc | Generating a synchronous digital circuit from a source code construct defining a function call |
| US11106437B2 (en) * | 2019-01-14 | 2021-08-31 | Microsoft Technology Licensing, Llc | Lookup table optimization for programming languages that target synchronous digital circuits |
| US11093682B2 (en) | 2019-01-14 | 2021-08-17 | Microsoft Technology Licensing, Llc | Language and compiler that generate synchronous digital circuits that maintain thread execution order |
| US11144286B2 (en) | 2019-01-14 | 2021-10-12 | Microsoft Technology Licensing, Llc | Generating synchronous digital circuits from source code constructs that map to circuit implementations |
| US11113176B2 (en) | 2019-01-14 | 2021-09-07 | Microsoft Technology Licensing, Llc | Generating a debugging network for a synchronous digital circuit during compilation of program source code |
| US11923009B2 (en) | 2022-06-15 | 2024-03-05 | Hewlett Packard Enterprise Development Lp | Compact K-SAT verification with TCAMS |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3948494B2 (ja) * | 1995-04-28 | 2007-07-25 | ザイリンクス，インコーポレイテッド | プログラム可能論理装置によってアクセス可能な分散レジスタを有するマイクロプロセサ |
| US6247036B1 (en) * | 1996-01-22 | 2001-06-12 | Infinite Technology Corp. | Processor with reconfigurable arithmetic data path |
| DE19843640A1 (de) | 1998-09-23 | 2000-03-30 | Siemens Ag | Verfahren zum Konfigurieren eines konfigurierbaren Hardware-Blocks |
| JP4285877B2 (ja) * | 1999-02-23 | 2009-06-24 | 株式会社リコー | 動的再構成計算のためのメタアドレス指定アーキテクチャ及び動的再構成計算のためのメタアドレス指定方法 |
| JP4558879B2 (ja) * | 2000-02-15 | 2010-10-06 | 富士通株式会社 | テーブルを用いたデータ処理装置および処理システム |
| JP2002026721A (ja) * | 2000-07-10 | 2002-01-25 | Fuji Xerox Co Ltd | 情報処理装置 |
| CA2458199A1 (en) * | 2001-08-16 | 2003-02-27 | Pact Xpp Technologies Ag | Method for the translation of programs for reconfigurable architectures |
| DE10347975B4 (de) | 2002-10-24 | 2008-10-09 | Siemens Ag | Einrichtung der programmierbaren Logik |
| JP4011007B2 (ja) * | 2003-01-15 | 2007-11-21 | 三洋電機株式会社 | リコンフィギュラブル回路を備えた集積回路装置および処理装置 |
| DE102004044976A1 (de) * | 2004-09-16 | 2006-03-30 | Siemens Ag | Rechnereinrichtung mit rekonfigurierbarer Architektur |
-
2005
- 2005-02-03 DE DE102005005073A patent/DE102005005073B4/de not_active Expired - Fee Related
- 2005-02-07 CN CNB2005800048743A patent/CN100388264C/zh not_active Expired - Fee Related
- 2005-02-07 JP JP2006552599A patent/JP5027515B2/ja not_active Expired - Fee Related
- 2005-02-07 WO PCT/EP2005/050500 patent/WO2005078599A1/de not_active Ceased
- 2005-02-07 US US10/588,860 patent/US7352205B2/en not_active Expired - Fee Related
-
2011
- 2011-11-02 JP JP2011241298A patent/JP2012074051A/ja active Pending
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