CN100388264C - 具有可重构体系结构的计算机装置 - Google Patents

具有可重构体系结构的计算机装置 Download PDF

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Publication number
CN100388264C
CN100388264C CNB2005800048743A CN200580004874A CN100388264C CN 100388264 C CN100388264 C CN 100388264C CN B2005800048743 A CNB2005800048743 A CN B2005800048743A CN 200580004874 A CN200580004874 A CN 200580004874A CN 100388264 C CN100388264 C CN 100388264C
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China
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input
memory
level
output
architecture
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Chinese (zh)
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CN1918560A (zh
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克里斯琴·威甘德
克里斯琴·西默斯
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Siemens Corp
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Siemens Corp
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
CNB2005800048743A 2004-02-13 2005-02-07 具有可重构体系结构的计算机装置 Expired - Fee Related CN100388264C (zh)

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DE102004007232 2004-02-13
DE102004007232.9 2004-02-13

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CN1918560A CN1918560A (zh) 2007-02-21
CN100388264C true CN100388264C (zh) 2008-05-14

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US (1) US7352205B2 (https=)
JP (2) JP5027515B2 (https=)
CN (1) CN100388264C (https=)
DE (1) DE102005005073B4 (https=)
WO (1) WO2005078599A1 (https=)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7509479B2 (en) * 2004-09-16 2009-03-24 Siemens Aktiengesellschaft Reconfigurable global cellular automaton with RAM blocks coupled to input and output feedback crossbar switches receiving clock counter value from sequence control unit
US7801835B2 (en) * 2005-06-15 2010-09-21 International Business Machines Corporation Method for constructing autonomic advisors and learning procedural knowledge from scored examples
CN101325559B (zh) * 2008-07-28 2010-08-18 腾讯科技（深圳）有限公司 一种推荐游戏房间的方法、系统和游戏服务器
KR101274115B1 (ko) * 2009-10-06 2013-06-13 한국전자통신연구원 스크램블 장치 및 이의 동작 방법
US11275568B2 (en) 2019-01-14 2022-03-15 Microsoft Technology Licensing, Llc Generating a synchronous digital circuit from a source code construct defining a function call
US11106437B2 (en) * 2019-01-14 2021-08-31 Microsoft Technology Licensing, Llc Lookup table optimization for programming languages that target synchronous digital circuits
US11093682B2 (en) 2019-01-14 2021-08-17 Microsoft Technology Licensing, Llc Language and compiler that generate synchronous digital circuits that maintain thread execution order
US11144286B2 (en) 2019-01-14 2021-10-12 Microsoft Technology Licensing, Llc Generating synchronous digital circuits from source code constructs that map to circuit implementations
US11113176B2 (en) 2019-01-14 2021-09-07 Microsoft Technology Licensing, Llc Generating a debugging network for a synchronous digital circuit during compilation of program source code
US11923009B2 (en) 2022-06-15 2024-03-05 Hewlett Packard Enterprise Development Lp Compact K-SAT verification with TCAMS

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Publication number Priority date Publication date Assignee Title
JP3948494B2 (ja) * 1995-04-28 2007-07-25 ザイリンクス，インコーポレイテッド プログラム可能論理装置によってアクセス可能な分散レジスタを有するマイクロプロセサ
US6247036B1 (en) * 1996-01-22 2001-06-12 Infinite Technology Corp. Processor with reconfigurable arithmetic data path
DE19843640A1 (de) 1998-09-23 2000-03-30 Siemens Ag Verfahren zum Konfigurieren eines konfigurierbaren Hardware-Blocks
JP4285877B2 (ja) * 1999-02-23 2009-06-24 株式会社リコー 動的再構成計算のためのメタアドレス指定アーキテクチャ及び動的再構成計算のためのメタアドレス指定方法
JP4558879B2 (ja) * 2000-02-15 2010-10-06 富士通株式会社 テーブルを用いたデータ処理装置および処理システム
JP2002026721A (ja) * 2000-07-10 2002-01-25 Fuji Xerox Co Ltd 情報処理装置
CA2458199A1 (en) * 2001-08-16 2003-02-27 Pact Xpp Technologies Ag Method for the translation of programs for reconfigurable architectures
DE10347975B4 (de) 2002-10-24 2008-10-09 Siemens Ag Einrichtung der programmierbaren Logik
JP4011007B2 (ja) * 2003-01-15 2007-11-21 三洋電機株式会社 リコンフィギュラブル回路を備えた集積回路装置および処理装置
DE102004044976A1 (de) * 2004-09-16 2006-03-30 Siemens Ag Rechnereinrichtung mit rekonfigurierbarer Architektur

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
Effective and efficient FPGA synthesisthroughgeneralfunctional decomposition. JOZWIAK L等.JOURNAL OF SYSTEM ARCHITECTURE,Vol.49 No.4. 2003
Effective and efficient FPGA synthesisthroughgeneralfunctional decomposition. JOZWIAK L等.JOURNAL OF SYSTEM ARCHITECTURE,Vol.49 No.4. 2003 *
PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM,2003.PROCEEDINGS.INTERNATIONAL. HOFFMANN R等,GCA:a massively parallel model,IEEE. 2003
PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM,2003.PROCEEDINGS.INTERNATIONAL. HOFFMANN R等,GCA:a massively parallel model,IEEE. 2003 *

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Publication number Publication date
WO2005078599A1 (de) 2005-08-25
JP2012074051A (ja) 2012-04-12
US7352205B2 (en) 2008-04-01
US20070171101A1 (en) 2007-07-26
CN1918560A (zh) 2007-02-21
JP2007522571A (ja) 2007-08-09
DE102005005073B4 (de) 2009-05-07
DE102005005073A1 (de) 2005-09-08
JP5027515B2 (ja) 2012-09-19

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