JP2007521538A5 - - Google Patents

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Publication number
JP2007521538A5
JP2007521538A5 JP2005509229A JP2005509229A JP2007521538A5 JP 2007521538 A5 JP2007521538 A5 JP 2007521538A5 JP 2005509229 A JP2005509229 A JP 2005509229A JP 2005509229 A JP2005509229 A JP 2005509229A JP 2007521538 A5 JP2007521538 A5 JP 2007521538A5
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JP
Japan
Prior art keywords
stage
unit
system clock
register
input
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JP2005509229A
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English (en)
Japanese (ja)
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JP2007521538A (ja
JP4524251B2 (ja
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Priority claimed from PCT/US2003/026531 external-priority patent/WO2005031565A1/en
Publication of JP2007521538A publication Critical patent/JP2007521538A/ja
Publication of JP2007521538A5 publication Critical patent/JP2007521538A5/ja
Application granted granted Critical
Publication of JP4524251B2 publication Critical patent/JP4524251B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2005509229A 2003-08-26 2003-08-26 要求駆動型クロック・スロットリング電力低減を用いるプロセッサ Expired - Fee Related JP4524251B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2003/026531 WO2005031565A1 (en) 2002-07-02 2003-08-26 Processor with demand-driven clock throttling for power reduction

Publications (3)

Publication Number Publication Date
JP2007521538A JP2007521538A (ja) 2007-08-02
JP2007521538A5 true JP2007521538A5 (https=) 2009-07-30
JP4524251B2 JP4524251B2 (ja) 2010-08-11

Family

ID=37390854

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005509229A Expired - Fee Related JP4524251B2 (ja) 2003-08-26 2003-08-26 要求駆動型クロック・スロットリング電力低減を用いるプロセッサ

Country Status (5)

Country Link
EP (1) EP1658560B1 (https=)
JP (1) JP4524251B2 (https=)
CN (1) CN100399262C (https=)
AT (1) ATE433581T1 (https=)
DE (1) DE60327953D1 (https=)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8006070B2 (en) * 2007-12-05 2011-08-23 International Business Machines Corporation Method and apparatus for inhibiting fetch throttling when a processor encounters a low confidence branch instruction in an information handling system
JP5311234B2 (ja) * 2008-04-09 2013-10-09 日本電気株式会社 計算機システムとその動作方法
JP2011044072A (ja) * 2009-08-24 2011-03-03 Panasonic Corp アイドル状態検出回路、半導体集積回路、信号処理装置、アイドル状態検出方法
CN102129286B (zh) * 2010-01-15 2013-04-24 炬力集成电路设计有限公司 实时时钟电路及包含实时时钟电路的芯片和数码设备
JP2014048972A (ja) * 2012-08-31 2014-03-17 Fujitsu Ltd 処理装置、情報処理装置、及び消費電力管理方法
JP5928272B2 (ja) * 2012-09-18 2016-06-01 富士通株式会社 半導体集積回路及びコンパイラ
CN104102327B (zh) * 2014-07-28 2017-02-15 联想(北京)有限公司 一种工作处理器的控制电路和电子设备
US20170090508A1 (en) * 2015-09-25 2017-03-30 Qualcomm Incorporated Method and apparatus for effective clock scaling at exposed cache stalls
CN112712829B (zh) * 2019-10-24 2024-07-02 珠海格力电器股份有限公司 一种跨时钟域的寄存器读写电路及方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2762670B2 (ja) * 1990-03-30 1998-06-04 松下電器産業株式会社 データ処理装置
US5416911A (en) * 1993-02-02 1995-05-16 International Business Machines Corporation Performance enhancement for load multiple register instruction
JP2636695B2 (ja) * 1993-08-03 1997-07-30 日本電気株式会社 パイプライン処理回路
JP3562215B2 (ja) * 1997-05-13 2004-09-08 セイコーエプソン株式会社 マイクロコンピュータ及び電子機器
US5987620A (en) * 1997-09-19 1999-11-16 Thang Tran Method and apparatus for a self-timed and self-enabled distributed clock
AU9798798A (en) * 1997-10-10 1999-05-03 Rambus Incorporated Power control system for synchronous memory device
US6112297A (en) * 1998-02-10 2000-08-29 International Business Machines Corporation Apparatus and method for processing misaligned load instructions in a processor supporting out of order execution
US6990598B2 (en) * 2001-03-21 2006-01-24 Gallitzin Allegheny Llc Low power reconfigurable systems and methods

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