JP2007515066A5 - - Google Patents

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Publication number
JP2007515066A5
JP2007515066A5 JP2006544622A JP2006544622A JP2007515066A5 JP 2007515066 A5 JP2007515066 A5 JP 2007515066A5 JP 2006544622 A JP2006544622 A JP 2006544622A JP 2006544622 A JP2006544622 A JP 2006544622A JP 2007515066 A5 JP2007515066 A5 JP 2007515066A5
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JP
Japan
Prior art keywords
semiconductor device
region
producing
semiconductor substrate
amorphous layer
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Withdrawn
Application number
JP2006544622A
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English (en)
Japanese (ja)
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JP2007515066A (ja
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Publication date
Application filed filed Critical
Priority claimed from PCT/IB2004/052644 external-priority patent/WO2005062354A1/en
Publication of JP2007515066A publication Critical patent/JP2007515066A/ja
Publication of JP2007515066A5 publication Critical patent/JP2007515066A5/ja
Withdrawn legal-status Critical Current

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JP2006544622A 2003-12-18 2004-12-02 固相エピタキシャル再成長を用いて接合の漏損を低減させた半導体基板及び同半導体基板の生産方法 Withdrawn JP2007515066A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP03104781 2003-12-18
PCT/IB2004/052644 WO2005062354A1 (en) 2003-12-18 2004-12-02 A semiconductor substrate with solid phase epitaxial regrowth with reduced junction leakage and method of producing same

Publications (2)

Publication Number Publication Date
JP2007515066A JP2007515066A (ja) 2007-06-07
JP2007515066A5 true JP2007515066A5 (enExample) 2008-01-24

Family

ID=34707259

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006544622A Withdrawn JP2007515066A (ja) 2003-12-18 2004-12-02 固相エピタキシャル再成長を用いて接合の漏損を低減させた半導体基板及び同半導体基板の生産方法

Country Status (6)

Country Link
US (1) US8187959B2 (enExample)
EP (1) EP1697978A1 (enExample)
JP (1) JP2007515066A (enExample)
CN (1) CN100477092C (enExample)
TW (1) TW200525762A (enExample)
WO (1) WO2005062354A1 (enExample)

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US8995204B2 (en) 2011-06-23 2015-03-31 Suvolta, Inc. Circuit devices and methods having adjustable transistor body bias
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US8614128B1 (en) 2011-08-23 2013-12-24 Suvolta, Inc. CMOS structures and processes based on selective thinning
US8713511B1 (en) 2011-09-16 2014-04-29 Suvolta, Inc. Tools and methods for yield-aware semiconductor manufacturing process target generation
US9236466B1 (en) 2011-10-07 2016-01-12 Mie Fujitsu Semiconductor Limited Analog circuits having improved insulated gate transistors, and methods therefor
US8895327B1 (en) 2011-12-09 2014-11-25 Suvolta, Inc. Tipless transistors, short-tip transistors, and methods and circuits therefor
US8819603B1 (en) 2011-12-15 2014-08-26 Suvolta, Inc. Memory circuits and methods of making and designing the same
US8883600B1 (en) 2011-12-22 2014-11-11 Suvolta, Inc. Transistor having reduced junction leakage and methods of forming thereof
US8599623B1 (en) 2011-12-23 2013-12-03 Suvolta, Inc. Circuits and methods for measuring circuit elements in an integrated circuit device
US8970289B1 (en) 2012-01-23 2015-03-03 Suvolta, Inc. Circuits and devices for generating bi-directional body bias voltages, and methods therefor
US8877619B1 (en) 2012-01-23 2014-11-04 Suvolta, Inc. Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom
US9093550B1 (en) 2012-01-31 2015-07-28 Mie Fujitsu Semiconductor Limited Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same
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US9299698B2 (en) 2012-06-27 2016-03-29 Mie Fujitsu Semiconductor Limited Semiconductor structure with multiple transistors having various threshold voltages
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US9112057B1 (en) 2012-09-18 2015-08-18 Mie Fujitsu Semiconductor Limited Semiconductor devices with dopant migration suppression and method of fabrication thereof
US9041126B2 (en) 2012-09-21 2015-05-26 Mie Fujitsu Semiconductor Limited Deeply depleted MOS transistors having a screening layer and methods thereof
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US9070477B1 (en) 2012-12-12 2015-06-30 Mie Fujitsu Semiconductor Limited Bit interleaved low voltage static random access memory (SRAM) and related methods
US9112484B1 (en) 2012-12-20 2015-08-18 Mie Fujitsu Semiconductor Limited Integrated circuit process and bias monitors and related methods
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