JP2007507791A5 - - Google Patents

Download PDF

Info

Publication number
JP2007507791A5
JP2007507791A5 JP2006533824A JP2006533824A JP2007507791A5 JP 2007507791 A5 JP2007507791 A5 JP 2007507791A5 JP 2006533824 A JP2006533824 A JP 2006533824A JP 2006533824 A JP2006533824 A JP 2006533824A JP 2007507791 A5 JP2007507791 A5 JP 2007507791A5
Authority
JP
Japan
Prior art keywords
instruction
trace
cache
exception
trace cache
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006533824A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007507791A (ja
Filing date
Publication date
Priority claimed from US10/676,437 external-priority patent/US7133969B2/en
Application filed filed Critical
Publication of JP2007507791A publication Critical patent/JP2007507791A/ja
Publication of JP2007507791A5 publication Critical patent/JP2007507791A5/ja
Pending legal-status Critical Current

Links

JP2006533824A 2003-10-01 2004-06-28 トレースキャッシュベースのプロセッサ中の例外命令を処理するためのシステム及び方法 Pending JP2007507791A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/676,437 US7133969B2 (en) 2003-10-01 2003-10-01 System and method for handling exceptional instructions in a trace cache based processor
PCT/US2004/020721 WO2005041024A2 (en) 2003-10-01 2004-06-28 System and method for handling exceptional instructions in a trace cache based processor

Publications (2)

Publication Number Publication Date
JP2007507791A JP2007507791A (ja) 2007-03-29
JP2007507791A5 true JP2007507791A5 (enExample) 2007-07-19

Family

ID=34393582

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006533824A Pending JP2007507791A (ja) 2003-10-01 2004-06-28 トレースキャッシュベースのプロセッサ中の例外命令を処理するためのシステム及び方法

Country Status (8)

Country Link
US (1) US7133969B2 (enExample)
JP (1) JP2007507791A (enExample)
KR (1) KR100993018B1 (enExample)
CN (1) CN100407134C (enExample)
DE (1) DE112004001854T5 (enExample)
GB (1) GB2422464B (enExample)
TW (1) TWI352927B (enExample)
WO (1) WO2005041024A2 (enExample)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8069336B2 (en) * 2003-12-03 2011-11-29 Globalfoundries Inc. Transitioning from instruction cache to trace cache on label boundaries
US7437512B2 (en) * 2004-02-26 2008-10-14 Marvell International Ltd. Low power semi-trace instruction/trace hybrid cache with logic for indexing the trace cache under certain conditions
US7197630B1 (en) 2004-04-12 2007-03-27 Advanced Micro Devices, Inc. Method and system for changing the executable status of an operation following a branch misprediction without refetching the operation
US7365007B2 (en) * 2004-06-30 2008-04-29 Intel Corporation Interconnects with direct metalization and conductive polymer
US7568070B2 (en) * 2005-07-29 2009-07-28 Qualcomm Incorporated Instruction cache having fixed number of variable length instructions
US7987342B1 (en) 2005-09-28 2011-07-26 Oracle America, Inc. Trace unit with a decoder, a basic-block cache, a multi-block cache, and sequencer
US7966479B1 (en) 2005-09-28 2011-06-21 Oracle America, Inc. Concurrent vs. low power branch prediction
US7953961B1 (en) 2005-09-28 2011-05-31 Oracle America, Inc. Trace unit with an op path from a decoder (bypass mode) and from a basic-block builder
US7783863B1 (en) 2005-09-28 2010-08-24 Oracle America, Inc. Graceful degradation in a trace-based processor
US7877630B1 (en) 2005-09-28 2011-01-25 Oracle America, Inc. Trace based rollback of a speculatively updated cache
US7953933B1 (en) 2005-09-28 2011-05-31 Oracle America, Inc. Instruction cache, decoder circuit, basic block cache circuit and multi-block cache circuit
US8024522B1 (en) 2005-09-28 2011-09-20 Oracle America, Inc. Memory ordering queue/versioning cache circuit
US7814298B1 (en) 2005-09-28 2010-10-12 Oracle America, Inc. Promoting and appending traces in an instruction processing circuit based upon a bias value
US7546420B1 (en) 2005-09-28 2009-06-09 Sun Microsystems, Inc. Efficient trace cache management during self-modifying code processing
US8032710B1 (en) 2005-09-28 2011-10-04 Oracle America, Inc. System and method for ensuring coherency in trace execution
US7849292B1 (en) 2005-09-28 2010-12-07 Oracle America, Inc. Flag optimization of a trace
US8019944B1 (en) 2005-09-28 2011-09-13 Oracle America, Inc. Checking for a memory ordering violation after a speculative cache write
US8051247B1 (en) 2005-09-28 2011-11-01 Oracle America, Inc. Trace based deallocation of entries in a versioning cache circuit
US7870369B1 (en) 2005-09-28 2011-01-11 Oracle America, Inc. Abort prioritization in a trace-based processor
US8037285B1 (en) 2005-09-28 2011-10-11 Oracle America, Inc. Trace unit
US8370576B1 (en) 2005-09-28 2013-02-05 Oracle America, Inc. Cache rollback acceleration via a bank based versioning cache ciruit
US7949854B1 (en) 2005-09-28 2011-05-24 Oracle America, Inc. Trace unit with a trace builder
US8499293B1 (en) 2005-09-28 2013-07-30 Oracle America, Inc. Symbolic renaming optimization of a trace
US8015359B1 (en) 2005-09-28 2011-09-06 Oracle America, Inc. Method and system for utilizing a common structure for trace verification and maintaining coherency in an instruction processing circuit
US7937564B1 (en) 2005-09-28 2011-05-03 Oracle America, Inc. Emit vector optimization of a trace
US7797517B1 (en) 2005-11-18 2010-09-14 Oracle America, Inc. Trace optimization via fusing operations of a target architecture operation set
CN100444119C (zh) * 2005-12-28 2008-12-17 中国科学院计算技术研究所 一种面向服务体系结构中消息层异常处理方法
US8370609B1 (en) 2006-09-27 2013-02-05 Oracle America, Inc. Data cache rollbacks for failed speculative traces with memory operations
US8010745B1 (en) 2006-09-27 2011-08-30 Oracle America, Inc. Rolling back a speculative update of a non-modifiable cache line
US8074060B2 (en) * 2008-11-25 2011-12-06 Via Technologies, Inc. Out-of-order execution microprocessor that selectively initiates instruction retirement early
CN102360344B (zh) * 2011-10-10 2014-03-12 西安交通大学 矩阵处理器及其指令集和嵌入式系统
US8935574B2 (en) 2011-12-16 2015-01-13 Advanced Micro Devices, Inc. Correlating traces in a computing system
US8832500B2 (en) 2012-08-10 2014-09-09 Advanced Micro Devices, Inc. Multiple clock domain tracing
US8959398B2 (en) 2012-08-16 2015-02-17 Advanced Micro Devices, Inc. Multiple clock domain debug capability
GB2553582B (en) * 2016-09-13 2020-07-08 Advanced Risc Mach Ltd An apparatus and method for generating and processing a trace stream indicative of instruction execution by processing circuitry
US12204430B2 (en) * 2020-09-26 2025-01-21 Intel Corporation Monitoring performance cost of events

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3896419A (en) * 1974-01-17 1975-07-22 Honeywell Inf Systems Cache memory store in a processor of a data processing system
WO1993017385A1 (en) * 1992-02-27 1993-09-02 Intel Corporation Dynamic flow instruction cache memory
US6167536A (en) * 1997-04-08 2000-12-26 Advanced Micro Devices, Inc. Trace cache for a microprocessor-based device
US6018786A (en) * 1997-10-23 2000-01-25 Intel Corporation Trace based instruction caching
US6185675B1 (en) * 1997-10-24 2001-02-06 Advanced Micro Devices, Inc. Basic block oriented trace cache utilizing a basic block sequence buffer to indicate program order of cached basic blocks
US5930497A (en) * 1997-12-11 1999-07-27 International Business Machines Corporation Method and means for generation of realistic access patterns in storage subsystem benchmarking and other tests
US6182210B1 (en) * 1997-12-16 2001-01-30 Intel Corporation Processor having multiple program counters and trace buffers outside an execution pipeline
GB2381101B (en) 1998-04-20 2003-06-25 Intel Corp System and method for maintaining branch information
US6256727B1 (en) 1998-05-12 2001-07-03 International Business Machines Corporation Method and system for fetching noncontiguous instructions in a single clock cycle
US6339822B1 (en) * 1998-10-02 2002-01-15 Advanced Micro Devices, Inc. Using padded instructions in a block-oriented cache
US6247097B1 (en) * 1999-01-22 2001-06-12 International Business Machines Corporation Aligned instruction cache handling of instruction fetches across multiple predicted branch instructions
US6345295B1 (en) * 1999-01-22 2002-02-05 International Business Machines Corporation Conducting traces in a computer system attachment network
US6535905B1 (en) * 1999-04-29 2003-03-18 Intel Corporation Method and apparatus for thread switching within a multithreaded processor
US6357016B1 (en) * 1999-12-09 2002-03-12 Intel Corporation Method and apparatus for disabling a clock signal within a multithreaded processor
US6889319B1 (en) * 1999-12-09 2005-05-03 Intel Corporation Method and apparatus for entering and exiting multiple threads within a multithreaded processor
US6578128B1 (en) * 2001-03-29 2003-06-10 Emc Corporation Address management for a shared memory region on a multi-processor controller board
US20020144101A1 (en) * 2001-03-30 2002-10-03 Hong Wang Caching DAG traces
US6973543B1 (en) * 2001-07-12 2005-12-06 Advanced Micro Devices, Inc. Partial directory cache for reducing probe traffic in multiprocessor systems
US6823428B2 (en) * 2002-05-17 2004-11-23 International Business Preventing cache floods from sequential streams
US7139902B2 (en) * 2002-10-29 2006-11-21 Broadcom Corporation Implementation of an efficient instruction fetch pipeline utilizing a trace cache
US7024537B2 (en) * 2003-01-21 2006-04-04 Advanced Micro Devices, Inc. Data speculation based on addressing patterns identifying dual-purpose register
US7143273B2 (en) * 2003-03-31 2006-11-28 Intel Corporation Method and apparatus for dynamic branch prediction utilizing multiple stew algorithms for indexing a global history
US7003629B1 (en) * 2003-07-08 2006-02-21 Advanced Micro Devices, Inc. System and method of identifying liveness groups within traces stored in a trace cache
US8069336B2 (en) * 2003-12-03 2011-11-29 Globalfoundries Inc. Transitioning from instruction cache to trace cache on label boundaries

Similar Documents

Publication Publication Date Title
JP2007507791A5 (enExample)
KR102771877B1 (ko) 이벤트 기동된 프로그래머블 프리페처
US8990597B2 (en) Instruction for enabling a processor wait state
US6651158B2 (en) Determination of approaching instruction starvation of threads based on a plurality of conditions
US7401211B2 (en) Method for converting pipeline stalls caused by instructions with long latency memory accesses to pipeline flushes in a multithreaded processor
CN104077106B (zh) 具有原生切换机制的非对称多核心处理器
JP2006509282A (ja) マルチスレッディング・リサイクルおよびディスパッチ機構
US10628160B2 (en) Selective poisoning of data during runahead
TWI476580B (zh) 偵測指令提取錯誤以及從指令提取錯誤復原的方法、裝置及電腦系統
JPH10506739A (ja) スーパースカラプロセッサにおけるトラップを検出して実行する装置
US9891972B2 (en) Lazy runahead operation for a microprocessor
US20140164738A1 (en) Instruction categorization for runahead operation
Morancho et al. Recovery mechanism for latency misprediction
US9400655B2 (en) Technique for freeing renamed registers
US7941646B2 (en) Completion continue on thread switch based on instruction progress metric mechanism for a microprocessor
EP1967950A2 (en) Multiprocessor system for continuing program execution upon detection of abnormality
US7370181B2 (en) Single stepping a virtual machine guest using a reorder buffer
TW201931109A (zh) 用於預執行資料相依之負載的薄片結構
US6367002B1 (en) Apparatus and method for fetching instructions for a program-controlled unit
EP2717156A1 (en) Speculative privilege elevation
JP2011129130A5 (enExample)
Hu et al. Scheduling reusable instructions for power reduction
CN104808996B (zh) 减少处理引擎中的加载-存储冲突惩罚的系统和方法
JP2008299740A5 (enExample)
JPH09244895A5 (enExample)