GB2381101B - System and method for maintaining branch information - Google Patents

System and method for maintaining branch information

Info

Publication number
GB2381101B
GB2381101B GB0229082A GB0229082A GB2381101B GB 2381101 B GB2381101 B GB 2381101B GB 0229082 A GB0229082 A GB 0229082A GB 0229082 A GB0229082 A GB 0229082A GB 2381101 B GB2381101 B GB 2381101B
Authority
GB
Grant status
Grant
Patent type
Prior art keywords
system
method
branch information
maintaining branch
maintaining
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB0229082A
Other versions
GB0229082D0 (en )
GB2381101A (en )
Inventor
Sa V Reynold D
Alan B Kyker
Gad S Sheaffer
Gustavo P Espinosa
Stavros Kalafatis
Rebecca E Hebda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Grant date

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802Instruction prefetching
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802Instruction prefetching
    • G06F9/3804Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802Instruction prefetching
    • G06F9/3808Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
    • G06F9/3842Speculative instruction execution
    • G06F9/3848Speculative instruction execution using hybrid branch prediction, e.g. selection between prediction techniques
GB0229082A 1998-04-20 1999-04-20 System and method for maintaining branch information Expired - Fee Related GB2381101B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US09063205 US6055630A (en) 1998-04-20 1998-04-20 System and method for processing a plurality of branch instructions by a plurality of storage devices and pipeline units
GB0021233A GB2350219B (en) 1998-04-20 1999-04-20 System and method for maintaining branch information

Publications (3)

Publication Number Publication Date
GB0229082D0 GB0229082D0 (en) 2003-01-15
GB2381101A true GB2381101A (en) 2003-04-23
GB2381101B true GB2381101B (en) 2003-06-25

Family

ID=26244931

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0229082A Expired - Fee Related GB2381101B (en) 1998-04-20 1999-04-20 System and method for maintaining branch information

Country Status (1)

Country Link
GB (1) GB2381101B (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7133969B2 (en) 2003-10-01 2006-11-07 Advanced Micro Devices, Inc. System and method for handling exceptional instructions in a trace cache based processor
US8069336B2 (en) 2003-12-03 2011-11-29 Globalfoundries Inc. Transitioning from instruction cache to trace cache on label boundaries
US8935574B2 (en) 2011-12-16 2015-01-13 Advanced Micro Devices, Inc. Correlating traces in a computing system
US8832500B2 (en) 2012-08-10 2014-09-09 Advanced Micro Devices, Inc. Multiple clock domain tracing
US8959398B2 (en) 2012-08-16 2015-02-17 Advanced Micro Devices, Inc. Multiple clock domain debug capability

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5542109A (en) * 1994-08-31 1996-07-30 Exponential Technology, Inc. Address tracking and branch resolution in a processor with multiple execution pipelines and instruction stream discontinuities
WO1998000778A1 (en) * 1996-06-28 1998-01-08 Intel Corporation A processor and method for speculatively executing instructions from multiple instruction streams indicated by a branch instruction
US5748932A (en) * 1990-02-26 1998-05-05 Advanced Micro Devices, Inc. Cache memory system for dynamically altering single cache memory line as either branch target entry or prefetch instruction queue based upon instruction sequence

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5748932A (en) * 1990-02-26 1998-05-05 Advanced Micro Devices, Inc. Cache memory system for dynamically altering single cache memory line as either branch target entry or prefetch instruction queue based upon instruction sequence
US5542109A (en) * 1994-08-31 1996-07-30 Exponential Technology, Inc. Address tracking and branch resolution in a processor with multiple execution pipelines and instruction stream discontinuities
WO1998000778A1 (en) * 1996-06-28 1998-01-08 Intel Corporation A processor and method for speculatively executing instructions from multiple instruction streams indicated by a branch instruction

Also Published As

Publication number Publication date Type
GB0229082D0 (en) 2003-01-15 grant
GB2381101A (en) 2003-04-23 application

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20100420