TWI352927B - System and method for handling exceptional instruc - Google Patents

System and method for handling exceptional instruc Download PDF

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Publication number
TWI352927B
TWI352927B TW093129526A TW93129526A TWI352927B TW I352927 B TWI352927 B TW I352927B TW 093129526 A TW093129526 A TW 093129526A TW 93129526 A TW93129526 A TW 93129526A TW I352927 B TWI352927 B TW I352927B
Authority
TW
Taiwan
Prior art keywords
instruction
cache
tracking
group
instructions
Prior art date
Application number
TW093129526A
Other languages
English (en)
Chinese (zh)
Other versions
TW200517955A (en
Inventor
Mitchell Alsup
Gregory William Smaus
James K Pickett
Brian D Mcminn
Michael A Filippo
Benjamin T Sander
Original Assignee
Globalfoundries Us Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Globalfoundries Us Inc filed Critical Globalfoundries Us Inc
Publication of TW200517955A publication Critical patent/TW200517955A/zh
Application granted granted Critical
Publication of TWI352927B publication Critical patent/TWI352927B/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Debugging And Monitoring (AREA)
TW093129526A 2003-10-01 2004-09-30 System and method for handling exceptional instruc TWI352927B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/676,437 US7133969B2 (en) 2003-10-01 2003-10-01 System and method for handling exceptional instructions in a trace cache based processor

Publications (2)

Publication Number Publication Date
TW200517955A TW200517955A (en) 2005-06-01
TWI352927B true TWI352927B (en) 2011-11-21

Family

ID=34393582

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093129526A TWI352927B (en) 2003-10-01 2004-09-30 System and method for handling exceptional instruc

Country Status (8)

Country Link
US (1) US7133969B2 (enExample)
JP (1) JP2007507791A (enExample)
KR (1) KR100993018B1 (enExample)
CN (1) CN100407134C (enExample)
DE (1) DE112004001854T5 (enExample)
GB (1) GB2422464B (enExample)
TW (1) TWI352927B (enExample)
WO (1) WO2005041024A2 (enExample)

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US11561882B2 (en) 2016-09-13 2023-01-24 Arm Limited Apparatus and method for generating and processing a trace stream indicative of instruction execution by processing circuitry

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US7437512B2 (en) * 2004-02-26 2008-10-14 Marvell International Ltd. Low power semi-trace instruction/trace hybrid cache with logic for indexing the trace cache under certain conditions
US7197630B1 (en) 2004-04-12 2007-03-27 Advanced Micro Devices, Inc. Method and system for changing the executable status of an operation following a branch misprediction without refetching the operation
US7365007B2 (en) * 2004-06-30 2008-04-29 Intel Corporation Interconnects with direct metalization and conductive polymer
US7568070B2 (en) * 2005-07-29 2009-07-28 Qualcomm Incorporated Instruction cache having fixed number of variable length instructions
US7987342B1 (en) 2005-09-28 2011-07-26 Oracle America, Inc. Trace unit with a decoder, a basic-block cache, a multi-block cache, and sequencer
US7966479B1 (en) 2005-09-28 2011-06-21 Oracle America, Inc. Concurrent vs. low power branch prediction
US7953961B1 (en) 2005-09-28 2011-05-31 Oracle America, Inc. Trace unit with an op path from a decoder (bypass mode) and from a basic-block builder
US7783863B1 (en) 2005-09-28 2010-08-24 Oracle America, Inc. Graceful degradation in a trace-based processor
US7877630B1 (en) 2005-09-28 2011-01-25 Oracle America, Inc. Trace based rollback of a speculatively updated cache
US7953933B1 (en) 2005-09-28 2011-05-31 Oracle America, Inc. Instruction cache, decoder circuit, basic block cache circuit and multi-block cache circuit
US8024522B1 (en) 2005-09-28 2011-09-20 Oracle America, Inc. Memory ordering queue/versioning cache circuit
US7814298B1 (en) 2005-09-28 2010-10-12 Oracle America, Inc. Promoting and appending traces in an instruction processing circuit based upon a bias value
US7546420B1 (en) 2005-09-28 2009-06-09 Sun Microsystems, Inc. Efficient trace cache management during self-modifying code processing
US8032710B1 (en) 2005-09-28 2011-10-04 Oracle America, Inc. System and method for ensuring coherency in trace execution
US7849292B1 (en) 2005-09-28 2010-12-07 Oracle America, Inc. Flag optimization of a trace
US8019944B1 (en) 2005-09-28 2011-09-13 Oracle America, Inc. Checking for a memory ordering violation after a speculative cache write
US8051247B1 (en) 2005-09-28 2011-11-01 Oracle America, Inc. Trace based deallocation of entries in a versioning cache circuit
US7870369B1 (en) 2005-09-28 2011-01-11 Oracle America, Inc. Abort prioritization in a trace-based processor
US8037285B1 (en) 2005-09-28 2011-10-11 Oracle America, Inc. Trace unit
US8370576B1 (en) 2005-09-28 2013-02-05 Oracle America, Inc. Cache rollback acceleration via a bank based versioning cache ciruit
US7949854B1 (en) 2005-09-28 2011-05-24 Oracle America, Inc. Trace unit with a trace builder
US8499293B1 (en) 2005-09-28 2013-07-30 Oracle America, Inc. Symbolic renaming optimization of a trace
US8015359B1 (en) 2005-09-28 2011-09-06 Oracle America, Inc. Method and system for utilizing a common structure for trace verification and maintaining coherency in an instruction processing circuit
US7937564B1 (en) 2005-09-28 2011-05-03 Oracle America, Inc. Emit vector optimization of a trace
US7797517B1 (en) 2005-11-18 2010-09-14 Oracle America, Inc. Trace optimization via fusing operations of a target architecture operation set
CN100444119C (zh) * 2005-12-28 2008-12-17 中国科学院计算技术研究所 一种面向服务体系结构中消息层异常处理方法
US8370609B1 (en) 2006-09-27 2013-02-05 Oracle America, Inc. Data cache rollbacks for failed speculative traces with memory operations
US8010745B1 (en) 2006-09-27 2011-08-30 Oracle America, Inc. Rolling back a speculative update of a non-modifiable cache line
US8074060B2 (en) * 2008-11-25 2011-12-06 Via Technologies, Inc. Out-of-order execution microprocessor that selectively initiates instruction retirement early
CN102360344B (zh) * 2011-10-10 2014-03-12 西安交通大学 矩阵处理器及其指令集和嵌入式系统
US8935574B2 (en) 2011-12-16 2015-01-13 Advanced Micro Devices, Inc. Correlating traces in a computing system
US8832500B2 (en) 2012-08-10 2014-09-09 Advanced Micro Devices, Inc. Multiple clock domain tracing
US8959398B2 (en) 2012-08-16 2015-02-17 Advanced Micro Devices, Inc. Multiple clock domain debug capability
US12204430B2 (en) * 2020-09-26 2025-01-21 Intel Corporation Monitoring performance cost of events

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11561882B2 (en) 2016-09-13 2023-01-24 Arm Limited Apparatus and method for generating and processing a trace stream indicative of instruction execution by processing circuitry
TWI820005B (zh) * 2016-09-13 2023-11-01 英商Ａｒｍ股份有限公司 用於產生及處理指示由處理電路系統所進行之指令執行的追蹤流的裝置及方法

Also Published As

Publication number Publication date
WO2005041024A3 (en) 2006-05-11
KR100993018B1 (ko) 2010-11-09
KR20060108644A (ko) 2006-10-18
GB2422464B (en) 2007-02-14
JP2007507791A (ja) 2007-03-29
GB2422464A (en) 2006-07-26
CN1864131A (zh) 2006-11-15
US20050076180A1 (en) 2005-04-07
DE112004001854T5 (de) 2006-08-03
CN100407134C (zh) 2008-07-30
WO2005041024A2 (en) 2005-05-06
TW200517955A (en) 2005-06-01
GB0606179D0 (en) 2006-05-10
US7133969B2 (en) 2006-11-07

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