KR100993018B1 - 트레이스 캐시 기반 프로세서에서 예외 명령어들을 처리하는 시스템 및 방법 - Google Patents

트레이스 캐시 기반 프로세서에서 예외 명령어들을 처리하는 시스템 및 방법 Download PDF

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KR100993018B1
KR100993018B1 KR1020067008482A KR20067008482A KR100993018B1 KR 100993018 B1 KR100993018 B1 KR 100993018B1 KR 1020067008482 A KR1020067008482 A KR 1020067008482A KR 20067008482 A KR20067008482 A KR 20067008482A KR 100993018 B1 KR100993018 B1 KR 100993018B1
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trace
instructions
instruction
cache
exception
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KR20060108644A (ko
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미?M 알서프
그레고리 윌리암 스마우스
제임스 케이. 픽케트
브라이언 디. 엠친
마이클 에이. 필리포
벤자민 티. 샌더
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글로벌파운드리즈 인크.
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Debugging And Monitoring (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
KR1020067008482A 2003-10-01 2004-06-28 트레이스 캐시 기반 프로세서에서 예외 명령어들을 처리하는 시스템 및 방법 Expired - Fee Related KR100993018B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/676,437 US7133969B2 (en) 2003-10-01 2003-10-01 System and method for handling exceptional instructions in a trace cache based processor
US10/676,437 2003-10-01

Publications (2)

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KR20060108644A KR20060108644A (ko) 2006-10-18
KR100993018B1 true KR100993018B1 (ko) 2010-11-09

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Country Status (8)

Country Link
US (1) US7133969B2 (enExample)
JP (1) JP2007507791A (enExample)
KR (1) KR100993018B1 (enExample)
CN (1) CN100407134C (enExample)
DE (1) DE112004001854T5 (enExample)
GB (1) GB2422464B (enExample)
TW (1) TWI352927B (enExample)
WO (1) WO2005041024A2 (enExample)

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US7365007B2 (en) * 2004-06-30 2008-04-29 Intel Corporation Interconnects with direct metalization and conductive polymer
US7568070B2 (en) * 2005-07-29 2009-07-28 Qualcomm Incorporated Instruction cache having fixed number of variable length instructions
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US8019944B1 (en) 2005-09-28 2011-09-13 Oracle America, Inc. Checking for a memory ordering violation after a speculative cache write
US8037285B1 (en) 2005-09-28 2011-10-11 Oracle America, Inc. Trace unit
US8032710B1 (en) 2005-09-28 2011-10-04 Oracle America, Inc. System and method for ensuring coherency in trace execution
US7966479B1 (en) 2005-09-28 2011-06-21 Oracle America, Inc. Concurrent vs. low power branch prediction
US8015359B1 (en) 2005-09-28 2011-09-06 Oracle America, Inc. Method and system for utilizing a common structure for trace verification and maintaining coherency in an instruction processing circuit
US8370576B1 (en) 2005-09-28 2013-02-05 Oracle America, Inc. Cache rollback acceleration via a bank based versioning cache ciruit
US7676634B1 (en) 2005-09-28 2010-03-09 Sun Microsystems, Inc. Selective trace cache invalidation for self-modifying code via memory aging
US8499293B1 (en) 2005-09-28 2013-07-30 Oracle America, Inc. Symbolic renaming optimization of a trace
US7870369B1 (en) 2005-09-28 2011-01-11 Oracle America, Inc. Abort prioritization in a trace-based processor
US7814298B1 (en) 2005-09-28 2010-10-12 Oracle America, Inc. Promoting and appending traces in an instruction processing circuit based upon a bias value
US7783863B1 (en) 2005-09-28 2010-08-24 Oracle America, Inc. Graceful degradation in a trace-based processor
US7949854B1 (en) 2005-09-28 2011-05-24 Oracle America, Inc. Trace unit with a trace builder
US7987342B1 (en) 2005-09-28 2011-07-26 Oracle America, Inc. Trace unit with a decoder, a basic-block cache, a multi-block cache, and sequencer
US7937564B1 (en) 2005-09-28 2011-05-03 Oracle America, Inc. Emit vector optimization of a trace
US8051247B1 (en) 2005-09-28 2011-11-01 Oracle America, Inc. Trace based deallocation of entries in a versioning cache circuit
US7849292B1 (en) 2005-09-28 2010-12-07 Oracle America, Inc. Flag optimization of a trace
US8024522B1 (en) 2005-09-28 2011-09-20 Oracle America, Inc. Memory ordering queue/versioning cache circuit
US7953933B1 (en) 2005-09-28 2011-05-31 Oracle America, Inc. Instruction cache, decoder circuit, basic block cache circuit and multi-block cache circuit
US7877630B1 (en) 2005-09-28 2011-01-25 Oracle America, Inc. Trace based rollback of a speculatively updated cache
US7797517B1 (en) 2005-11-18 2010-09-14 Oracle America, Inc. Trace optimization via fusing operations of a target architecture operation set
CN100444119C (zh) * 2005-12-28 2008-12-17 中国科学院计算技术研究所 一种面向服务体系结构中消息层异常处理方法
US8010745B1 (en) 2006-09-27 2011-08-30 Oracle America, Inc. Rolling back a speculative update of a non-modifiable cache line
US8370609B1 (en) 2006-09-27 2013-02-05 Oracle America, Inc. Data cache rollbacks for failed speculative traces with memory operations
US8074060B2 (en) * 2008-11-25 2011-12-06 Via Technologies, Inc. Out-of-order execution microprocessor that selectively initiates instruction retirement early
CN102360344B (zh) * 2011-10-10 2014-03-12 西安交通大学 矩阵处理器及其指令集和嵌入式系统
US8935574B2 (en) 2011-12-16 2015-01-13 Advanced Micro Devices, Inc. Correlating traces in a computing system
US8832500B2 (en) 2012-08-10 2014-09-09 Advanced Micro Devices, Inc. Multiple clock domain tracing
US8959398B2 (en) 2012-08-16 2015-02-17 Advanced Micro Devices, Inc. Multiple clock domain debug capability
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US12204430B2 (en) * 2020-09-26 2025-01-21 Intel Corporation Monitoring performance cost of events

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US20010014941A1 (en) 1997-12-16 2001-08-16 Haitham Akkary Processor having multiple program counters and trace buffers outside an execution pipeline

Also Published As

Publication number Publication date
GB0606179D0 (en) 2006-05-10
WO2005041024A3 (en) 2006-05-11
JP2007507791A (ja) 2007-03-29
GB2422464B (en) 2007-02-14
TWI352927B (en) 2011-11-21
WO2005041024A2 (en) 2005-05-06
DE112004001854T5 (de) 2006-08-03
GB2422464A (en) 2006-07-26
US7133969B2 (en) 2006-11-07
TW200517955A (en) 2005-06-01
CN1864131A (zh) 2006-11-15
US20050076180A1 (en) 2005-04-07
CN100407134C (zh) 2008-07-30
KR20060108644A (ko) 2006-10-18

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