JP2007504549A5 - - Google Patents

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Publication number
JP2007504549A5
JP2007504549A5 JP2006525227A JP2006525227A JP2007504549A5 JP 2007504549 A5 JP2007504549 A5 JP 2007504549A5 JP 2006525227 A JP2006525227 A JP 2006525227A JP 2006525227 A JP2006525227 A JP 2006525227A JP 2007504549 A5 JP2007504549 A5 JP 2007504549A5
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JP
Japan
Prior art keywords
data processing
node
processing system
memory
port
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Application number
JP2006525227A
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English (en)
Japanese (ja)
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JP2007504549A (ja
JP4729490B2 (ja
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Application filed filed Critical
Priority claimed from PCT/IB2004/051491 external-priority patent/WO2005026964A2/en
Publication of JP2007504549A publication Critical patent/JP2007504549A/ja
Publication of JP2007504549A5 publication Critical patent/JP2007504549A5/ja
Application granted granted Critical
Publication of JP4729490B2 publication Critical patent/JP4729490B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2006525227A 2003-09-04 2004-08-19 データ処理システム Expired - Fee Related JP4729490B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP03103293.1 2003-09-04
EP03103293 2003-09-04
PCT/IB2004/051491 WO2005026964A2 (en) 2003-09-04 2004-08-19 Data processing system

Publications (3)

Publication Number Publication Date
JP2007504549A JP2007504549A (ja) 2007-03-01
JP2007504549A5 true JP2007504549A5 (OSRAM) 2007-10-11
JP4729490B2 JP4729490B2 (ja) 2011-07-20

Family

ID=34306924

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006525227A Expired - Fee Related JP4729490B2 (ja) 2003-09-04 2004-08-19 データ処理システム

Country Status (7)

Country Link
US (1) US7870347B2 (OSRAM)
EP (1) EP1671233B1 (OSRAM)
JP (1) JP4729490B2 (OSRAM)
KR (1) KR101109016B1 (OSRAM)
CN (1) CN100520748C (OSRAM)
AT (1) ATE534080T1 (OSRAM)
WO (1) WO2005026964A2 (OSRAM)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1751667B1 (en) 2004-05-18 2008-05-21 Koninklijke Philips Electronics N.V. Integrated circuit and method for buffering to optimize burst length in networks on chips
US7561584B1 (en) * 2005-11-09 2009-07-14 Sun Microsystems, Inc. Implementation of a graph property in a switching fabric for fast networking
CN103186501A (zh) * 2011-12-29 2013-07-03 中兴通讯股份有限公司 一种多处理器共享存储方法及系统
JP5992652B1 (ja) 2013-09-02 2016-09-14 フィリップス ライティング ホールディング ビー ヴィ 透明なコンピュータ構造
US20160164999A1 (en) * 2014-12-09 2016-06-09 International Business Machines Corporation Hybrid web storage model
CN107368523B (zh) * 2017-06-07 2020-05-12 武汉斗鱼网络科技有限公司 一种数据处理方法及系统
KR102109371B1 (ko) 2018-01-15 2020-05-12 주식회사 경인기계 팬 및 이를 포함하는 냉각탑
EP3798850B1 (en) * 2018-06-27 2025-11-19 Shanghai Cambricon Information Technology Co., Ltd On-chip code breakpoint debugging method, on-chip processor, and chip breakpoint debugging system
WO2020078470A1 (zh) * 2018-10-18 2020-04-23 上海寒武纪信息科技有限公司 片上网络数据处理方法及装置
US11250015B2 (en) 2020-02-07 2022-02-15 Coupang Corp. Systems and methods for low-latency aggregated-data provision
CN115311125A (zh) * 2022-07-04 2022-11-08 深圳市国微电子有限公司 图像处理方法、装置及芯片系统

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63236159A (ja) * 1987-03-25 1988-10-03 Hitachi Ltd 並列プロセツサのメモリアクセス方式
GB8713460D0 (en) * 1987-06-09 1987-07-15 Philips Nv Data processing system
GB8914352D0 (en) 1989-06-22 1989-08-09 Int Computers Ltd Multiprocessor data processing system
US5261067A (en) 1990-04-17 1993-11-09 North American Philips Corp. Method and apparatus for providing synchronized data cache operation for processors in a parallel processing system
CA2051029C (en) * 1990-11-30 1996-11-05 Pradeep S. Sindhu Arbitration of packet switched busses, including busses for shared memory multiprocessors
US5469542A (en) * 1991-07-22 1995-11-21 International Business Machines Corporation Serial diagnostic interface bus for multiprocessor systems
JP2819982B2 (ja) * 1993-03-18 1998-11-05 株式会社日立製作所 範囲指定可能なキャッシュ一致保証機能を有するマルチプロセッサシステム
US6292705B1 (en) * 1998-09-29 2001-09-18 Conexant Systems, Inc. Method and apparatus for address transfers, system serialization, and centralized cache and transaction control, in a symetric multiprocessor system
TW440793B (en) 1998-02-25 2001-06-16 Koninkl Philips Electronics Nv A method for structuring a multi-instruction computer program from basic blocks that compose from internal instructions and external jumps in an internal directed acyclic graph, and a processor loaded with such program
JP4179677B2 (ja) 1998-09-04 2008-11-12 株式会社ルネサステクノロジ マルチプロセッサ装置
US6625700B2 (en) * 2001-05-31 2003-09-23 Sun Microsystems, Inc. Arbitration and select logic for accessing a shared memory
US6961804B2 (en) * 2001-07-20 2005-11-01 International Business Machines Corporation Flexible techniques for associating cache memories with processors and main memory
US7024506B1 (en) * 2002-12-27 2006-04-04 Cypress Semiconductor Corp. Hierarchically expandable fair arbiter

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