CN100520748C - 数据处理系统 - Google Patents

数据处理系统 Download PDF

Info

Publication number
CN100520748C
CN100520748C CNB2004800252825A CN200480025282A CN100520748C CN 100520748 C CN100520748 C CN 100520748C CN B2004800252825 A CNB2004800252825 A CN B2004800252825A CN 200480025282 A CN200480025282 A CN 200480025282A CN 100520748 C CN100520748 C CN 100520748C
Authority
CN
China
Prior art keywords
data processing
module
node
modules
port
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2004800252825A
Other languages
English (en)
Chinese (zh)
Other versions
CN1902611A (zh
Inventor
彼得·范德沃尔夫
约瑟夫斯·T·J·范埃及恩德霍恩
约翰尼斯·布恩斯特拉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Network System Technology Co ltd
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of CN1902611A publication Critical patent/CN1902611A/zh
Application granted granted Critical
Publication of CN100520748C publication Critical patent/CN100520748C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1663—Access to shared memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)
CNB2004800252825A 2003-09-04 2004-08-19 数据处理系统 Expired - Fee Related CN100520748C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP03103293.1 2003-09-04
EP03103293 2003-09-04

Publications (2)

Publication Number Publication Date
CN1902611A CN1902611A (zh) 2007-01-24
CN100520748C true CN100520748C (zh) 2009-07-29

Family

ID=34306924

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2004800252825A Expired - Fee Related CN100520748C (zh) 2003-09-04 2004-08-19 数据处理系统

Country Status (7)

Country Link
US (1) US7870347B2 (OSRAM)
EP (1) EP1671233B1 (OSRAM)
JP (1) JP4729490B2 (OSRAM)
KR (1) KR101109016B1 (OSRAM)
CN (1) CN100520748C (OSRAM)
AT (1) ATE534080T1 (OSRAM)
WO (1) WO2005026964A2 (OSRAM)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100445977C (zh) 2004-05-18 2008-12-24 皇家飞利浦电子股份有限公司 数据处理系统以及用于处理数据的方法
US7561584B1 (en) * 2005-11-09 2009-07-14 Sun Microsystems, Inc. Implementation of a graph property in a switching fabric for fast networking
CN103186501A (zh) * 2011-12-29 2013-07-03 中兴通讯股份有限公司 一种多处理器共享存储方法及系统
RU2678321C2 (ru) 2013-09-02 2019-01-28 Филипс Лайтинг Холдинг Б.В. Прозрачная вычислительная конструкция
US20160164999A1 (en) * 2014-12-09 2016-06-09 International Business Machines Corporation Hybrid web storage model
CN107368523B (zh) * 2017-06-07 2020-05-12 武汉斗鱼网络科技有限公司 一种数据处理方法及系统
KR102109371B1 (ko) 2018-01-15 2020-05-12 주식회사 경인기계 팬 및 이를 포함하는 냉각탑
WO2020001438A1 (zh) * 2018-06-27 2020-01-02 上海寒武纪信息科技有限公司 片上代码断点调试方法、片上处理器及芯片断点调试系统
JP7060720B2 (ja) * 2018-10-18 2022-04-26 シャンハイ カンブリコン インフォメーション テクノロジー カンパニー リミテッド ネットワークオンチップによるデータ処理方法及び装置
US11250015B2 (en) 2020-02-07 2022-02-15 Coupang Corp. Systems and methods for low-latency aggregated-data provision
CN115311125A (zh) * 2022-07-04 2022-11-08 深圳市国微电子有限公司 图像处理方法、装置及芯片系统

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0294890A2 (en) * 1987-06-09 1988-12-14 Koninklijke Philips Electronics N.V. Data processing system
GB2233480A (en) * 1989-06-22 1991-01-09 Int Computers Ltd Multiprocessor data processing system
US5440698A (en) * 1990-11-30 1995-08-08 Xerox Corporation Arbitration of packet switched busses, including busses for shared memory multiprocessors
US6292705B1 (en) * 1998-09-29 2001-09-18 Conexant Systems, Inc. Method and apparatus for address transfers, system serialization, and centralized cache and transaction control, in a symetric multiprocessor system

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63236159A (ja) * 1987-03-25 1988-10-03 Hitachi Ltd 並列プロセツサのメモリアクセス方式
US5261067A (en) * 1990-04-17 1993-11-09 North American Philips Corp. Method and apparatus for providing synchronized data cache operation for processors in a parallel processing system
US5469542A (en) * 1991-07-22 1995-11-21 International Business Machines Corporation Serial diagnostic interface bus for multiprocessor systems
JP2819982B2 (ja) * 1993-03-18 1998-11-05 株式会社日立製作所 範囲指定可能なキャッシュ一致保証機能を有するマルチプロセッサシステム
TW440793B (en) 1998-02-25 2001-06-16 Koninkl Philips Electronics Nv A method for structuring a multi-instruction computer program from basic blocks that compose from internal instructions and external jumps in an internal directed acyclic graph, and a processor loaded with such program
JP4179677B2 (ja) 1998-09-04 2008-11-12 株式会社ルネサステクノロジ マルチプロセッサ装置
US6625700B2 (en) * 2001-05-31 2003-09-23 Sun Microsystems, Inc. Arbitration and select logic for accessing a shared memory
US6961804B2 (en) * 2001-07-20 2005-11-01 International Business Machines Corporation Flexible techniques for associating cache memories with processors and main memory
US7024506B1 (en) * 2002-12-27 2006-04-04 Cypress Semiconductor Corp. Hierarchically expandable fair arbiter

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0294890A2 (en) * 1987-06-09 1988-12-14 Koninklijke Philips Electronics N.V. Data processing system
GB2233480A (en) * 1989-06-22 1991-01-09 Int Computers Ltd Multiprocessor data processing system
US5440698A (en) * 1990-11-30 1995-08-08 Xerox Corporation Arbitration of packet switched busses, including busses for shared memory multiprocessors
US6292705B1 (en) * 1998-09-29 2001-09-18 Conexant Systems, Inc. Method and apparatus for address transfers, system serialization, and centralized cache and transaction control, in a symetric multiprocessor system

Also Published As

Publication number Publication date
KR20060080186A (ko) 2006-07-07
JP2007504549A (ja) 2007-03-01
ATE534080T1 (de) 2011-12-15
JP4729490B2 (ja) 2011-07-20
WO2005026964A2 (en) 2005-03-24
KR101109016B1 (ko) 2012-01-31
WO2005026964A3 (en) 2006-08-31
CN1902611A (zh) 2007-01-24
EP1671233A2 (en) 2006-06-21
EP1671233B1 (en) 2011-11-16
US7870347B2 (en) 2011-01-11
US20070028038A1 (en) 2007-02-01

Similar Documents

Publication Publication Date Title
US8214845B2 (en) Context switching in a network on chip by thread saving and restoring pointers to memory arrays containing valid message data
US7627738B2 (en) Request and combined response broadcasting to processors coupled to other processors within node and coupled to respective processors in another node
US10210117B2 (en) Computing architecture with peripherals
CN100478939C (zh) 数据处理的系统和方法
CN104699631A (zh) Gpdsp中多层次协同与共享的存储装置和访存方法
JPH11282820A (ja) スイッチをベースとするマルチプロセッサシステムに使用するための順序サポート機構
CN100520748C (zh) 数据处理系统
US7406568B2 (en) Buffer allocation for split data messages
US9542317B2 (en) System and a method for data processing with management of a cache consistency in a network of processors with cache memories
JPH0810447B2 (ja) メモリ共有マルチプロセッサが使用する全ての物理的アドレスのデータ両立性を保持する方法
CN118012788A (zh) 数据处理器、数据处理方法、电子设备和存储介质
US20050041655A1 (en) Method and apparatus for routing packets that have ordering requirements
US10601723B2 (en) Bandwidth matched scheduler
US10999401B2 (en) Multiple on-die communication networks
CN102065073B (zh) 向协议层直接提供数据消息
US7221678B1 (en) Method and apparatus for routing packets
US7274692B1 (en) Method and apparatus for routing packets that have multiple destinations
CN115643205B (zh) 数据生产和消费主体的通信控制单元、及相关装置和方法
CN120929222A (zh) 数据访问方法、缓存装置、芯片产品及计算机设备

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CP03 Change of name, title or address

Address after: 52 high-tech park, 5656AG, Edelhofen, Netherlands

Patentee after: KONINKLIJKE PHILIPS N.V.

Address before: Holland Ian Deho Finn

Patentee before: KONINKLIJKE PHILIPS ELECTRONICS N.V.

CP03 Change of name, title or address
TR01 Transfer of patent right

Effective date of registration: 20230530

Address after: Maine

Patentee after: Network System Technology Co.,Ltd.

Address before: 52 high-tech park, 5656AG, Edelhofen, Netherlands

Patentee before: KONINKLIJKE PHILIPS N.V.

TR01 Transfer of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090729

CF01 Termination of patent right due to non-payment of annual fee