GB8914352D0 - Multiprocessor data processing system - Google Patents

Multiprocessor data processing system

Info

Publication number
GB8914352D0
GB8914352D0 GB898914352A GB8914352A GB8914352D0 GB 8914352 D0 GB8914352 D0 GB 8914352D0 GB 898914352 A GB898914352 A GB 898914352A GB 8914352 A GB8914352 A GB 8914352A GB 8914352 D0 GB8914352 D0 GB 8914352D0
Authority
GB
United Kingdom
Prior art keywords
data processing
processing system
multiprocessor data
multiprocessor
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
GB898914352A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Services Ltd
Original Assignee
Fujitsu Services Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Services Ltd filed Critical Fujitsu Services Ltd
Priority to GB898914352A priority Critical patent/GB8914352D0/en
Publication of GB8914352D0 publication Critical patent/GB8914352D0/en
Priority to GB9006508A priority patent/GB2233480B/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0692—Multiconfiguration, e.g. local and global addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
GB898914352A 1989-06-22 1989-06-22 Multiprocessor data processing system Pending GB8914352D0 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
GB898914352A GB8914352D0 (en) 1989-06-22 1989-06-22 Multiprocessor data processing system
GB9006508A GB2233480B (en) 1989-06-22 1990-03-23 Multiprocessor data processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB898914352A GB8914352D0 (en) 1989-06-22 1989-06-22 Multiprocessor data processing system

Publications (1)

Publication Number Publication Date
GB8914352D0 true GB8914352D0 (en) 1989-08-09

Family

ID=10658879

Family Applications (2)

Application Number Title Priority Date Filing Date
GB898914352A Pending GB8914352D0 (en) 1989-06-22 1989-06-22 Multiprocessor data processing system
GB9006508A Expired - Fee Related GB2233480B (en) 1989-06-22 1990-03-23 Multiprocessor data processing system

Family Applications After (1)

Application Number Title Priority Date Filing Date
GB9006508A Expired - Fee Related GB2233480B (en) 1989-06-22 1990-03-23 Multiprocessor data processing system

Country Status (1)

Country Link
GB (2) GB8914352D0 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5410654A (en) * 1991-07-22 1995-04-25 International Business Machines Corporation Interface with address decoder for selectively generating first and second address and control signals respectively in response to received address and control signals
US5485594A (en) * 1992-07-17 1996-01-16 International Business Machines Corporation Apparatus and method using an atomic fetch and add for establishing temporary ownership of a common system resource in a multiprocessor data processing system
GB9727452D0 (en) 1997-12-31 1998-02-25 Northern Telecom Ltd Method and apparatus for replicating operations on data
CN100520748C (en) * 2003-09-04 2009-07-29 皇家飞利浦电子股份有限公司 Data processing system
JP4376040B2 (en) 2003-11-27 2009-12-02 株式会社日立製作所 Apparatus and method for performing information processing using a plurality of processors

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1223142B (en) * 1987-11-17 1990-09-12 Honeywell Bull Spa MULTIPROCESSOR PROCESSING SYSTEM WITH MULTIPLATION OF GLOBAL DATA

Also Published As

Publication number Publication date
GB2233480A (en) 1991-01-09
GB2233480B (en) 1993-03-17
GB9006508D0 (en) 1990-05-23

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