JP2007329698A - Pulse width modulating circuit, and switching amplifier using same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pulse width modulating circuit of novel constitution whose carrier frequency is made nearly constant. <P>SOLUTION: The pulse width modulating circuit 1 charges a first integrating capacitor C1 with a current based upon an audio signal e<SB>S</SB>in a first period T1 (wherein SWs 2 and 3 are ON, and SWs 1 and 4 are OFF), and varies the charging voltage accumulated in the C1 with a constant bias current Ib in a second period (wherein the SWs 2 and 3 are OFF and the SWs 1 and 4 are ON). Further, the pulse width modulating circuit charges a second integrating capacitor C2 with the current based upon e<SB>S</SB>in the T2 and varies the charging voltage accumulated in the C2 with the Ib in a third period T3 (wherein the SWs 2 and 3 are ON and the SWs 1 and 4 are OFF). The time from when the T2 starts until when the voltage across the C1 reaches Vref is detected. The time from when the T3 starts until when the voltage across the C2 reaches Vref is detected. Based upon those times, a pulse signal having a pulse width of the times is generated. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a pulse width modulation circuit that outputs, for example, a pulse width modulation (PWM) of an audio signal and a switching amplifier (for example, an audio amplifier) using the same.

  2. Description of the Related Art Conventionally, switching amplifiers have been proposed in which a pulse width modulation circuit that uses, for example, pulse width modulation of an audio signal as an input signal and outputs the modulation signal is used. In this switching amplifier, a predetermined power supply voltage is switched based on the modulation signal output from the pulse width modulation circuit, and the switched output signal is output to a load (for example, a speaker) through, for example, a low-pass filter.

FIG. 21 is a configuration diagram illustrating an example of a conventional switching amplifier. This switching amplifier includes a pulse width modulation circuit 51 (for example, refer to Patent Document 1) connected to an audio signal generation source AU, a switching circuit 52, and a low-pass filter circuit 53. According to this switching amplifier, the amplitude of the audio signal e _S output from the audio signal generation source AU is subjected to pulse width modulation in the pulse width modulation circuit 51, and the modulated modulation signals OUT 1 and OUT 2 are output to the switching circuit 52. Is done. In the switching circuit 52, the positive and negative power supply voltages + V _D and −V _D are alternately switched based on the modulation signals OUT1 and OUT2, and the high-frequency component is removed from the switched output by the low-pass filter circuit 53, and the output signal V _0. As shown in FIG.

JP 2004-320097 A

  FIG. 22 is a circuit diagram showing an internal configuration of pulse width modulation circuit 51 shown in FIG.

  The pulse width modulation circuit 51 is an integration type pulse width modulation circuit using an unstable multivibrator. For example, an audio signal as an input signal is subjected to pulse width modulation (PWM) to generate and output two modulation signals OUT1 and OUT2. To do. The two modulation signals OUT1 and OUT2 change so that their levels are alternately different. For example, when the modulation signal OUT1 is at a high level, the modulation signal OUT2 is at a low level.

As shown in FIG. 22, the pulse width modulation circuit 51 includes a bias current source 54, a modulation circuit 55 connected to the bias current source 54, and a pulse generation circuit 56 connected to the modulation circuit 55. . When a predetermined power supply voltage V _A is supplied to the bias current source 54, the bias current 2Ib flowing through the bias current source 54 flows to the modulation circuit 55 via the input terminal 55a.

The modulation circuit 55 is configured by a so-called differential amplifier circuit, and includes resistors R51 and R52 having one ends connected to the input end 55a and transistors Q51 and Q52 connected to the other ends. The modulation circuit 55 includes currents of first and second currents I1 and I2 that flow through the transistors Q51 and Q52, respectively, in accordance with an audio signal e _S (= e1−e2) indicated by a voltage difference between the two input terminals e1 and e2. The distribution ratio is changed. That is, the audio signals e1 and e2 are converted into the first and second currents I1 and I2 by the transistors Q51 and Q52, respectively.

Here, when the conversion conductance of the bias current Ib with respect to the audio signal e _S is G ₀ , the conversion conductance G ₀ is represented by G ₀ = 1 / (R51 + R52), and the first current I1 is I1 = Ib−G _0. in · e _S, the second current I2 can be represented respectively by _{I2 = Ib + G 0 · e} S.

  The pulse generation circuit 56 generates a pulse signal that is a modulated signal (carrier) of the pulse width modulation signal, and includes charging capacitors C51 and C52, first to fourth inverter circuits INV51 to INV54, and first and It consists of second diodes D51 and D52. Based on the first and second currents I1 and I2 supplied from the modulation circuit 55, the pulse generation circuit 56 accumulates charges in the charging capacitors C51 and C52 and charges the charging capacitors C51 and C52. Modulation signals OUT1 and OUT2 having a time width corresponding to.

A predetermined power supply voltage V _B is supplied to each cathode side of the first and second diodes D51 and D52, and the first to fourth inverter circuits INV51 to INV54 have predetermined power supply voltages V _B and V _C. (For example, V _C = V _B −5V) is supplied (in FIG. 22, only a part of the power supply form to each of the inverter circuits INV51 to INV54 is described).

  Here, the capacitances of the charging capacitors C51 and C52 are the same (= C), and the first and second currents I1 and I2 respectively charge the charging capacitors C51 and C52 with a predetermined threshold voltage Vth (first to fourth inverter circuits). Assuming that the time for charging up to INV51 to INV54 (the voltage that determines the high level or low level) is T1 and T2, the relations I1 · T1 = C · Vth and I2 · T2 = C · Vth are established. Accordingly, the charging times T1 and T2 are T1 = C · Vth / I1 and T2 = C · Vth / I2, respectively.

  As shown in FIG. 21, the switching circuit 52 includes switches SW-a and SW-b that are alternately turned on and off based on the modulation signals OUT1 and OUT2 output from the pulse generation circuit 56. The switches SW-a and SW-b are turned on during charging times T1 and T2 of the charging capacitors C51 and C52, respectively.

FIG. 23 is a diagram showing the output waveforms of the modulation signals OUT1 and OUT2, and the output waveforms after switching by the switches SW-a and SW-b at the point P in FIG. 21, but at the on time T1 of the switch SW-a. Outputs a positive power supply voltage + V _{D and} outputs a negative power supply voltage −V _D during the on-time T2 of the switch SW2.

Here, the modulation degree m of this switching amplifier can be expressed as modulation degree m = (T1−T2) / (T1 + T2) using charging times T1 and T2 of the charging capacitors C51 and C52. In this equation, the charging time T1 = C · Vth / I1, T2 = C · Vth / I2, the first current I1 = Ib−G ₀ · e _S , and the second current I2 = Ib + G ₀ · e _S are described. When substituted, the modulation degree m can be expressed by m = G ₀ · e _S / Ib. That is, the degree of modulation m was found to be proportional to the audio signal e _S, thereby, it can be seen that the pulse width modulation according to the audio signal e _S is realized.

On the other hand, since one period T obtained by adding the charging times T1 and T2 of the charging capacitors C51 and C52 is T == T1 + T2, T = C · Vth · [(I1 + I2) / (I1 · I2)]. Substituting the first current I1 = Ib−G ₀ · e _S and the second current I2 = Ib + G ₀ · e _S into the _equation , and further considering the degree of modulation m = G ₀ · e _S / Ib, the period T is , T = 2C · Vth / [Ib · (1−m ² )].

This expression period T (= T1 + T2) is dependent on the degree of modulation m, i.e. depending on the amplitude of the audio signal e _S, it can be seen that vary the amplitude of the audio signal e _S. For example, when there is no amplitude of the audio signal e _S (when there is no signal), the modulation factor m = 0, so the period T is minimum. On the other hand, when the amplitude of the audio signal e _S (the absolute value of the audio signal e _S) is increased, the larger the amplitude, that is, as the modulation factor m is if increased, the period T becomes longer in response to this increase.

In this case, the frequency f (hereinafter referred to as “carrier frequency”) of the modulated signal (carrier) of the pulse width modulation signal is represented by f = 1 / (T1 + T2) which is the reciprocal of the period T. f is f = Ib · (1−m ² ) / (2C · Vth). Therefore, when the audio signal e _S is not present (m = 0), the carrier component is sufficiently attenuated by the low-pass filter circuit 53 including the LC circuit including the coil L and the capacitor C.

However, when the amplitude of the audio signal e _S increases, that is, when the modulation degree m increases, the value of the carrier frequency f decreases. When the amplitude of the audio signal e _S increases and the value of the carrier frequency f decreases. For example, when the carrier frequency f approaches the cutoff frequency (for example, 60 kHz) of the low-pass filter circuit 53, a part of the carrier component passes through the low-pass filter circuit 53. This causes a problem that the amount of leakage of the carrier component increases, and this leakage amount is output as noise from a speaker as a load (not shown).

  When the value of the carrier frequency f decreases and approaches the series resonance frequency of the low-pass filter circuit 53, for example, the switches SW-a and SW-b applied to the switching circuit 53 are configured by switching output transistors. In such a case, an excessive current flows through the switching output transistor, which may destroy the switching transistor.

  As described above, in the conventional pulse width modulation circuit 51, the modulated signal (carrier) of the pulse width modulation signal is generated and oscillated inside the pulse width modulation circuit 51. It is impossible to control the modulation signal or synchronize the modulated signal.

  Further, when the conventional pulse width modulation circuit 51 is applied to a multi-channel switching amplifier having a plurality of channels, the carrier frequency f includes the bias current Ib, the capacitances of the first and second capacitors C51 and C52, the first Since it depends on the threshold voltage Vth of the fourth inverter circuits INV51 to INV54, if these values vary, the carrier frequency f slightly differs between channels, and beats between modulated signals (carriers) occur. The components are mixed in the audio frequency, and the beat sound is output as noise. For this reason, there is a problem in that a sound whose volume is slightly changed is output from the load (speaker) to the outside.

  The present invention has been conceived under the circumstances described above, and it is an object of the present invention to provide a pulse modulation circuit having a novel configuration in which the carrier frequency is substantially constant and a switching amplifier to which the pulse modulation circuit is applied. To do.

  In order to solve the above problems, the present invention takes the following technical means.

  The pulse width modulation circuit provided by the first aspect of the present invention charges the first integration circuit based on a current based on an input signal in a first period which is a half cycle of a predetermined clock signal, and In the second period following the first period, which is shifted by a half cycle from the period, the charging voltage accumulated in the first integration circuit is changed based on a constant bias current, and based on the current based on the input signal. A second integration circuit different from the first integration circuit is charged, and a charging voltage accumulated in the second integration circuit is changed based on the bias current in a third period of a half cycle following the second period. An integration control circuit; a first detection circuit that detects a time from when the second period starts until the voltage in the first integration circuit reaches a predetermined reference voltage; and the third period starts. And a second detection circuit that detects a time until the voltage in the second integration circuit reaches a predetermined reference voltage, and alternates every half cycle of the clock signal from the first detection circuit and the second detection circuit. And a pulse signal generation circuit that generates a pulse signal having a pulse width corresponding to the time based on the time repeatedly output to (1).

  According to this configuration, in the first period that is a half cycle of the clock signal, the first integration circuit (for example, the first integration capacitor) is charged based on the current based on the input signal (for example, the audio signal). In the subsequent second period, the charging voltage accumulated in the first integrating circuit is changed (for example, discharged or further charged) based on a constant bias current. On the other hand, in the second period, the second integration circuit (for example, the first integration capacitor) is charged based on the current based on the input signal. In the subsequent third period, the charging voltage accumulated in the second integrating circuit is changed (for example, discharged or further charged) based on a constant bias current.

  In the second period, the time from the start of the second period until the voltage in the first integration circuit reaches a predetermined reference voltage is detected. In the third period, the third period is started. Until the voltage in the second integration circuit reaches a predetermined reference voltage. These detected times are alternately output every half cycle of the clock signal, and a pulse signal having a pulse width of the time is generated based on these times.

  The time from the start of the second period until the voltage in the first integration circuit reaches the predetermined reference voltage is equal to the amount of charge charged in the first integration circuit based on the current based on the input signal in the first period. Depends on the amount of charge. In addition, the time from the start of the third period until the voltage in the second integration circuit reaches the predetermined reference voltage is the charge charged in the first integration circuit based on the current based on the input signal in the first period. It depends on the amount and varies depending on the amount of charge. Therefore, a pulse width corresponding to the input signal can be generated, and a predetermined clock signal having a substantially constant period is used, so that pulse width modulation with a substantially constant carrier frequency can be performed.

  In the pulse width modulation circuit of the present invention, the integration control circuit includes: a first discharge circuit that discharges with a constant discharge amount based on the constant bias current in the second period; and the constant bias in the third period. And a second discharge circuit that discharges with a constant discharge amount based on the current.

  In the pulse width modulation circuit of the present invention, the integration control circuit includes a voltage-current conversion circuit that converts a voltage based on the input signal into a current, a bias current generation circuit that generates the constant bias current, and the voltage-current conversion. An addition circuit for adding the current converted by the circuit and the constant bias current generated by the bias current generation circuit, a state of supplying the output of the addition circuit to the first integration circuit, and an output of the addition circuit It is preferable to further include a switching circuit that switches a state of supplying the second integration circuit to the second integration circuit based on the clock signal.

  In the pulse width modulation circuit of the present invention, the integration control circuit includes a first charging circuit that charges the first integration circuit at a constant rate based on the constant bias current in the second period, and the third period. And a second charging circuit that charges the second integration circuit at a constant rate based on the constant bias current.

  In the pulse width modulation circuit according to the present invention, the integration control circuit includes a first bias generation circuit that generates the constant bias current and a second bias generation circuit that generates another constant bias current different from the bias current. A voltage-current conversion circuit that converts a voltage based on the input signal into a current; and a current converted by the voltage-current conversion circuit is added to a bias current generated by a first bias generation circuit, and the first integration circuit Based on the clock signal, and a state in which the current converted by the voltage-current conversion circuit is added to the bias current generated by the second bias generation circuit and is supplied to the second integration circuit. And a switching circuit for switching between them.

  In the pulse width modulation circuit of the present invention, the first detection circuit includes a first comparison circuit that compares a charge voltage accumulated in the first integration circuit in the second period with a predetermined reference voltage, The second detection circuit includes a second comparison circuit that compares the charging voltage accumulated in the second integration circuit in the third period with a predetermined reference voltage, and the pulse width signal generation circuit includes the first width detection circuit. The pulse signal may be generated based on the output of the comparison circuit and the output of the second comparison circuit.

  In the pulse width modulation circuit of the present invention, a first forced discharge circuit for forcibly discharging a charging voltage accumulated in the first integration circuit based on an output of the first comparison circuit, and an output of the second comparison circuit And a second forced discharge circuit that forcibly discharges the charging voltage accumulated in the second integration circuit based on the above (Claim 7).

  The pulse width modulation circuit of the present invention may include a clock generation circuit for generating the clock signal.

  The pulse width modulation circuit of the present invention may further comprise a dead time generation circuit for generating a dead time for suppressing a delay time at the time of inversion of the clock signal generated from the clock generation circuit. .

  The switching amplifier provided by the second aspect of the present invention includes a pulse width modulation circuit provided by the first aspect of the present invention, a voltage source that outputs a predetermined power supply voltage, and an output from the pulse width modulation circuit. And a switching circuit for switching a predetermined power supply voltage supplied from the voltage source based on the modulated signal.

  According to this configuration, since this switching amplifier includes the pulse width modulation circuit provided by the first aspect of the present invention, the same effect as the pulse width modulation circuit provided by the first aspect can be obtained. Play.

  Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

  Hereinafter, preferred embodiments of the present invention will be specifically described with reference to the accompanying drawings.

<First Embodiment>
FIG. 1 is a configuration diagram showing a switching amplifier to which a pulse width modulation (PWM) circuit according to a first embodiment of the present invention is applied. FIG. 2 is a block circuit diagram showing an embodiment of the pulse width modulation circuit shown in FIG. The switching amplifier includes a pulse width modulation circuit 1 connected to an audio signal generation source AU, a switching circuit 2, a low-pass filter circuit 3, positive and negative power supply voltage + E _B, the first power supply 4 and supplies -E _B A second power source 5 is provided. A speaker (not shown) as a load RL is connected to the output of the low-pass filter circuit 3.

The pulse width modulation circuit 1 generates and outputs a modulation signal PWM-OUT by pulse width modulating the audio signal e _S as an input signal output from the audio signal generation source AU. The modulation signal PWM-OUT output from the pulse width modulation circuit 1 is input to the switching circuit 2.

In the switching circuit 2, positive and negative power supply voltages + E _B and −E _B supplied from the first power supply 4 and the second power supply 5 are alternately switched based on the modulated modulation signal PWM-OUT. That is, the switching circuit 2 includes an inverter 2a that inverts the phase of the modulation signal PWM-OUT output from the pulse width modulation circuit 1, a switch element SW-A that operates on and off based on the modulation signal PWM-OUT, Based on the modulation signal PWM-OUT ′ obtained by inverting the modulation signal PWM-OUT by the inverter 2a, the switch element SW-B that is turned on and off is connected to both ends of both switch elements SW-A and SW-B. Reverse-current preventing diodes DA and DB are provided.

The switch elements SW-A and SW-B are alternately turned on and off by the modulation signal PWM-OUT and the inverted modulation signal PWM-OUT ′, and are switched with respect to the low-pass filter circuit 3 and the load RL. positive and negative power supply voltage + E _B, supplies -E _B.

The low-pass filter circuit 3 is configured by an LC circuit including a coil L ₀ and a capacitor C ₀ and is a circuit that removes a high-frequency component of an output signal output from the switching circuit 2 and supplies the output signal to the load RL. Has a frequency. In the low-pass filter circuit 3, the high-frequency components of the switched positive and negative power supply voltages + E _B and −E _B are removed, and the output is supplied to the load RL and is output from the load RL as sound.

  As shown in FIG. 2, the pulse width modulation circuit 1 includes an audio signal conversion circuit 11, a charging bias current source 12, a current adding circuit 13, a switch circuit 14, a clock generation circuit 15, and a discharging bias current. A source 16, first and second integration circuits 17 and 18, first and second comparison circuits 19 and 20, first and second reset circuits 21 and 22, and a signal output circuit 23 are configured. .

The audio signal conversion circuit 11 is a circuit for voltage-current conversion of the audio signal e _S supplied from the audio signal generation source AU (see FIG. 1) to the pulse width modulation circuit 1. Here, when the conversion conductance in the audio signal conversion circuit 11 is G, the current flowing into the downstream current addition circuit 13 can be expressed as G · e _S.

The charging bias current source 12 is a circuit that converts a predetermined positive power supply voltage + Va into a bias current Ib and supplies the bias current Ib to the downstream current adding circuit 13. The current adding circuit 13 adds the current (G · e _S ) converted by the audio signal conversion circuit 11 and the bias current Ib converted by the charging bias current source 12 (G · e _S + Ib). Is supplied to the downstream switch circuit 14.

The switch circuit 14 includes first to fourth switches SW <b> 1 to SW <b> 4, and a first current to a second current output from the clock generation circuit 15 is output from the sum current (G · e _S + Ib) added by the current addition circuit 13. This circuit is switched by two clock signals φ1 and φ2 (described later) and is supplied to first and second integrating circuits 17 and 18 in the subsequent stage.

  The connection configuration will be described. One end of each of the first and second switches SW1, SW2 is connected to the current adding circuit 13, and the other end of the first switch SW1 (see point A in FIG. 2) is connected to the first integrating circuit. 17, thereby forming a charging path for the first integrating circuit 17. The other end of the first switch SW 1 is also connected to one end of the third switch SW 3, and the other end of the third switch SW 3 is connected to the discharge bias current source 16. A discharge path is formed. On the other hand, the other end of the second switch SW2 (see the point B in FIG. 2) is connected to the second integration circuit 18, thereby forming a charging path for the second integration circuit 18. The other end of the second switch SW2 is also connected to one end of the fourth switch SW4, and the other end of the fourth switch SW4 is connected to the discharge bias current source 16, whereby the second integrating circuit 18 A discharge path is formed.

  The clock generation circuit 15 supplies switching signals (clock signals) for switching the first to fourth switches SW1 to SW4 of the switch circuit 14 to the first to fourth switches SW1 to SW4, respectively, as shown in FIG. The first clock signal φ1 having a duty ratio of approximately 50% and the second clock signal φ2 having the opposite phase to the first clock signal φ1 are output. The clock generation circuit 15 may be provided outside the pulse width modulation circuit 1 and may be configured to supply the first clock signal φ1 and the second clock signal φ2 to the pulse width modulation circuit 1 as external clock signals. .

  The second and third switches SW2 and SW3 of the switch circuit 14 are both turned on and off by the first clock signal φ1, and the first and fourth switches SW1 and SW4 are both turned on and off by the second clock signal φ2. Is done. Therefore, the second and third switches SW2 and SW3 and the first and fourth switches SW1 and SW4 are alternately turned on and off.

For example, as shown in FIG. 3, when the first clock signal φ1 is at a high level and the second clock signal φ2 is at a low level (hereinafter referred to as “first period T1”), the second and third switches SW2, SW3 Is turned on, and the first and fourth switches SW1 and SW4 are turned off (see the state of the switch circuit 4 in FIG. 2). In this case, the sum current (G · e _S + Ib) from the current addition circuit 13 flows to the second integration circuit 18 via the second switch SW2, thereby charging the second integration circuit 18.

On the other hand, when the first clock signal φ1 is at a low level and the second clock signal φ2 is at a high level (hereinafter referred to as “second period T2”), the first and fourth switches SW1 and SW4 are turned on, The third switches SW2 and SW3 are turned off. In this case, the sum current (G · e _S + Ib) flows to the first integration circuit 17 via the first switch SW1, thereby charging the first integration circuit 17.

The first and second integrating circuits 17 and 18 are constituted by a first integrating capacitor C1 and a second integrating capacitor C2, respectively. As described above, in the first integration capacitor C1, the first switch SW1 is turned on and the third switch SW3 is turned off in the second period T2, whereby the sum current (G • Charged by e _S + Ib). The first integrating capacitor C1 is charged when the first switch SW1 is turned off and the third switch SW3 is turned on during the next half-cycle period (hereinafter referred to as “third period T3”). The discharged electric charge flows into the discharge bias current source 16 to discharge with a constant discharge amount.

  On the other hand, in the second integration capacitor C2, the sum current flowing from the current addition circuit 13 is turned on when the second switch SW2 is turned on and the fourth switch SW4 is turned off in the first period T1 (see FIG. 3). Is charged by. In the second integration capacitor C2, in the next second period T2, the second switch SW2 is turned off and the fourth switch SW4 is turned on, so that the charged charge flows to the discharge bias current source 16. As a result, the battery is discharged at a constant discharge amount. That is, the first and second integrating capacitors C1 and C2 are alternately charged and discharged every unit period (for example, the first period T1) in which the levels of the first and second clock signals φ1 and φ2 are maintained. Is called.

  The discharging bias current source 16 is connected to the negative power supply voltage −Va, and has the same magnitude as the bias current Ib flowing in the charging bias current source 12 when the first or second integrating capacitor C1 or C2 is discharged. This is for flowing the bias current Ib.

  The first and second comparison circuits 19 and 20 compare the voltage accumulated in the first and second integration circuits 17 and 18 with a predetermined reference voltage Vref, so that the pulse width modulation signal PWM− is output at the output. It is a circuit for defining the pulse width of OUT. The first and second comparison circuits 19 and 20 are circuits for forcibly resetting the first and second integration circuits 17 and 18 when the first and second integration circuits 17 and 18 are discharged. In the case where the first and second comparison circuits 19 and 20 are constituted by, for example, CMOS inverter elements, the reference voltage Vref corresponds to a threshold value defined by the CMOS inverter element high level and low level. Is set to about ½ of the power supply voltage of the CMOS inverter element. For example, if the power supply voltage of the CMOS inverter element is about 5V, the reference voltage Vref is about 2.5V, which is half of that.

  The reference voltage Vref is input to the positive (+) side input terminals of the first and second comparison circuits 19 and 20, respectively, and the first and second integration capacitors C1 and C2 are input to the negative (−) side input terminals. One end of each is connected. The first and second comparison circuits 19 and 20 can be configured by, for example, CMOS inverter elements (not shown). When the first and second comparison circuits 19 and 20 are configured by CMOS inverter elements, the high and low levels of the CMOS inverter elements are set. A prescribed threshold value is set as the reference voltage Vref.

  The outputs of the first and second comparison circuits 19 and 20 (see the points C and D in FIG. 2) are normally at a high level, and the voltages (first and second integration capacitors C1 and C2) at the negative input terminals. When the charging voltage is higher than the reference voltage Vref, a low level signal is output from the output terminal.

  The first and second reset circuits 21 and 22 forcibly end the discharge in the first and second integration capacitors C1 and C2 during the period in which the first and second integration circuits 17 and 18 are discharged, respectively. This is a circuit for resetting. The first reset circuit 21 includes a first AND circuit A1 and a fifth switch SW5, and the second reset circuit 22 includes a second AND circuit A2 and a sixth switch SW6.

  The first AND circuit A1 has one input terminal connected to the output terminal of the first comparison circuit 19, the other input terminal connected to the clock generation circuit 15, and the first clock signal φ1. The output terminal of the first AND circuit A1 (see point E in FIG. 2) is connected to the fifth switch SW5, and the output of the first AND circuit A1 controls the on / off operation of the fifth switch SW5.

  On the other hand, one input terminal of the second AND circuit A2 is connected to the output terminal of the second comparison circuit 20, the other input terminal is connected to the clock generation circuit 15, and the second clock signal φ2 is input thereto. The output terminal of the second AND circuit A2 (see point F in FIG. 2) is connected to the sixth switch SW6, and the output of the second AND circuit A2 controls the on / off operation of the sixth switch SW6.

  FIG. 4 is a diagram showing a voltage waveform at one end of the first integrating capacitor C1 (see point A in FIG. 2) when the second clock signal φ2 changes.

At point A in FIG. 2, when the second clock signal φ2 is at a high level (see the second period T2), the first switch SW1 is turned on and the third switch element SW3 is turned off. The capacitor C1 is charged. The slope of the voltage waveform during charging (the voltage at point A in FIG. 2) depends on the magnitude of the sum current (G · e _S + Ib), that is, the positive / negative state of the audio signal e _S and the magnitude of the amplitude. To do.

Here, the voltage waveform of the symbol W0 in FIG. 4 indicates a waveform when the audio signal e _S is no signal, and the voltage waveform of the symbol W1 indicates that the audio signal e _S is positive (0 <(G · e _S ) < (Ib / 2)) in which the amplitude is relatively large (that is, when the modulation factor m is relatively high), and the voltage waveform of the sign W2 indicates that the audio signal e _S is negative (0> (G The waveform is shown when e _S )> (− Ib / 2)) and the amplitude is relatively large.

According to the figure, the voltage waveform W1 when the audio signal e _S is positive and the amplitude thereof is relatively large has a steeper slope than the voltage waveform W0 when the audio signal e _S is no signal. The voltage waveform W2 when the audio signal e _S is negative and its amplitude is relatively large has a gentler slope than the voltage waveform W0 when the audio signal e _S is no signal.

  Charging in the first integrating capacitor C1 is continued until the level of the second clock signal φ2 is inverted, and when the second clock signal φ2 is inverted and becomes a low level (see the third period T3), the first switch SW1 is turned on. Since the third switch SW3 is turned on as well as being turned off, the first integrating capacitor C1 is discharged.

Therefore, the charging in the first integrating capacitor C1 becomes maximum when the level of the second clock signal φ2 is inverted. As shown in FIG. 4, for example, when the audio signal e _S is no signal, the maximum charging voltage is Vm0. It becomes. When the audio signal e _S is positive and the amplitude is relatively large, the maximum charging voltage is Vm1 (> Vm0). When the audio signal e _S is negative and the amplitude is relatively large, the maximum charging voltage is Vm2 (<Vm0). The circuit constant is set so that the maximum charging voltage Vm0 when the audio signal e _S is no signal is approximately twice the value of the reference voltage Vref.

On the other hand, the voltage waveform at the time of discharge of the first integration capacitor C1 and a third period T3, since the bias current Ib flowing to the discharging bias current source 16 is constant at all times, of the positive and negative audio signal e _S state and The slope is constant regardless of the magnitude of the amplitude. That is, as shown in FIG. 4, the slope of the voltage waveform when the first integrating capacitor C1 is discharged is independent of the slope of the voltage waveform when the first integrating capacitor C1 is charged (second period T2). , Become constant.

  In the third period T3, the discharge of the first integration capacitor C1 is continued with a constant voltage waveform slope, and the voltage at the point A of the first integration capacitor C1 is the reference voltage Vref of the first comparison circuit 19. If the value is less than, the fifth switch SW5 of the first reset circuit 21 is turned on. That is, the first comparison circuit 19 outputs a high level when the voltage at one end of the first integrating capacitor C1 (see point A in FIG. 2) is lower than the reference voltage Vref. Therefore, the first AND circuit A1 outputs a reset signal to the fifth switch SW5 when the first clock signal φ1 is at a high level and the output of the first comparison circuit 19 is at a high level in the third period T3. At this timing, the fifth switch SW5 is turned on.

When the fifth switch SW5 is turned on, the voltage at one end of the first integration capacitor C1 is instantaneously supplied to the ground potential, and the electric charge accumulated in the first integration capacitor C1 is forcibly discharged, and the first integration The voltage is reset so that the voltage at the capacitor C1 becomes zero (see t _{R in} FIG. 4). The reset timing depends on the positive / negative state of the audio signal e _S and the magnitude of the amplitude.

That is, the first integrating capacitor C1 is charged in the second period T2, but the charge amount in this charging depends on the positive and negative states of the audio signal e _S and the magnitude of the amplitude. In the third period T3, the first integration capacitor C1 is discharged. In this case, since the discharge amount is constant, the discharge of the first integration capacitor C1 is started (the third period T3). The time t until the voltage of the first integration capacitor C1 reaches the reference voltage Vref depends on the positive and negative states of the audio signal e _S and the magnitude of the amplitude.

For example, if the audio signal e _S is positive and the amplitude is relatively large, the voltage in the first integration capacitor C1 becomes the maximum charging voltage Vm1, and in this case, the voltage of the first integration capacitor C1 is the reference voltage. The time until Vref (see t _{1 in} FIG. 4) is longer than that in the case where the audio signal e _S is no signal (see t _{0 in} FIG. 4). Conversely, when the audio signal e _S is negative and the amplitude is relatively large, the voltage at the first integrating capacitor C1 becomes the maximum charging voltage Vm2, and in this case, the voltage of the first integrating capacitor C1 is the reference. The time to reach the voltage Vref (see t _{2 in} FIG. 4) is shorter than that when the audio signal e _S is no signal (see t _{0 in} FIG. 4).

That is, the time t from when the discharge of the first integration capacitor C1 is started until the voltage of the first integration capacitor C1 reaches the reference voltage Vref depends on the positive / negative state of the audio signal e _S and the magnitude of the amplitude. Therefore, if the pulse width of the pulse width modulation signal is generated based on the time t, the pulse width can be generated based on the clock signals φ1 and φ2 having a constant period.

Here, the capacitances of the first and second integration capacitors C1 and C2 are the same (= C), and the period of time for charging the first and second integration capacitors C1 and C2 is T (for example, the first period T1). Equivalent), the maximum charging voltage Vm is represented by Vm = [(Ib + G · e _S ) · T] / C.

If the circuit constant is set so that the reference voltage Vref is Vref = (Ib · T) / 2C, the maximum charging voltage Vm becomes Vm = 2Vref + (G · e _S · T) / C. When deformed, Vm−Vref = Vref + (G · e _S · T) / C.

The period from when the discharge of the first integration capacitor C1 (or the second integration capacitor C2) is started until the voltage of the first integration capacitor C1 (or the second integration capacitor C2) reaches the reference voltage Vref is t. Then, since t = [C · (Vm−Vref)] / Ib, t = (C · Vref) / I _B + (G · e _S · T) / C = T / 2 + (G · e _S T) / C.

Therefore, t / T = 1/2 + (G · e _S · T) / C, and the modulation degree m is expressed by m = 2G · e _S / Ib, and therefore t / T = (1 + m) / 2. Become.

Accordingly, a period from when the discharge of the first integration capacitor C1 (or the second integration capacitor C2) is started until the voltage of the first integration capacitor C1 (or the second integration capacitor C2) reaches the reference voltage Vref. t is proportional to the degree of modulation m and proportional to the amplitude of the audio signal e _S.

The operations of the second integration capacitor C2, the second comparison circuit 20, and the second reset circuit 22 are the same as those of the first integration capacitor C1, the first comparison circuit 19, and the second reset circuit 21 described with reference to FIG. The same operation is performed in a period in which the clock signal is shifted by a half cycle. For example, the second integration capacitor C2 is charged according to the audio signal e _S in the first period T1, the second clock signal φ2 is at the high level in the second period T2, and the output of the second comparison circuit 20 is output. Is at the high level, the second AND circuit A2 outputs a reset signal to the sixth switch SW6 to turn on the sixth switch SW6.

  In the second comparison circuit 20, since the high level is output when the voltage at the second integration capacitor C2 falls below the reference voltage Vref, the sixth switch SW6 is turned on at this timing. When the sixth switch SW6 is turned on, the voltage in the second integration capacitor C2 is instantaneously supplied to the ground potential, and the charge accumulated in the second integration capacitor C2 is forcibly discharged and reset.

  The signal output circuit 23 includes first and second NOR circuits N1, N2 and an OR circuit O1. The first NOR circuit N1 has one input terminal connected to the output terminal of the first comparison circuit 19 (see point C in FIG. 2), and the other input terminal connected to the clock generation circuit 15 to be connected to the second clock signal φ2. Is entered. On the other hand, the second NOR circuit N2 has one input terminal connected to the output terminal of the second comparison circuit 20 (see point D in FIG. 2), and the other input terminal connected to the clock generation circuit 15 to be connected to the first clock. Signal φ1 is input. The output terminal of the second NOR circuit N2 is connected to the other input terminal of the OR circuit O1.

  The output terminal of the first NOR circuit N1 (see point G in FIG. 2) and the output terminal of the second NOR circuit N2 (see point H in FIG. 2) are connected to each input terminal of the OR circuit O1, and the output terminal of the OR circuit O1. Is connected to the subsequent switching circuit 2 (see FIG. 1) as a pulse width modulation signal PWM-OUT.

  The first NOR circuit N1 calculates the negative logical sum of the second clock signal φ2 and the output of the first comparison circuit 19 to start discharging by the first integration capacitor C1, and then the first integration capacitor C1. A high level is output at time t until the voltage of C1 reaches the reference voltage Vref. The second NOR circuit N2 calculates the negative logical sum of the first clock signal φ1 and the output of the second comparison circuit 20, thereby starting the discharge by the second integration capacitor C2, and then the second integration capacitor A high level is output at time t until the voltage of C2 reaches the reference voltage Vref.

  The OR circuit O1 calculates the logical sum of the outputs of the first and second NOR circuits N1 and N2, and sets the outputs of the first and second NOR circuits N1 and N2 as one pulse width modulation signal PWM-OUT. 2 is output.

5 to 7 are diagrams showing timing charts of respective signals in the pulse width modulation circuit 1. FIG. FIG. 5 shows a case where the audio signal e _S is no signal (G · e _S = 0), and FIG. 6 shows a case where the audio signal e _S is positive (0 <G · e _S <Ib / 2). FIG. 7 shows a case where the audio signal e _S is negative (0> G · e _S > −Ib / 2).

In the first period T1 in FIG. 5, the first clock signal φ1 from the clock generation circuit 15 is at a high level (the second clock signal φ2 is at a low level), and thereby the second switch SW2 is turned on (fourth switch element). SW4 is turned off. Therefore, the second integration capacitor C2 of the second integration circuit 18 is supplied with the sum current (G · e _S + Ib) from the current addition circuit 13, and the second integration capacitor C2 is charged (point B waveform). reference).

  In the first period T1, the voltage resulting from charging of the second integrating capacitor C2 in the second comparison circuit 20 exceeds the reference voltage Vref, and the output of the second comparison circuit 20 changes from high level to low level (D Since the second clock signal φ2 input to the other terminal maintains the low level even when the low level signal is input to one terminal of the second AND circuit A2, the second AND circuit A2 Does not output a reset signal.

  Further, in the first period T1, the first switch SW1 is turned off and the third switch SW3 is turned on, so that the first integrating capacitor C1 of the first integrating circuit 17 has a half cycle before the first period T1. The charge charged in the period T0 flows to the discharge bias current source 16 and is discharged at a constant discharge amount (see waveform at point A).

  In the first period T1, when the voltage resulting from charging of the first integrating capacitor C1 in the first comparison circuit 19 is lower than the reference voltage Vref, the output of the first comparison circuit 19 changes from low level to high level ( The waveform is input to one input terminal of the first AND circuit A1. Since the high level of the first clock signal φ1 is input to the other input terminal of the first AND circuit A1, the output terminal of the first AND circuit A1 also changes from the low level to the high level (see the waveform at point E). The reset signal is output to the fifth switch SW5.

  As a result, the fifth switch SW5 changes from the OFF state to the ON state, and the electric charge discharged by the first integrating capacitor C1 flows to the ground terminal via the fifth switch SW5, and is discharged forcibly and at once. Is called.

  Since the second clock signal φ2 and the output of the first comparison circuit 19 are inputted to the first NOR circuit N1, the first integration circuit 17 starts discharging in the first period T1 in the first NOR circuit N1. A high level is output at a time t from when to forcibly reset (see point G waveform). The second NOR circuit N2 receives the first clock signal φ1 and the output of the second comparison circuit 20, but the output of the second NOR circuit N2 maintains the low level (refer to the point H waveform). Accordingly, the output of the OR circuit O1 is directly output as the pulse width modulation signal PWM-OUT as the high level as the output of the first NOR circuit N1.

Next, in the period of the second period T2, the first clock signal φ1 from the clock generation circuit 15 changes from the high level to the low level (the second clock signal φ2 changes from the low level to the high level). One switch SW1 is turned on (the third switch element SW3 is turned off). Therefore, the first integration capacitor C1 of the first integration circuit 17 is supplied with the sum current (G · e _S + Ib) from the current addition circuit 13, and the first integration capacitor C1 is charged (point A waveform). reference).

  In the second period, the second switch SW2 is turned off and the fourth switch SW4 is turned on, so that the second integration capacitor C2 of the second integration circuit 18 is charged in the first period T1. Charge flows into the discharge bias current source 16 and is discharged with a constant discharge amount (see waveform at point B).

  Thereafter, when the voltage resulting from charging of the second integration capacitor C2 in the second comparison circuit 20 falls below the reference voltage Vref, the output of the second comparison circuit 20 changes from low level to high level (see waveform at point D). The second AND circuit A2 is input to one input terminal. Since the high level of the second clock signal φ2 is input to the other input terminal of the second AND circuit A2, the output terminal of the second AND circuit A2 also changes from the low level to the high level (see the F point waveform). The reset signal is output to the sixth switch SW6.

  As a result, the sixth switch SW6 changes from the OFF state to the ON state, and the electric charge discharged by the second integrating capacitor C2 flows to the ground terminal via the sixth switch SW6 and is discharged forcibly and at once. Is called.

  Although the second clock signal φ2 and the output of the first comparison circuit 19 are input to the first NOR circuit N1, the output of the first NOR circuit N1 maintains a low level (see waveform at point G). On the other hand, since the first clock signal φ1 and the output of the second comparison circuit 20 are input to the second NOR circuit N2, the second integration circuit 18 starts discharging in the second period T2. Then, a high level is output at time t from when it is forcibly reset (see waveform at point H). Therefore, the output of the OR circuit O1 is directly output as the pulse width modulation signal PWM-OUT as the high level output from the second NOR circuit N2.

  Thereafter, in the third period T3, since the first and second clock signals φ1 and φ2 are inverted, charging is performed in the second integrating capacitor C2, while discharging is performed in the first integrating capacitor C1. Thereafter, each time a half cycle elapses, the first and second clock signals φ1 and φ2 are inverted, and the first and second integrating capacitors C1 and C2 are alternately charged and discharged.

As shown in FIG. 6, when the audio signal e _S is positive, the sum current (G · e _S + Ib) becomes large, and one end (point A or point B) of the first or second integrating capacitors C1 and C2 The slope of the voltage waveform at () also becomes steeper than when the audio signal e _S is no signal. Therefore, the charging voltage Vm at one end of the first or second integrating capacitor C1, C2 at the time when the level of the first or second clock signal φ1, φ2 is inverted becomes relatively large, and when these are discharged, Compared to the case where the audio signal e _S is no signal, the time that is lower than the reference voltage Vref, that is, the time t from when discharge is started until it is forcibly reset becomes longer. Therefore, the pulse width modulation signal PWM-OUT is output at the timing shown in FIG. Thus, the pulse width modulation signal PWM-OUT corresponding to the amplitude of the audio signal e _S is output.

As shown in FIG. 7, when the audio signal e _S is negative, the sum current (G · e _S + Ib) becomes small, and the voltage waveform at one end of the first or second integrating capacitors C1 and C2 is reduced. The inclination is also gentler than when the audio signal e _S is no signal. Therefore, the charging voltage Vm at one end of the first or second integrating capacitor C1, C2 at the time when the level of the first or second clock signal φ1, φ2 is inverted becomes relatively small, and when these are discharged, Compared to the case where the audio signal e _S is not a signal, the time that is lower than the reference voltage Vref, that is, the time t from the start of discharge to the forced reset is shortened. Therefore, the pulse width modulation signal PWM-OUT is output at the timing indicated by the pulse width modulation signal PWM-OUT in FIG.

In the pulse width modulation circuit 51 (see FIG. 22) in the conventional configuration, when the amplitude of the audio signal e _S increases, the carrier frequency f decreases, the leakage of the carrier component of the carrier frequency f increases, and noise is generated from the speaker. However, according to the pulse width modulation circuit 1 having the configuration according to the first embodiment, the first and second clock signals φ1 and φ2 having substantially constant cycles are used. The carrier frequency f can be made substantially constant. Since the first and second clock signals φ1 and φ2 define the charge / discharge time by the first and second integration capacitors C1 and C2, it is possible to suppress an increase in leakage of the carrier component. It is possible to provide a pulse width modulation circuit 1 having a novel configuration.

  Further, since the carrier frequency f is fixed, this does not approach the series resonance frequency of the low-pass filter circuit 53 (see FIG. 21), and an excessive current flows through the switching output transistor applied to the switching circuit 52. There is nothing. Therefore, the fear of destroying this can be eliminated.

  Further, even when the pulse width modulation circuit 1 is applied to a multi-channel switching amplifier having a plurality of channels, the pulse width modulation circuit 1 performs pulse width modulation in synchronization with the first and second clock signals φ1 and φ2. Therefore, the carrier frequency f does not differ slightly between channels, and it is possible to suppress the mixing of beat components between modulated signals (carriers) in the audio frequency.

  According to the above configuration, if the bias current Ib, the reference voltage Vref, and the charge capacities of the first and second integration capacitors C1 and C2 are set appropriately, the first and second clock signals φ1 and φ2 Even if the duty cycle is slightly deviated from the ideal 50%, the influence is canceled during one clock cycle.

  In the pulse width modulation circuit 1, the bias current Ib flowing through the discharge bias current source 16 is the same as the bias current Ib flowing through the charge bias current source 12. It is more preferable that the bias current flowing in can be set individually.

For example, the capacitor voltage Vc of the first integration capacitor C1 when the discharge is started in the first integration capacitor C1 is expressed by Vc = [(Ib + G · e _S ) · T] / C (T is the first (Charging period or discharging period of 1 integrating capacitor C1), ta is the period from the start of discharging of first integrating capacitor C1 to the voltage of first integrating capacitor C1 reaching reference voltage Vref, and discharging bias current When the bias current flowing through the source 16 is Ic, the period ta is represented by ta = [(Vm−Vref) · C] / Ic.

If the period from when the voltage of the first integrating capacitor C1 reaches the reference voltage Vref to when charging is started is represented by tb, the period T is represented by T = ta + tb. m = | ta−tb | / T = 2G · e _S / Ic + 2Ib / Ic− (2C · Vref) / (Ic · T) −1. On the other hand, if the maximum allowable voltage of the capacitor voltage Vc of the first integrating capacitor C1 is Vm, the capacitor voltage Vc is Vc = (Vm + Vref) / 2 in order to make maximum use of the modulation degree m. In addition, a condition of ta = T / 2 is necessary.

More specifically, when the first comparison circuit 19 is composed of a CMOS inverter element, the reference voltage Vref is normally set to ½ of the power supply voltage Vcc (Vref = Vcc / 2). Since the charging to the reference voltage Vref must be performed at least during the charging period of the first integrating capacitor C1, in order to make the maximum use of the modulation degree m, the first signal is used in the absence of the audio signal e _S. The capacitor voltage Vc at the completion of charging of the integrating capacitor C1 needs to be Vc = (Vcc + Vref) / 2 = (3/2) Vref.

  In this case, the charge value of the bias current Ib charged to the value of the capacitor voltage Vc during the charging period T is Ib = [(3/2) Vref · C] / T, and the power supply voltage Vcc was charged during modulation. In this case, the bias current Ic discharged until reaching the value of the reference voltage Vref is Ic = Vref · C / T. Therefore, the relationship between the bias current Ib flowing through the charging bias current source 12 and the bias current Ic flowing through the discharging bias current source 16 is Ib = (3/2) Ic. The bias current Ib flowing through the charging bias current source 12 and the bias current Ic flowing through the discharging bias current source 16 may be set.

Further, if the constants of the respective circuits are set so that the above equation is established, the modulation degree m becomes m = 2G · e _S / Ic, and modulation proportional to the audio signal e _S can be performed. Further, if there is a difference between the charge / discharge bias current values Ib and Ic due to the influence of circuit component errors and the like, an offset may occur in the pulse width modulation signal PWM-OUT, but the charge / discharge bias current values Ib and Ic. By setting each individually, the offset can be canceled.

  Note that 3/2 of Ib = (3/2) Ic can be set to an arbitrary value by changing each value of the power supply voltage Vcc and the reference voltage Vref of the CMOS inverter element. In other words, it is possible to cope with various settings of the power supply voltage Vcc and the reference voltage Vref by individually setting appropriate charge / discharge bias current values Ib and Ic.

  FIG. 8 is a detailed circuit diagram of the pulse width modulation circuit 1 shown in FIG.

  According to the circuit diagram shown in FIG. 8, the audio signal conversion circuit 11, the charging bias current source 12, and the current addition circuit 13 are combined to form a single circuit. The clock generation circuit 15 is configured by a multivibrator including a plurality of inverters, resistors, and capacitors. The switch circuit 14 for switching the charge / discharge current direction is constituted by a general-purpose electronic switch. The first and second comparison circuits 19 and 20 are composed of a plurality of CMOS inverter elements.

  In the figure, diodes D1 to D4 are reverse current prevention diodes for preventing the charging current from being biased by the power supply voltage of the CMOS inverter element. In the figure, resistors R1 to R4 are the power supply voltage (for example, 15V) of the electronic switch as the switch circuit 14, the first and second comparison circuits 19 and 20, the first and second reset circuits 21 and 22, and the signal output circuit. It functions as an attenuator for adjusting the level of 23 power supply voltages (for example, 5 V).

  The logic circuits of the first and second reset circuits 21 and 22 and the signal output circuit 23 are strictly different from the logic circuit having the configuration shown in FIG. 2, but the positive and negative values are adjusted. Therefore, the substantial operation is common. Further, the circuit shown in FIG. 8 is an example, and the pulse width modulation circuit 1 according to the present embodiment is not limited to this.

  FIG. 9 is a diagram showing another modification of the clock generation circuit 15 shown in FIG. The clock generation circuit 24 shown in the figure is composed of a plurality of CMOS inverter elements to which a charging bias current source 12, a discharging bias current source 16 and a switch circuit 14 are added. As described above, the clock generation circuit 24 including the charging bias current source 12, the discharging bias current source 16 and the switch circuit 14 shown in FIG. 9 may be composed of a plurality of CMOS inverter elements. When the circuit shown in FIG. 8 is applied to the pulse width modulation circuit 1 shown in FIG. 8, the entire circuit can be configured using CMOS inverter elements. Note that the circuit 25 in a portion surrounded by a one-dot chain line in FIG. 9 is a level shift circuit for converting a 5V system circuit into a 15V system circuit, for example.

  FIG. 10 is a diagram showing a modification when the audio signal conversion circuit 11, the charging bias current source 12, and the current addition circuit 13 are combined to form a single circuit. FIG. 11 is a diagram showing a modification of the discharge bias current source 16. The first and second reset circuits 21 and 22 may be configured by open drain NAND gates.

  By the way, in the clock generation circuit 15, as shown in FIGS. 5 to 7, the first clock signal φ 1 and the second clock signal φ 2 are converted into, for example, an inverter 15 a (see the final stage of the clock generation circuit 15 in FIG. 8). They are generated by inverting each other. In this case, when the inverter 15a is used, a timing shift occurs due to the propagation delay time TD of the inverter 15a between the first and second clock signals φ1 and φ2.

  FIG. 12 is a timing chart when the propagation delay time TD occurs. According to FIGS. 12A and 12B, when the first clock signal φ1 is inverted from the low level to the high level, the second clock signal φ2 is normally inverted from the high level to the low level at the same timing. Since the first clock signal φ1 to be the second clock signal φ2 passes through the inverter 15a, a propagation delay time TD (see the TD portion in FIG. 12) is generated by the inverter 15a, and in this propagation delay time TD, the first clock signal It may happen that φ1 and the second clock signal φ2 simultaneously become high level.

  When a period TD in which the first and clock signals φ1 and φ2 are simultaneously at a high level occurs, for example, the first and second integration capacitors C1 and C2 are simultaneously charged, and the first and second integration capacitors are used. It becomes impossible for the capacitors C1 and C2 to alternately perform charging and discharging operations at appropriate timing, and an error occurs in the output of the pulse width modulation signal PWM-OUT.

  In such a case, as shown in FIG. 13, a dead time is generated in the subsequent stage of the clock generation circuit 15 so as not to generate the period TD in which the first clock signal φ1 and the second clock signal φ2 are simultaneously at the high level. A dead time generation circuit 26 may be provided.

  Specifically, the dead time generation circuit 26 is configured with an appropriate logic gate, and as shown in FIG. 13, a NOT circuit NT1, an EX-OR (exclusive OR) circuit EX1, and first and second NORs. It consists of circuits NR1 and NR2. The connection configuration will be described. The NOT circuit NT1 is connected to the output of the second clock signal φ2, and the EX-OR circuit EX1 is connected to the output of the NOT circuit NT1 and the output of the first clock signal φ1, and this EX-OR circuit. A first NOR circuit NR1 is connected to the output of EX1 and the output of the first clock signal φ1, and the output of the first NOR circuit NR1 is newly output to the pulse width modulation circuit 1 as the output of the first clock signal φ1 ′. Is done. Further, the second NOR circuit NR2 is connected to the output of the EX-OR circuit EX1 and the output of the NOT circuit NT1, and the output of the second NOR circuit NR2 is newly subjected to pulse width modulation as the output of the second clock signal φ2 ′. It is output to the circuit 1.

  According to the above configuration, as shown in the timing charts of FIGS. 12C to 12F, the output of the second clock signal φ2 is inverted and output by the NOT circuit NT1 (point K in FIGS. 12 and 13). reference). At this time, a propagation delay time is also generated by the NOT circuit NT1. The output of the NOT circuit NT1 is calculated by the exclusive OR with the first clock signal φ1 by the EX-OR circuit EX1 (see point L in FIGS. 12 and 13). In this case, a propagation delay time is also generated by the EX-OR circuit EX1.

  The output of the EX-OR circuit EX1 is output as the first clock signal φ1 ′ by performing an inversion OR operation with the second clock signal φ2 by the first NOR circuit NR1. In this case, a propagation delay time is also generated by the first NOR circuit NR1. In addition, the output of the EX-OR circuit EX1 is output as the second clock signal φ2 ′ by performing an inversion OR operation with the output of the NOT circuit NT1 by the second NOR circuit NR2. In this case, a propagation delay time is also generated by the second NOR circuit NR2.

  As a result, the dead time DD is generated as the period shown in FIGS. 12E and 12F between the output of the first clock signal φ1 ′ and the output of the second clock signal φ2 ′, and both signals are simultaneously high. The level can be suppressed. The dead time generation circuit 26 is not limited to the above-described configuration, and various logic circuit configurations can be employed.

Second Embodiment
FIG. 14 is a block circuit diagram showing a configuration of a pulse width modulation circuit according to the second embodiment of the present invention. The pulse width modulation circuit 30 of the second embodiment charges and discharges the first and second integrating capacitors C1 and C2 every half cycle of the first clock signal φ1 (or the second clock signal φ2). In contrast to the first embodiment, the first and second integration capacitors C1 and C2 are different from the first embodiment in that only charging is performed.

  The pulse width modulation circuit 30 includes first and second charging bias current sources 31 and 32, an audio signal conversion circuit 33, a clock generation circuit 34, a switch circuit 35, an inverter circuit 36, and third and third. 4 integration circuits 37, 38, third and fourth comparison circuits 39, 40, third and fourth reset circuits 41, 42, first and second RS flip-flop circuits 43, 44, signal output circuit 45, It is constituted by.

  The first and second charging bias current sources 31 and 32 convert a predetermined power supply voltage Va into a bias current Ib and supply it to the downstream third and fourth integrating circuits 37 and 38, respectively. Unlike the configuration of the first embodiment, the first and second charging bias current sources 31 and 32 are directly connected to the third and fourth integrating circuits 37 and 38 without passing through the switch circuit. Specifically, the output of the first charging bias current source 31 (see point A in FIG. 14) is connected to the third integrating circuit 37, and the output of the second charging bias current source 32 (in FIG. 14). Is connected to the fourth integration circuit 38. Accordingly, the bias current Ib generated in the first and second charging bias current sources 31 and 32 is always supplied to the third and fourth integrating circuits 37 and 38, respectively.

The audio signal conversion circuit 33 is a circuit for voltage-current conversion of the audio signal e _S supplied from the audio signal generation source AU (see FIG. 1) to the pulse width modulation circuit 1, and according to the second embodiment. Also in the audio signal conversion circuit 33, the current output from the audio signal conversion circuit 33 can be expressed by G · e _S.

  Unlike the clock generation circuit 15 according to the first embodiment, the clock generation circuit 34 outputs a single third clock signal φ3 shown in FIG. The third clock signal φ3 is for switching the switch circuit 35. The clock generation circuit 34 outputs the third clock signal φ3 and, for example, by combining with the inverter circuit 36, a clock signal (not shown) having an inverted phase obtained by inverting the third clock signal φ3. It may be output.

The switch circuit 35 is switched by the third clock signal φ3 from the clock generation circuit 34, the current (G · e _S ) from the audio signal conversion circuit 33 is supplied to the third integration circuit 37, and the audio signal conversion The state in which the current (G · e _S ) from the circuit 33 is supplied to the fourth integrating circuit 38 is switched.

For example, when the third clock signal φ3 is at a high level, the switch circuit 35 is switched to the third integration circuit 37 side (see the state of the switch circuit 35 in FIG. 14), whereby the current from the audio signal conversion circuit 33 ( G · e _S ) is combined with the bias current Ib from the first charging bias current source 31 and supplied to the third integrating circuit 37. At this time, the bias current Ib from the second charging bias current source 32 is directly supplied to the fourth integrating circuit 38.

On the other hand, when the third clock signal φ3 becomes low level, the switch circuit 35 is switched to the fourth integration circuit 38 side, whereby the current (G · e _S ) from the audio signal conversion circuit 33 is used for the second charging. It is combined with the bias current Ib from the bias current source 32 and supplied to the fourth integration circuit 38. At this time, the bias current Ib from the first charging bias current source 31 is directly supplied to the third integrating circuit 37.

  The third and fourth integrating circuits 37 and 38 are constituted by integrating capacitors in the same manner as the first and second integrating circuits 17 and 18 according to the first embodiment, and the third integrating capacitor C3 and the fourth integrating capacitor. Each has C4. The first integration capacitor C1 and the second integration capacitor C2 according to the first embodiment are provided with a charge period and a discharge period for each half cycle of the first or second clock signal φ1, φ2, respectively. However, the third integration capacitor C3 and the fourth integration capacitor C4 according to the second embodiment are continuously charged in one cycle as will be described later.

  The third and fourth comparison circuits 39 and 40 have substantially the same configuration and function as the first and second comparison circuits 19 and 20 according to the first embodiment, and the third integration capacitor C3 and the fourth integration circuit. This is a circuit for defining the pulse width of the pulse width modulation signal PWM-OUT at its output by comparing the voltage at the capacitor C4 with a predetermined reference voltage Vref. The output of the third comparison circuit 39 (see point C in FIG. 14) is connected to the set terminal (S) of the first RS flip-flop circuit 43, and the output of the fourth comparison circuit 40 (see point D in FIG. 14) is The second RS flip-flop circuit 44 is connected to the set terminal (S).

  The third and fourth reset circuits 41 and 42 force the charging states of the third and fourth integration capacitors C3 and C4 during the period when the third and fourth integration capacitors C3 and C4 are charged, respectively. It is a circuit for terminating (resetting). The third reset circuit 41 includes a third NOR circuit N3 and a seventh switch SW7, and the fourth reset circuit 42 includes a fourth NOR circuit N4 and an eighth switch SW8.

  The third NOR circuit N3 has one input terminal connected to the Q (/) terminal (see point E in FIG. 14) of the first RS flip-flop circuit 43, and the other input terminal connected to the clock generation circuit 34. A 3-clock signal φ3 is input. The output terminal of the third NOR circuit N3 (see point I in FIG. 14) is connected to the seventh switch SW7, and the output of the third NOR circuit N3 controls the on / off operation of the seventh switch SW7.

  The fourth NOR circuit N4 has one input terminal connected to the Q (/) terminal (see point F in FIG. 14) of the second RS flip-flop circuit 44, and a clock obtained by inverting the third clock signal φ3 by the inverter circuit 36. A signal is input. The output terminal of the fourth NOR circuit N4 (see point J in FIG. 14) is connected to the eighth switch SW8, and the output of the fourth NOR circuit N4 controls the on / off operation of the eighth switch SW8.

  The first RS flip-flop circuit 43 is a circuit for holding the output of the first comparison circuit 39 for a predetermined period. The first RS flip-flop circuit 43 is configured by combining the fifth and sixth NOR circuits N5 and N6. In the first RS flip-flop circuit 43, the output terminals of the fifth and sixth NOR circuits N5 and N6 are connected to one another. Connected to the input terminal. The other input terminals of the fifth and sixth NOR circuits N5 and N6 are connected to the ground terminal via the resistors R5 and R6, respectively, and are normally maintained at a low level.

  The other input terminal of the fifth NOR circuit N5 is a terminal to which the set signal (S) is input as an RS flip-flop, and the other input terminal of the sixth NOR circuit N6 is an input to the reset signal (R) as an RS flip-flop. Terminal. The output terminal of the fifth NOR circuit N5 corresponds to the Q (/) terminal of the RS flip-flop, and the output terminal of the sixth NOR circuit N6 corresponds to the Q terminal of the RS flip-flop.

  The other input terminal of the fifth NOR circuit N5 is connected to the output terminal of the first comparison circuit 39, and the other input terminal of the sixth NOR circuit N6 is connected to the clock generation circuit 34, and the third clock signal φ3. Is entered.

  The second RS flip-flop circuit 44 is a circuit for holding the output of the second comparison circuit 40 for a predetermined period. As shown in FIG. 14, the second RS flip-flop circuit 44 is configured by seventh and eighth NOR circuits N7 and N8, and has substantially the same configuration as the first RS flip-flop circuit 43.

  The signal output circuit 45 is configured by a ninth NOR circuit N9. The input terminal of the ninth NOR circuit N9 includes the output terminal (Q terminal) of the sixth NOR circuit N6 of the first RS flip-flop circuit 43 and the second RS flip-flop circuit 44. The output terminal (Q terminal) of the eighth NOR circuit N8 is connected. The pulse width modulation signal PWM-OUT is output from the output terminal of the ninth NOR circuit N9.

  FIG. 15 is a diagram illustrating a voltage waveform at one end of the third integrating capacitor C3 (see the point A in FIG. 14) in the signal change of the third clock signal φ3.

At point A in FIG. 14, when the third clock signal φ3 is at a high level (see the first period T1), the switch circuit 35 is switched to the third integrating circuit 37 side, whereby the third integrating capacitor C3 is charged. Is done. That is, the bias current Ib from the first charging bias current source 31 and the current (G · e _S ) from the audio signal conversion circuit 33 are combined, and the combined sum current is supplied to the third integrating capacitor C3. (Ib + G · e _S ) flows, and charging is performed in the third charging capacitor C3.

The voltage waveform indicated by the symbol W0 in FIG. 15 indicates a waveform when the audio signal e _S is not present, and the voltage waveform indicated by the symbol W1 indicates that the audio signal e _S is positive (0 <(G · e _S ) <(Ib / 2)) when the amplitude is relatively large (that is, when the modulation factor m is relatively high), and the voltage waveform of the sign W2 indicates that the audio signal e _S is negative (0> (G · e _S )> (− Ib / 2)) and the waveform is shown when the amplitude is relatively large.

According to FIG. 15, the voltage waveform W1 when the audio signal e _S is positive and the amplitude thereof is relatively large has a steeper slope than the voltage waveform W0 when the audio signal e _S is no signal. The voltage waveform W2 when the audio signal e _S is negative and its amplitude is relatively large has a gentler slope than the voltage waveform W0 when the audio signal e _S is no signal.

The charging in the third charging capacitor C3 is continued until the level of the third clock signal φ3 is inverted, that is, the charging in the third integrating capacitor C3 is maximum when the level of the third clock signal φ3 is inverted. Become. For example, as shown in FIG. 15, when the audio signal e _S is no signal, the maximum charging voltage is Vm0. When the audio signal e _S is positive and the amplitude is relatively large, the maximum charging voltage is Vm1 (> Vm0). When the audio signal e _S is negative and the amplitude is relatively large, the maximum charging voltage is Vm2 (<Vm0).

When the third clock signal φ3 is inverted to a low level (see the second period T2), the switch circuit 35 is switched to the fourth integration circuit 38 side, and the fourth charge / discharge capacitor C4 is charged. Since the switch circuit 35 is switched to the fourth integration circuit 38 side in the third integration capacitor C3 in the second period T2, the current (G · e _S ) from the audio signal conversion circuit 33 does not flow, and Since only the bias current Ib from the one charging bias current source 31 flows, the slope of the voltage waveform (point A waveform) in the second period T2 is independent of the positive / negative state and amplitude of the audio signal e _S. , Always constant.

  In the second period T2, the charging of the third integration capacitor C3 is continued with a constant voltage waveform slope, and the voltage at the point A of the third integration capacitor C3 is the reference voltage Vref of the third comparison circuit 39. The third switch SW7 is turned on by the third reset circuit 41.

  That is, when the voltage at the point A of the third integration capacitor C3 reaches the reference voltage Vref, the output of the third comparison circuit 39 instantaneously becomes a high level, which is the set terminal (S of the first RS flip-flop circuit 43). ). As a result, the Q (/) terminal of the first RS flip-flop circuit 43 becomes low level, and this is input to the third NOR circuit N3 of the third reset circuit 41. In the third NOR circuit N3, since the low level signal of the third clock signal φ3 (due to the second period T2) is input, the output of the third NOR circuit N3 becomes high level, and this is used as the reset signal. The seventh switch SW7 is turned on by outputting to the switch SW7.

When the seventh switch SW7 is turned on, the voltage at one end of the third integration capacitor C3 is instantaneously supplied to the ground potential, and the charge accumulated in the third integration capacitor C3 is forcibly discharged, and the third integration The voltage at the capacitor C3 is reset to zero (see t _{R in} FIG. 15). The reset timing depends on the positive / negative state of the audio signal e _S and the magnitude of the amplitude.

That is, the third integrating capacitor C3 is charged in the first period T1, and the charge amount in this charging depends on the positive and negative states of the audio signal e _S and the magnitude of the amplitude. Then, in the second period T2, the third integration capacitor C3 is charged by the bias current Ib, but since the amount of charge in this case is constant, charging by the bias current Ib of the third integration capacitor C3 is started. The time t until the voltage of the third integrating capacitor C3 reaches the reference voltage Vref after the transition to the second period T2 depends on the positive / negative state of the audio signal e _S and the magnitude of the amplitude. Will do.

For example, if the audio signal e _S is positive and the amplitude is relatively large, the voltage at the third integrating capacitor C3 becomes the maximum charging voltage Vm1, and in this case, the voltage at the third integrating capacitor C3 is the reference voltage. The time required to reach Vref (see t _{1 in} FIG. 15) is longer than that in the case where the audio signal e _S is no signal (see t _{0 in} FIG. 15). Conversely, when the audio signal e _S is negative and the amplitude is relatively large, the voltage at the third integration capacitor C3 becomes the maximum charging voltage Vm2, and in this case, the voltage of the third integration capacitor C3 is the reference. time until the voltage Vref (see t ₂ in FIG. 15) the audio signal e _S is shorter than that of the case of no signal (see t ₀ in FIG. 15).

In other words, the time t from the charging only by the bias current Ib of the third integrating capacitor C3 is started until the voltage of the third integrating capacitor C3 reaches the reference voltage Vref, the positive and negative state and the amplitude of the audio signal e _S If the pulse width of the pulse width modulation signal is generated based on the time t, the pulse width is generated based on the third clock signal φ3 having a constant period. Can do.

Here, the capacitances of the third and fourth integration capacitors C3 and C4 are the same (= C), and the period (for example, corresponding to the first period T1) is the charging time of the third and fourth integration capacitors C3 and C4. If T is T, the maximum charging voltage Vm is expressed by Vm = [(Ib + G · e _S ) · T] / C.

  Assuming that the period from when charging with only the bias current Ib is started until the voltage of the third integration capacitor C3 (or the fourth integration capacitor C4) reaches the reference voltage Vref is t, the reference voltage Vref is Vref = Vm + It is expressed by (Ib · t) / C.

Here, by transforming both equations and obtaining t, t becomes t = [C · (Vref)] / Ib − [(1+ (G · e _S ) / Ib)] · T, and T−t = 2T + (G · e _S ) / Ib · T− (C · Vref) / Ib.

On the other hand, since the modulation degree m is expressed by m = [t− (T−t)] / T, m = [2C · (Vref)] / (Ib · T) −3−2 (G · e _S ) / Ib. The condition that the modulation degree m is proportional to the audio signal e _S is [2C · (Vref)] / (Ib · T) = 3, that is, satisfies (Ib · T) / C = 2Vref / 3. If the bias current Ib and the capacitances of the third and fourth integration capacitors C3 and C4 are selected, appropriate pulse width modulation can be realized.

FIGS. 16 to 18 are diagrams showing timing charts of respective signals in the pulse width modulation circuit 30. FIG. FIG. 16 shows a case where the audio signal e _S is no signal (G · e _S = 0), and FIG. 17 shows a case where the audio signal e _S is a positive value (0 <G · e _S <Ib / FIG. 18 shows a case where the audio signal e _S is negative (0> G · e _S > −Ib / 2).

In the first period T1 in FIG. 16, the third clock signal φ3 from the clock generation circuit 34 is at a high level, whereby the switch circuit 35 is switched to the third integration circuit 37 side. Therefore, the bias current Ib from the first charging bias current source 31 and the current (G · e _S ) from the audio signal conversion circuit 33 are synthesized in the third integrating capacitor C3 of the third integrating circuit 37. The sum current (Ib + G · e _S ) is supplied, and the third integrating capacitor C3 is charged (see waveform at point A).

  In the first period T1, since the switch circuit 35 is switched to the third integration circuit 37 side, the fourth integration capacitor C4 of the fourth integration circuit 38 has a bias from the second charging bias current source 32. The current Ib is supplied, and the fourth integrating capacitor C4 is charged with a constant charge amount by the bias current Ib (see waveform at point B).

  In the first period T1, when the voltage resulting from charging the fourth integrating capacitor C4 in the fourth comparison circuit 40 reaches the reference voltage Vref, the output of the fourth comparison circuit 40 instantaneously changes from the low level to the high level. (Refer to the waveform at point D). Since the output of the fourth comparison circuit 40 is input to the set terminal (S) of the second RS flip-flop circuit 44, the Q (/) terminal of the second RS flip-flop circuit 44 is set from high level to low level. The

  The Q (/) terminal of the second RS flip-flop circuit 44 is connected to one input terminal of the fourth NOR circuit N4 of the fourth reset circuit 42, and the other input terminal of the fourth NOR circuit N4 is connected to the inverter circuit 36. Since the low level (the third clock signal φ3 is the high level) is input, the output of the fourth NOR circuit N4 changes from the low level to the high level (see the waveform at point J), and this reset signal is sent to the eighth switch SW8. Is output.

  As a result, the eighth switch SW8 changes from the OFF operation to the ON operation, and the charge stored in the fourth integrating capacitor C4 flows to the ground terminal via the eighth switch SW8, and is discharged forcibly and at once. Is called.

  The output (refer to the waveform at point H) of the Q terminal of the second RS flip-flop circuit 44 is input to the ninth NOR circuit N9 and output as the pulse width modulation signal PWM-OUT.

Next, in the period of the second period T2, the third clock signal φ3 from the clock generation circuit 34 changes from the high level to the low level, whereby the switch circuit 35 is switched to the fourth integration circuit 38 side. Therefore, the sum current (Ib + G · e _S ) is supplied to the fourth integration capacitor C4 of the fourth integration circuit 38, and the fourth integration capacitor C4 is charged thereby (see waveform at point B).

  In the second period T2, since the switch circuit 35 is switched to the fourth integrating circuit 38 side, the third integrating capacitor C3 of the third integrating circuit 37 has a bias from the second charging bias current source 32. Only the current Ib is supplied, and the third integrating capacitor C3 is charged with a constant charge amount by the bias current Ib (see waveform at point A).

  In the second period T2, when the voltage resulting from charging of the third integrating capacitor C3 in the third comparison circuit 39 reaches the reference voltage Vref, the output of the third comparison circuit 39 instantaneously changes from the low level to the high level. (See waveform at point C). Since the output of the third comparison circuit 39 is input to the set terminal (S) of the first RS flip-flop circuit 43, the Q (/) terminal of the first RS flip-flop circuit 43 is set from the high level to the low level. (Refer to point E waveform).

  The Q (/) terminal of the first RS flip-flop circuit 43 is connected to one input terminal of the third NOR circuit N3 of the third reset circuit 41, and the other input terminal of the third NOR circuit N3 is connected to the clock generation circuit 34. Since the third clock signal φ3 (low level in the second period T2) is input, the output of the third NOR circuit N3 changes from the low level to the high level (refer to the waveform at the point I). 7 is output to the switch SW7.

  As a result, the seventh switch SW7 changes from the OFF operation to the ON operation, and the charge stored in the third integrating capacitor C3 flows to the ground terminal via the seventh switch SW7, and is discharged forcibly and at once. Is called.

  The output of the Q terminal of the first RS flip-flop circuit 43 (see waveform at point G) is input to the ninth NOR circuit N9 and output as the pulse width modulation signal PWM-OUT.

Thereafter, in the third period T3, since the third clock signal φ3 is inverted, the third integration capacitor C3 is charged according to the amplitude of the audio signal e _S , while the fourth integration capacitor C4 is biased. Charging according to the current Ib is performed. Thereafter, every time a half cycle elapses, the third clock signal φ3 is inverted, and the third and fourth integration capacitors C3 and C4 are charged according to the amplitude of the audio signal e _S and charged according to the bias current Ib. Repeated alternately.

As shown in FIG. 17, when the audio signal e _S is positive, the sum current (G · e _S + Ib) becomes large, and one end (point A) of the third or fourth integrating capacitors C3, C4 Alternatively, the slope of the voltage waveform at point B) also becomes steep. Therefore, the charging voltage Vm of the third or fourth integrating capacitors C3 and C4 at the time when the period of the half cycle changes becomes relatively large, and when these are charged in the next half cycle, the audio signal e _S is not signaled. Compared with the case, the time to reach the reference voltage Vref, that is, the time t from when charging is started to when it is forcibly reset only by supplying the bias current Ib is shortened. Therefore, the pulse width modulation signal PWM-OUT is output at the timing shown in FIG. Thus, the pulse width modulation signal PWM-OUT corresponding to the amplitude of the audio signal e _S is output.

As shown in FIG. 18, when the audio signal e _S is negative, the magnitude of the sum current (G · e _S + Ib) is small, and is applied to one end of the third or fourth integrating capacitors C3 and C4. The slope of the voltage waveform also becomes gentle. Therefore, the charging voltage Vm at one end of the third or fourth integrating capacitors C3 and C4 at the time when the half cycle period changes is relatively small, and when these are charged in the next half cycle, the audio signal e _S is Compared to the case of no signal, the time to reach the reference voltage Vref, that is, the time t from when charging is started to when it is forcibly reset only by supplying the bias current Ib becomes longer. Therefore, the pulse width modulation signal PWM-OUT is output at the timing indicated by the pulse width modulation signal PWM-OUT in FIG.

  Also in the second embodiment, since the third clock signal φ3 having a substantially constant cycle is used, the carrier frequency f can be made substantially constant, and the increase in the leakage amount of the carrier component can be suppressed. In addition, the same effects as those of the first embodiment can be obtained.

In the pulse width modulation circuit 1 according to the first embodiment, when the first and second comparison circuits 19 and 20 are composed of general-purpose CMOS inverter elements, the reference voltage Vref of the first and second comparison circuits 19 and 20 is If the power supply voltage of the CMOS inverter element is about 5V, it is about 2.5V, which is half of that. When the audio signal e _S is no signal, the maximum charging voltage Vm charged in the unit period (for example, the first period T1) of the first or second integrating capacitors C1 and C2 is twice the reference voltage Vref. The circuit constants are set so as to be values. Therefore, for example, when the audio signal e _S having the maximum amplitude is input, the maximum charging voltage Vm may greatly exceed the power supply voltage of the CMOS inverter element (e.g., rise to around 7.5 V). Arise. In some cases, if the maximum charging voltage Vm is high, this may exceed the breakdown voltage of the gate oxide film of the CMOS inverter element, and the CMOS inverter element may be destroyed.

  However, according to the second embodiment, the maximum charging voltage Vm of the third or fourth integrating capacitor C3, C4 does not exceed the reference voltage Vref (see FIG. 15), so the maximum charging voltage Vm is equal to the CMOS inverter. It is possible to prevent the power supply voltage of the element from being exceeded, and to eliminate the risk of the CMOS inverter element being destroyed.

  In the pulse width modulation circuit 1 according to the first embodiment, the switch circuit 14 for switching the current direction in the charge / discharge operation of the first and second integrating capacitors C1 and C2 is usually configured by a general-purpose electronic switch. In many cases, the maximum charging voltage Vm by the first and second integration capacitors C1 and C2 may be supplied to the electronic switch. Therefore, the electronic switch includes the first and second integration capacitors. A power supply voltage higher than the maximum charging voltage Vm of the capacitors C1 and C2 is supplied.

  The charging bias current source 11 is supplied with a power supply voltage sufficiently higher than the maximum charging voltage Vm, and the discharging bias current source 16 is lower than the low potential voltage of the power supply voltage of the CMOS inverter element. Power supply voltage is supplied. Therefore, in the pulse width modulation circuit 1 according to the first embodiment, each circuit requires a large number of power supply voltages having different output voltage values corresponding to them, and the number of necessary power supplies increases. It was.

  However, in the pulse width modulation circuit 30 according to the second embodiment, since the maximum charging voltage Vm does not exceed the reference voltage Vref, the switch circuit 35 corresponding to the switch circuit 14 of the first embodiment or the first embodiment. It is not necessary to supply a power supply voltage higher than the maximum charging voltage Vm to the first and second charging bias current sources 31 and 32 corresponding to the charging bias current source 11. Further, the reverse current prevention diodes D1 to D4 (see FIG. 8) for preventing the charging current from being biased by the power supply voltage of the CMOS inverter element are also unnecessary.

In the pulse width modulation circuit 1 according to the first embodiment, since the reference level of the input audio signal e _S is different from the reference level of the pulse width modulation output, a circuit that performs signal level shifting (ground) A circuit that converts a signal based on the potential into the same reference potential as that of the charging bias current source 11 (for example, R1 to R4 shown in FIG. 8) is also required.

  However, in the pulse width modulation circuit 30 according to the second embodiment, since the maximum charge voltage Vm does not exceed the reference voltage Vref, the level shift circuit is not necessary, and the power supply voltage value supplied to each circuit is The power supply voltages can be shared and do not require a large number of power supply voltages having different output voltage values. For example, as shown in FIG. 19 to be described later, the power necessary for the pulse width modulation circuit 30 is a ± 10 V system supplied to the first and second charging bias current sources 31 and 32 and the voltage / current conversion circuit 33. There may be two types of power supply and 5V power supply supplied to logic gates such as the third and fourth comparison circuits 39, 40 and the first and second RS flip-flops 43, 44. Therefore, it can contribute to the reduction of parts cost.

  FIG. 19 is a detailed circuit diagram of the pulse width modulation circuit shown in FIG.

  According to the circuit diagram shown in FIG. 19, the first and second charging bias current sources 31 and 32 are configured as a single circuit by combining a plurality of CMOS inverter elements. The clock generation circuit 34 is configured by a multivibrator including a plurality of inverters, resistors, and capacitors. The switch circuit 35 includes two switch elements 35a and 35b. The switch element 35a is ON / OFF controlled by a third clock signal φ3, and the switch element 35b is a fourth clock signal obtained by inverting the third clock signal φ3. On / off control is performed by φ4.

  Further, the reset signals of the third and fourth reset circuits 41 and 42 use the outputs of the Q terminals of the first and second RS flip-flop circuits 43 and 44, respectively, and the voltages at the points G and I in FIG. Since the waveforms and the voltage waveforms at points H and j in FIG. 14 are the same, the outputs of the Q (/) terminals of the first and second RS flip-flop circuits 43 and 44 are not used.

FIG. 20 is a diagram showing a modification of the pulse width modulation circuit 30 shown in FIG. In the pulse width modulation circuit 30 of FIGS. 14 and 19, the audio signal e _S output from the audio generation source AU (see FIG. 1) has positive and negative amplitudes with respect to the reference potential. Reference numeral 33 denotes a so-called bipolar signal current that is generated by converting positive and negative amplitudes of the audio signal e _S into positive and negative currents. Therefore, the bias current Ib is constantly supplied to the third and fourth integrating circuits 37 and 38 by the charging bias current sources 31 and 32.

  Here, the audio generation source AU outputs a unipolar signal current in which a fixed bias current Ib1 is added to the bipolar signal current and output, for example, as in a current output DA converter (not shown). In this case, as shown in FIG. 20, a charging bias current source 47 for outputting a fixed bias current Ib2 is separately provided, and a unipolar signal current and a fixed bias current Ib2 are switched to switch the third and third bias currents Ib2. The fourth integrating circuits 37 and 38 may be charged.

  Specifically, the output of the audio signal conversion circuit 46 that is output by adding the fixed bias current Ib1 to the bipolar signal current and the output of the charging bias current source 47 are switched based on the third clock signal φ3. A changeover switch 48 is provided. For example, in the first period T1 shown in FIG. 15, the output of the audio signal conversion circuit 46 is switched to the third integration circuit 37 side, and the output of the charging bias current source 47 is switched to the fourth integration circuit 38 side. In the period T2, the output of the audio signal conversion circuit 46 is switched to the fourth integration circuit 38 side, and the output of the charging bias current source 47 is switched to the third integration circuit 37 side.

Thereby, in the first period T1, the third integrating circuit 37 is charged with the sum current (Ib1 + e _S ) of the fixed bias current Ib1 and the audio signal e _S , while the fourth integrating circuit 38 is fixed with the fixed bias. It is charged with current Ib2. In the second period T2, the third integrating circuit 37, while being charged with a fixed bias current Ib2, fourth integrating circuit 38, the sum current of a fixed bias current Ib1 and the audio signal e _S (Ib1 + e _S ) Is charged. Therefore, substantially the same operation as the pulse width modulation circuit 30 of FIGS. 14 and 19 can be realized, and an appropriate pulse width modulation signal PWM-OUT can be output.

In the audio signal conversion circuit 46, in order to output a unipolar signal current, the fixed bias current Ib1 needs to be larger than the absolute value of the audio signal e _S (Ib1 ≧ | e _S |). Further, the bias current Ib1 and the bias current Ib2 do not need to be set to the same value, and the modulation degree m is zero when the audio signal e _S is not present, and m when the audio signal e _{S is} the maximum signal. It is desirable that Ib2 ≧ Ib1 so that <1 is satisfied.

  Of course, the scope of the present invention is not limited to the above-described embodiment, and the circuit configurations shown in the first and second embodiments are examples, and various circuits can be used as long as they have equivalent functions. Can be applied.

1 is a configuration diagram illustrating a switching amplifier to which a pulse width modulation circuit according to a first embodiment of the present invention is applied. FIG. 2 is a block circuit diagram illustrating an embodiment of the pulse width modulation circuit illustrated in FIG. 1. It is a figure which shows the operation | movement relationship between a 1st and 2nd clock signal and a 1st thru | or 4th switch. It is a figure which shows the relationship between a 2nd clock signal and the voltage waveform in the A point of FIG. FIG. 3 is a timing chart showing a relationship between first and second clock signals and voltage waveforms at respective points in FIG. 2, and is a diagram showing a case where there is no audio signal. FIG. 3 is a timing chart showing a relationship between first and second clock signals and voltage waveforms at respective points in FIG. 2, and showing a case where an audio signal is positive. FIG. 3 is a timing chart showing a relationship between first and second clock signals and voltage waveforms at respective points in FIG. 2, and showing a case where an audio signal is negative. FIG. 3 is a detailed circuit diagram of the pulse width modulation circuit shown in FIG. 2. FIG. 10 is a diagram showing another modification of the clock generation circuit shown in FIG. 8. It is a figure which shows the modification of an audio signal conversion circuit, a charging bias current source, and a current addition circuit. It is a figure which shows the modification of the bias current source for discharge. It is a timing chart which shows the modification of the 1st and 2nd clock signal. It is a circuit diagram which shows a dead time generation circuit. It is a block circuit diagram which shows the pulse width modulation circuit which concerns on 2nd Embodiment of this invention. It is a figure which shows the relationship between a 3rd clock signal and the voltage waveform in the A point of FIG. It is a timing chart which shows the relationship between a 3rd clock signal and the voltage waveform in each point of FIG. 14, and is a figure which shows the case where an audio signal is a no signal. It is a timing chart which shows the relationship between a 3rd clock signal and the voltage waveform in each point of FIG. 14, and is a figure which shows the case where an audio signal is positive. It is a timing chart which shows the relationship between a 3rd clock signal and the voltage waveform in each point of FIG. 14, and is a figure which shows the case where an audio signal is negative. FIG. 15 is a detailed circuit diagram of the pulse width modulation circuit shown in FIG. 14. It is a figure which shows the modification of the pulse width modulation circuit shown in FIG. It is a block diagram which shows the switching amplifier with which the conventional pulse width modulation circuit is applied. It is a circuit diagram which shows the conventional pulse width modulation circuit. It is a figure which shows the output waveform of the modulation signal by the conventional pulse width modulation circuit, and the output waveform after switching in the point P of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Pulse width modulation circuit 2 Switching circuit 3 Low pass filter circuit 4 1st power supply 5 2nd power supply 11 Audio signal conversion circuit 12 Charging bias current source 13 Current addition circuit 14 Switch circuit 15 Clock generation circuit 16 Discharge bias current source 17 1 integration circuit 18 second integration circuit 19 first comparison circuit 20 second comparison circuit 21 first reset circuit 22 second reset circuit 23 signal output circuit 30 pulse width modulation circuit 31 first charging bias current source 32 second charging Bias current source 33 Audio signal conversion circuit 34 Clock generation circuit 35 Switch circuit 36 Inverter circuit 37 Third integration circuit 38 Fourth integration circuit 39 Third comparison circuit 40 Fourth comparison circuit 41 Third reset circuit 42 Fourth reset circuit 43 1RS flip-flop circuit 44 2nd RS flip-flop Circuit 45 signal output circuit C1 first integration capacitor C2 second integration capacitor AU audio generation source e _S audio signal Ib bias current T1 first period T2 second period T3 third period Vref reference voltage φ1 first clock signal φ2 Second clock signal φ3 Third clock signal

Claims (10)

In a first period that is a half cycle of a predetermined clock signal, the first integration circuit is charged based on a current based on an input signal, and in a second period following the first period that is shifted from the first period by a half cycle. Changing the charging voltage accumulated in the first integrating circuit based on a constant bias current, and charging a second integrating circuit different from the first integrating circuit based on the current based on the input signal, An integration control circuit that changes a charging voltage accumulated in the second integration circuit based on the bias current in a third period of a half cycle following the second period;
A first detection circuit for detecting a time from when the second period starts until the voltage in the first integration circuit reaches a predetermined reference voltage;
A second detection circuit that detects a time from when the third period starts until the voltage in the second integration circuit reaches a predetermined reference voltage;
A pulse signal generation circuit that generates a pulse signal having a pulse width of the time based on a time alternately output from the first detection circuit and the second detection circuit every half cycle of the clock signal;
A pulse width modulation circuit comprising: The integration control circuit includes:
A first discharge circuit for discharging at a constant discharge amount based on the constant bias current in the second period;
A second discharge circuit for discharging at a constant discharge amount based on the constant bias current in the third period;
The pulse width modulation circuit according to claim 1, comprising: The integration control circuit includes:
A voltage-current conversion circuit that converts a voltage based on the input signal into a current;
A bias current generating circuit for generating the constant bias current;
An addition circuit for adding the current converted by the voltage-current conversion circuit and the constant bias current generated by the bias current generation circuit;
A switching circuit that switches between a state in which the output of the addition circuit is supplied to the first integration circuit and a state in which the output of the addition circuit is supplied to the second integration circuit, based on the clock signal;
The pulse width modulation circuit according to claim 1, further comprising: The integration control circuit includes:
A first charging circuit that charges the first integrating circuit at a constant rate based on the constant bias current in the second period;
A second charging circuit for charging the second integrating circuit at a constant rate based on the constant bias current in the third period;
The pulse width modulation circuit according to claim 1, comprising: The integration control circuit includes:
A first bias generation circuit for generating the constant bias current;
A second bias generation circuit for generating another constant bias current different from the bias current;
A voltage-current conversion circuit that converts a voltage based on the input signal into a current;
A state in which the current converted by the voltage-current conversion circuit is added to the bias current generated by the first bias generation circuit and supplied to the first integration circuit, and the current converted by the voltage-current conversion circuit is A switching circuit for switching a state of adding to the bias current generated by the two bias generation circuit and supplying the bias current to the second integration circuit based on the clock signal;
The pulse width modulation circuit according to claim 1, further comprising: The first detection circuit includes:
A first comparison circuit that compares the charging voltage accumulated in the first integration circuit in the second period with a predetermined reference voltage;
The second detection circuit includes:
A second comparison circuit that compares the charging voltage accumulated in the second integration circuit in the third period with a predetermined reference voltage;
The pulse width signal generation circuit includes:
6. The pulse width modulation circuit according to claim 1, wherein the pulse signal is generated based on an output of the first comparison circuit and an output of the second comparison circuit. A first forced discharge circuit for forcibly discharging the charge voltage accumulated in the first integration circuit based on the output of the first comparison circuit;
A second forced discharge circuit for forcibly discharging the charge voltage accumulated in the second integration circuit based on the output of the second comparison circuit;
The pulse width modulation circuit according to claim 6 provided.   The pulse width modulation circuit according to claim 1, further comprising a clock generation circuit that generates the clock signal.   The pulse width modulation circuit according to claim 8, further comprising a dead time generation circuit that generates a dead time for suppressing a delay time when the clock signal generated from the clock generation circuit is inverted. A pulse width modulation circuit according to any one of claims 1 to 9,
A voltage source that outputs a predetermined power supply voltage;
A switching circuit for switching a predetermined power supply voltage supplied from the voltage source based on a modulation signal output from the pulse width modulation circuit;
A switching amplifier characterized by comprising:

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