JPH03123117A - Pulse signal duty cycle-voltage converter - Google Patents

Abstract

PURPOSE:To decrease the ripple and to quickly execute the response by a simple circuit by using an integrator, etc., to generate a voltage value corresponding to a duty cycle of a pulse signal and transferring it to the outside, when a level of the pulse signal is varied. CONSTITUTION:A buffer 1 inputs a pulse signal S and controls an analog switch 3 by its inversion output signal, and an integrator 4 integrates a positive or negative reference voltage VREF inputted from the analog switch 3 and outputs a voltage corresponding to the duty cycle of the pulse signal S. When the pulse signal S is converted to a high level, a hold signal - HOLD of a short pulse is outputted from a differentiating circuit 9, and an analog switch 5 is turned on through a buffer 10. Subsequently, an integral voltage value A of the integrator 4 is held in a data holding capacitor 6, and transferred as an output voltage VOUT to the outside by a buffer circuit 15. In such a way, the ripple is decreased and the response can be executed quickly by using a simple constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to pulse signal duty cycle to voltage converters.

[Conventional technology]

As a conventional technology of a pulse signal duty cycle-voltage converter, for example, the Utsukasho+12-141 shown in FIG.
Issue 221 has been opened. In this conventional example, when the pulse signal is at a high level, the reference voltage and ground are connected to the reference Ql+ voltage that generates the J1L quasi-voltage, the differential amplifier circuit, and the non-inverting input terminal and inverting input terminal of the differential amplifier circuit, respectively. an analog switch that inputs the ground and reference voltage when the pulse signal is at a low level, and a positive dip feedback type that inputs the output of the differential amplifier circuit and outputs a voltage corresponding to the duty cycle of the pulse signal. It has a second-order low-pass filter, and in this way, a highly accurate reference voltage is used, and the internal resistance of the changeover switch and the external connection of the differential amplifier circuit are controlled by using a circuit where the temperature effect of the resistance can be ignored. By passing the output through a vocal feedback secondary low-pass filter, a voltage corresponding to a highly accurate and stable duty cycle that is unaffected by fluctuations in the power supply voltage is obtained.

[Problem to be solved by the invention]

In the conventional example described above, the signal, which is originally a pulse, is passed through a filter, so there is P in the output signal as shown in Figure 4.
The ripple of the WM signal component is included, and if you try to reduce the ripple with the filter constant, the frequency 4r 't'
[There is a drawback that [] is reduced.

An object of the present invention is to provide a pulse signal duty cycle-to-voltage converter with less ripple and quick response using a simple configuration equivalent to the conventional example described above.

[Failure to solve the problem]

The pulse signal duty cycle-to-voltage converter of the present invention includes a reference voltage circuit that generates a reference voltage, an integrator having a non-inverting input terminal and an inverting input terminal, and the non-inverting input terminal when the pulse signal is at a high level. an analog switch that inputs a reference voltage to the input terminal and inputs the reference voltage to the inverting input terminal when the pulse signal is low level; and an analog switch that inputs the reference voltage to the inverting input terminal when the pulse signal is low level; A voltage holding circuit that holds and outputs the applied voltage value, a discharge circuit that clears the contents of the integrator immediately after the voltage holding circuit holds the voltage value output from the integrator, and a voltage holding circuit that outputs the voltage value output from the voltage holding circuit. A buffer circuit is used to transmit the information to the outside.

(Function) Since positive and negative reference voltages are input to the integrator corresponding to the high and low levels of the pulse signal, the voltage integrated output value when the pulse signal changes from low level to high level is the pulse signal duty cycle. It corresponds to Therefore, the voltage value is taken out to the outside and used as a required D/A conversion value, and at the same time, the contents of the integral value are cleared in preparation for the next pulse signal cycle. Therefore, there is no ripple in the output voltage value, and the delay in the output signal is only one cycle.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the pulse signal duty cycle to voltage converter of the present invention, and FIG. 2 is a timing chart showing the operation of this embodiment.

A reference voltage +VREF is generated by the Zener diode 2 and input to the analog switch 3.

The buffer 1 receives the pulse signal S and controls the analog switch 3 with its inverted output signal.

The analog switch 3 inputs the reference voltage +VREF and the ground G to the non-inverting input terminal and the inverting input terminal of the integrator 4 when the pulse signal S is at a high level, and inputs the ground G and the ground G when the pulse signal S is at a low level. Reference voltage→-■R, :F,
input each. Integrator 4 is analog switch 3
It integrates the positive or negative reference voltage VREI- inputted from and outputs a voltage value corresponding to the duty cycle of the pulse signal S. The inverter 7, the resistor R3, and the NAND gate 8 constitute a differentiating circuit 9, which outputs a short-width hold signal HOLD when the input pulse signal S rises from a low level to a high level. An analog switch 5 is installed on the output side of the integrator 4, and is turned on by the hold signal HOLD via a buffer 10. A data holding capacitor 6 is installed between the output side of the analog switch 5 and the ground G. 4 buffers 11
1 to 114 are connected in series to form the delay circuit 12, and the hold signal HO input from the Nant gate 8
A short width clear signal CLR is output by giving a slight delay to the LD. The clear signal CLR turns on the analog switch 14 via the buffer 13 and clears the contents of the integrator 4. The buffer circuit 15 inputs the voltage value held by the data holding capacitor 6 and outputs the voltage V. Output the IJT to the outside. Note that the voltage holding circuit in the claims corresponds to a circuit including a series of differentiating circuits 9, buffers 10, analog switches 5, and data holding capacitors 6, and the discharge circuit in the claims corresponds to a circuit including a series of differentiating circuits 9, buffers 10, analog switches 5, and data holding capacitors 6. This corresponds to a circuit including a buffer 13 and an analog switch 14.

Next, the operation of this embodiment will be explained using FIG.

The period from time t1 to time t2 is a high level period of the pulse signal S, and the integrator 4 receives the input positive reference voltage +V.
By integrating REF, the output voltage (I) increases. Time t2
Then, the pulse signal S changes to a low level, and the integrator 4 integrates the input negative reference voltage -RF:,P, so the output voltage VD decreases and a triangular waveform is formed. At time t3, when the pulse signal S changes to high level again, a short pulse halt signal HOLD is output from the differentiating circuit 9, and the analog switch 5 is turned on via the buffer 10, so that the integrator at time t3 The integrated voltage value A of 4 is held in the data holding capacitor 6, and output voltage V by the buffer circuit 15. It is communicated externally as IIT. Immediately after the hold signal HOLD, a clear signal CLR is output for a short time with a delay of the delay time of the delay circuit 12, which turns on the analog switch 14 for a short time, discharges the capacitor of the feedback circuit of the integrator 4, and calculates the integrated value. Clear. After that, the same operation is pulsed 4. Repeat during the input period of s.

The voltage value A held in the data holding capacitor 6 at time t3 clearly has a level corresponding to the duty cycle of the pulse signal S, and the resulting output voltage . IIT does not include any ripples, and the response of the output data is only one period of the pulse signal S.

〔Effect of the invention〕

As explained above, the present invention uses an integrator or the like to internally generate a voltage value corresponding to the duty cycle of the pulse signal for each period of the pulse signal, and when the level of the pulse signal changes, the voltage value is generated externally. By transmitting the pulse signal, it is possible to obtain a ripple-free and quick-response pulse signal duty cycle-to-voltage converter with a simple circuit.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the pulse signal duty cycle-voltage converter of the present invention, FIG. 2 is a timing chart showing the operation of this embodiment, and FIG. 3 is a pulse signal duty cycle-voltage converter. FIG. 4 is a circuit diagram showing the configuration of a conventional example of a converter, and FIG. 4 is a timing chart of input and output waveforms of the conventional example of FIG. 1... Buffer, 2... Zener diode, 3... Analog switch, 4... Integrator, 5...
...Analog switch, 6...Data retention capacitor, 7...Inverter, R1...Resistor, 8...
Nant gate, 9... Differential circuit, 10... Buffer, 111-114... Buffer, 12... Delay circuit, 13-... Buffer, 14...
...Analog switch, 15...Buffer circuit, S...Pulse signal, V
OUT...output voltage, HOLD...halt signal,
CLR...Clear signal.

Claims (1)

[Claims] 1. A reference voltage circuit that generates a reference voltage, an integrator having a non-inverting input terminal and an inverting input terminal, and a reference voltage circuit that inputs the reference voltage to the non-inverting input terminal when a pulse signal is at a high level. , an analog switch that inputs a reference voltage to the inverting input terminal when the pulse signal is at a low level; and an analog switch that maintains the voltage value output from the integrator and inputs the voltage value when the pulse signal changes from the low level to the high level. a discharge circuit that clears the contents of the integrator immediately after the voltage holding circuit holds the voltage value output from the integrator, and a buffer that transmits the voltage value output from the voltage holding circuit to the outside. A pulse signal duty cycle to voltage converter having a circuit.