JP2007318104A5 - - Google Patents

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Publication number
JP2007318104A5
JP2007318104A5 JP2007112835A JP2007112835A JP2007318104A5 JP 2007318104 A5 JP2007318104 A5 JP 2007318104A5 JP 2007112835 A JP2007112835 A JP 2007112835A JP 2007112835 A JP2007112835 A JP 2007112835A JP 2007318104 A5 JP2007318104 A5 JP 2007318104A5
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JP
Japan
Prior art keywords
forming
layer
semiconductor layer
type impurity
interlayer insulating
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JP2007112835A
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English (en)
Japanese (ja)
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JP2007318104A (ja
JP5137453B2 (ja
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Priority to JP2007112835A priority Critical patent/JP5137453B2/ja
Priority claimed from JP2007112835A external-priority patent/JP5137453B2/ja
Publication of JP2007318104A publication Critical patent/JP2007318104A/ja
Publication of JP2007318104A5 publication Critical patent/JP2007318104A5/ja
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Publication of JP5137453B2 publication Critical patent/JP5137453B2/ja
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JP2007112835A 2006-04-28 2007-04-23 半導体装置の作製方法 Active JP5137453B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007112835A JP5137453B2 (ja) 2006-04-28 2007-04-23 半導体装置の作製方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2006127087 2006-04-28
JP2006127087 2006-04-28
JP2007112835A JP5137453B2 (ja) 2006-04-28 2007-04-23 半導体装置の作製方法

Publications (3)

Publication Number Publication Date
JP2007318104A JP2007318104A (ja) 2007-12-06
JP2007318104A5 true JP2007318104A5 (https=) 2010-05-06
JP5137453B2 JP5137453B2 (ja) 2013-02-06

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ID=38851652

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007112835A Active JP5137453B2 (ja) 2006-04-28 2007-04-23 半導体装置の作製方法

Country Status (1)

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JP (1) JP5137453B2 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010026865A1 (en) 2008-09-05 2010-03-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor memory device and semiconductor device
JP5455753B2 (ja) 2009-04-06 2014-03-26 株式会社半導体エネルギー研究所 Ｉｃカード
US10014380B2 (en) 2012-12-14 2018-07-03 Cypress Semiconductor Corporation Memory first process flow and device
US9368606B2 (en) 2012-12-14 2016-06-14 Cypress Semiconductor Corporation Memory first process flow and device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10170955A (ja) * 1996-12-09 1998-06-26 Fujitsu Ltd 液晶表示装置及びその製造方法
JP3415401B2 (ja) * 1997-08-28 2003-06-09 株式会社東芝 半導体集積回路装置及びその製造方法
JP2004128471A (ja) * 2002-08-07 2004-04-22 Canon Inc 不揮発メモリ装置
JP4541651B2 (ja) * 2003-03-13 2010-09-08 シャープ株式会社 抵抗変化機能体、メモリおよびその製造方法並びに半導体装置および電子機器
JP2005116889A (ja) * 2003-10-09 2005-04-28 Mitsubishi Electric Corp ポリシリコン膜におけるｐｎ接合の形成方法、薄膜トランジスタ基板の製造方法、および画像表示装置

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