JP2007243018A - Cell arrangement method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a cell arrangement method of a semiconductor device which can distribute heat-generating region without increasing a chip area, by preventing an increase in thermal resistance due to centralized arrangement of heat-generating regions. <P>SOLUTION: A plurality of gate finger electrodes of a unit FET are put together to form single cells 11, and the finger electrodes are arranged in parallel in a longitudinal direction of a chip. Source electrode wirings 13 attached with via hole 12 to which source finger electrodes 13a are connected, gate electrode wirings 14 to which gate finger electrodes 14a are connected, and drain electrode wirings 15 to which drain finger electrodes 15a are connected, are arranged between the cells 11 in consideration of symmetry and are connected to a drain bus line 16; and the gate electrode wirings are each similarly connected to a gate bus line 17. Since an interval between the cells is about the thickness of a substrate, the heat in the longitudinal direction which is insufficiently radiated in a conventional method can be effectively radiated to a lower heat sink while being diffused in a laterally longitudinal direction. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a cell arrangement method for a semiconductor device having a field effect transistor (FET) with high output and low thermal resistance.

  In order to increase the output of a conventional FET, the cell arrangement is often configured by arranging the operation regions in parallel in a horizontal line as shown in FIG. In a GaAsFET fabricated on a GaAs (gallium arsenide) substrate, the low thermal conductivity of the GaAs material itself is the biggest obstacle to thermal design. By reducing the thickness of the GaAs layer to about 30 μm, heat dissipation is ensured. This is the current situation.

  With the advent of SiC (silicon carbide) and GaN (gallium nitride), semiconductor materials that can replace GaAs, the power density is several times higher than that of conventional devices, and the heat generation density increases accordingly. ing. SiC has excellent physical properties such as a dielectric breakdown voltage and a thermal conductivity 10 times higher than GaAs. Therefore, compared with FETs of the same size, a power density of 10 times can be theoretically obtained by simply multiplying the operating voltage by 10 times.

All SiC and GaN instead of GaAs use SiC as a supporting substrate. As mentioned above, SiC has higher thermal conductivity than GaAs and has a value close to that of a metal material. Therefore, the heat dissipation of a semiconductor substrate, which is a problem with GaAs, is not governed by the thickness of the substrate. In order to efficiently dissipate heat on the SiC support substrate, the arrangement of the FET cell, which is the heat generation region, is important. Therefore, as shown in FIG. 8 or FIG. 9, it is difficult to effectively dissipate heat generated due to high power density because heat diffusion cannot be performed in the longitudinal direction of the chip in the configuration arranged in a horizontal line. As a method of improving heat dissipation in the method of arranging in a horizontal line, the back surface of the heat generating area is processed thinly, and the drain or source electrode of the upper layer of the heat generating part is wide at the central part and narrow at the peripheral part, and further striped for heat dissipation There is something that forms. However, it does not fundamentally solve the heat generation due to the complicated design and high power density.
JP-A-11-87367

  Accordingly, the present invention has been made in view of the above, and an object of the present invention is to prevent the heat resistance from increasing due to the concentrated arrangement of the heat generation regions, and to increase the heat generation region without increasing the chip area. And a cell arrangement of a semiconductor device without sacrificing high-frequency characteristics.

  In order to solve the above-described problem, according to one aspect of the present invention, in a field effect transistor in which a gate electrode, a source electrode, and a drain electrode have a plurality of fingers, a cell in which the plurality of fingers are collected for each predetermined number is provided. There is provided a cell arrangement method for a semiconductor device, wherein a plurality of arrangements are provided, and a gap of about the substrate thickness is provided in the inter-cell arrangement.

  Further, according to one aspect of the present invention, in the field effect transistor in which the gate electrode, the source electrode, and the drain electrode have a plurality of fingers, and a via hole is provided in the source finger, the plurality of fingers are provided for each predetermined number. A cell arrangement method for a semiconductor device can be provided, wherein a plurality of cells arranged in (1) are arranged, and the inter-cell arrangement is arranged with a gap of about the substrate thickness.

  According to the present invention, the heat generation region can be dispersed by arranging the finger direction of the FET cell parallel to the chip longitudinal direction, and arranging the gap between the cell arrangement with a thickness of about the substrate thickness. It can be reduced by 20% or more. In addition, since the electrode wiring or the pad electrode can be disposed in the gap generated to disperse the heat generation region, an increase in the chip area can be avoided. Dispersing and arranging such cells may cause a phase difference in signal propagation. However, the wiring length to the cells should be equal, or the wiring should be wired symmetrically with respect to the bonding pad by wire bonding or the like. By doing so, it is possible to avoid the occurrence of a phase difference, so that high frequency characteristics are not sacrificed.

  Hereinafter, embodiments of the present invention will be described in detail. FIG. 1 is a conceptual diagram of a high-power FET semiconductor chip according to the first embodiment of the present invention. First, six cells of unit FETs having a gate finger electrode having a length of 100 μm are combined into one cell 11. The size of the cell 11 is 100 μm × 120 μm. In the cell 11, four source finger electrodes 13 a are connected in a comb shape to a source electrode wiring 13 with a via hole 12, and in the cell electrode 14, six gate finger electrodes 14 a are connected in a comb shape. Furthermore, the drain electrode electrode 15a is connected to the drain electrode wiring 15 in a comb shape.

  In the conventional structure, as shown in FIG. 8, twelve cells 11 are connected in parallel to form an operation region length of 120 μm × 12 = 1440 μm. In the first embodiment of the present invention, finger electrodes are arranged in parallel to the longitudinal direction of the semiconductor chip in the cell 11. When considering the same chip size as the conventional example, two cells can be arranged vertically and six cells can be arranged horizontally, and as a result, a gap can be formed between the cells 11 in the longitudinal direction. In view of symmetry, the source electrode wiring 13 with via holes 12 connected to the source finger electrode 13a, the gate electrode wiring 14 connected to the gate finger electrode 14a, and the drain electrode wiring 15 connected to the drain finger electrode 15a are formed in the gap. It has a structure arranged. Each drain electrode wiring 15 is connected to a drain bus line 16, and similarly each gate electrode wiring 14 is connected to a gate bus line 17.

  By arranging each cell 11 in the longitudinal direction, the gap between the cells is 144 μm, which is slightly larger than the substrate thickness of about 100 μm. As long as the heat radiation in the longitudinal direction, which has not been sufficiently achieved in the past, can be made about the thickness of the substrate connected to the heat sink material, the heat is effectively radiated to the lower heat sink while diffusing in the longitudinal and lateral directions. The chip shown in FIG. 8 and the chip according to the first embodiment of the present invention in which the chip size and the active region area are equally arranged are both mounted with AuSn (gold tin) on a package having a copper base of 1.2 mm thickness. When the thermal resistance was calculated under the same condition that this package was mounted on an aluminum heat sink having a thickness of 5 mm or more, the thermal resistance was reduced by about 20% in the first embodiment compared to the conventional example. It was planned.

  The effect of 2nd Embodiment is demonstrated using FIG. FIGS. 3A and 3B are diagrams showing bonding methods to pads in the first and second embodiments, respectively. The bonding wire 32 is connected to the drain bus line 33, and the drain bus line 33 is connected to the drain electrode wiring 34. For this reason, the wiring length becomes longer as the finger electrode is further away from the drain bus line 33. The difference in wiring length generated here cannot be ignored depending on the frequency used.

  In the second embodiment, the bonding wire 32 is directly connected to the center of the drain electrode wiring 34 to reduce the wiring length difference. By using such wiring, the drain output phases of the finger electrodes in each cell can be made to coincide with each other.

  FIG. 4 shows a conceptual diagram of a high-power FET semiconductor chip in which a via hole is formed in the source finger electrode in the third embodiment of the present invention. It is known that the heat dissipation effect is enhanced by forming the via hole 41 in the source finger electrode 13a. First, as in the first and second embodiments, unit FETs each having a finger electrode having a length of 100 μm are grouped into six cells to form one cell. The size of the cell 42 is 100 μm × 170 μm because the via hole 41 is provided in the source finger and the size of the cell is increased. In the conventional structure, as shown in FIG. 9, twelve cells 42 are connected in parallel to form an operation region length of 170 μm × 12 = 2040 μm. In the third embodiment of the present invention, finger electrodes are arranged in parallel with the longitudinal direction of the semiconductor chip in the cell 42. Considering the same chip size as in the conventional example, if one cell is arranged vertically and twelve cells are arranged horizontally, a gap can be formed between the cells 42 in the longitudinal direction, and the drain electrode wiring 43 is formed in the gap. And the gate wiring electrodes 44 are alternately arranged. Each drain electrode wiring 43 is connected to a drain bus line 45, and each gate electrode wiring 44 is connected to a gate bus line 46.

  By arranging each cell 42 in the longitudinal direction, the gap between the cells is 70 μm, which is about the same although it is smaller than the substrate thickness of about 100 μm. A chip having the same chip size and active region area as shown in FIG. 9 was bonded to a package having a copper die mount of 1.2 mm thickness for both the conventional and third embodiments with AuSn (gold tin). When the thermal resistance was calculated under the same condition that the package was mounted on an aluminum heat sink having a thickness of 5 mm or more, the thermal resistance was reduced by about 20% in the third embodiment compared to the conventional example. It was.

  FIG. 5 is a conceptual diagram of a high-power FET semiconductor chip according to the fourth embodiment of the present invention. The basic cell arrangement is the same as in FIG. 4, but the connection of the drain electrode wiring 43 to the drain bus line 45 is eliminated, the drain electrode wiring 51 is used as a bonding pad, and a bonding wire is directly connected thereto. . For this reason, if the bonding wire lengths are equal, the occurrence of a signal output phase difference can be reduced.

  FIG. 6 is a conceptual diagram of a high-power FET semiconductor chip according to the fifth embodiment of the present invention. The basic cell arrangement is the same as in FIG. 4 except that the gate bus line 46 is eliminated, the gate electrode wiring 44 is used as a gate electrode pad 61, and the area is enlarged to connect a bonding wire directly thereto. ing. Thereby, generation | occurrence | production of the phase difference of a signal input can be reduced.

  FIG. 7 is a conceptual diagram of a high-power FET semiconductor chip according to the sixth embodiment of the present invention. The basic cell arrangement is the same as that in FIG. 4, but the gate bus line 46 is eliminated and the area is enlarged in order to use the gate electrode wiring 71 as a gate electrode pad. The drain bus line 43 is also eliminated, and the drain electrode wiring 72 is used as a drain pad.

  By connecting a bonding wire to the center of the gate electrode wiring 71 and the drain electrode wiring 72, the occurrence of signal input / output phase differences and output signal phase differences can be reduced.

  As described above, according to the cell arrangement method of the semiconductor device according to the embodiment of the present invention configured as described above, the cell finger direction is arranged parallel to the chip longitudinal direction, and the substrate thickness is between the cell arrangements. By disposing the gaps at a certain degree, the heat generating area can be dispersed, and the thermal resistance can be reduced by 20% or more. In addition, since the electrode wiring or the pad electrode can be disposed in the gap generated to disperse the heat generation region, an increase in the chip area can be avoided. Dispersing and arranging such cells causes a phase difference in signal propagation. However, a phase difference is caused by equalizing the wiring length to the cells or by wiring by wire bonding at the center of the bonding pad. Since this can be avoided, the high frequency characteristics are not sacrificed.

  The present invention is not limited to the above-described embodiment as it is, and can be embodied without departing from the spirit of the invention at the stage of implementation. Although an example was calculated using an SiC substrate as an example, heat dispersion by cell arrangement and phase difference reduction by wire bonding can also be applied to FETs such as GaAs.

1 is a conceptual diagram of a semiconductor chip in a first embodiment of the present invention. It is a conceptual diagram of the semiconductor chip in the 2nd Embodiment of this invention. The figure shown about the bonding method to the package in the 1st and 2nd embodiment of this invention. It is a conceptual diagram of the semiconductor chip in the 3rd Embodiment of this invention. It is a conceptual diagram of the semiconductor chip in the 4th Embodiment of this invention. It is a conceptual diagram of the semiconductor chip in the 5th Embodiment of this invention. It is a conceptual diagram of the semiconductor chip in the 6th Embodiment of this invention. It is a conceptual diagram of the conventional semiconductor chip used for the comparison with 1st Embodiment. It is a conceptual diagram of the conventional semiconductor chip used for the comparison with 3rd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11, 42 ... Cell 12, 41 ... Via hole 13 ... Source electrode wiring 13a ... Source finger electrode 14, 44 ... Gate electrode wiring 14a ... Gate finger electrode 15, 22, 34, 43, 51, 72 ... Drain electrode wiring 15a ... Drain finger electrode
16, 33, 45 ... Drain bus lines 17, 31, 46 ... Gate bus lines 32 ... Bonding wires 61, 71 ... Gate pads

Claims (8)

  In a field effect transistor in which a gate electrode, a source electrode, and a drain electrode have a plurality of fingers, a plurality of cells in which the plurality of fingers are combined for each predetermined number are arranged, and a gap of about the substrate thickness is provided between the cells. A method of arranging a cell of a semiconductor device, comprising arranging the cells.   In a field effect transistor in which a gate electrode, a source electrode, and a drain electrode have a plurality of fingers, and a via hole is provided in the source finger, a plurality of cells in which the plurality of fingers are collected for each predetermined number are arranged, and the cell A cell arrangement method for a semiconductor device, characterized in that a gap of about a substrate thickness is provided in the interposition.   A drain in which the finger direction of the cell is arranged parallel to the chip longitudinal direction, a source electrode wiring or a drain electrode wiring in which a via hole is formed in a gap generated by the cell arrangement, and the drain electrode wirings are connected to each other 2. The cell arrangement method for a semiconductor device according to claim 1, wherein a bus line is arranged.   The finger direction of the cell is arranged parallel to the chip longitudinal direction, a source electrode wiring or a drain electrode wiring in which a via hole is formed in a gap generated by the cell arrangement is arranged, and the drain electrode wiring is used as a wire bonding pad. 2. The semiconductor device cell arrangement according to claim 1, wherein:   The gate bus line and the drain electrode in which the finger direction of the cell is arranged parallel to the chip longitudinal direction, the gate electrode wiring or the drain electrode wiring is arranged in the gap generated by the cell arrangement, and the gate electrode wirings are connected to each other 3. The cell arrangement method for a semiconductor device according to claim 2, wherein a drain bus line connecting the wirings is arranged.   The finger direction of the cell is arranged parallel to the chip longitudinal direction, the gate electrode wiring or the drain electrode wiring is arranged in the gap generated by the cell arrangement, and the gate bus line connecting the gate electrode wirings is arranged, 3. The method of claim 2, wherein the drain electrode wiring is a wire bonding pad.   The finger direction of the cell is arranged parallel to the chip longitudinal direction, a gate electrode wiring or a drain electrode wiring is arranged in a gap generated by the cell arrangement, and the gate electrode wiring is used as a wire bonding pad, and the drain electrode wirings are 3. The cell arrangement method for a semiconductor device according to claim 2, wherein a drain bus line connected to the semiconductor device is arranged.   The finger direction of the cell is arranged parallel to the chip longitudinal direction, the gate electrode wiring or the drain electrode wiring is arranged in the gap generated by the cell arrangement, and the gate electrode wiring and the drain electrode wiring are used as wire bonding pads. 3. A method of arranging a cell in a semiconductor device according to claim 2, wherein: