JP2012084915A - Field-effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a field-effect transistor in which thermal resistance is prevented from increasing due to concentrated arrangement of heat generation regions, and the heat generation regions are distributed without increasing the chip area.SOLUTION: In the field-effect transistor, a plurality of gate finger electrodes of unit FETs are collected as one cell 11, and the finger electrodes are arranged in parallel in the longitudinal direction of a chip. In the gap between each cell 11, source electrode wiring 13 with a via hole 12 connected with a source finger electrode 13a, and a gate electrode wiring 14 connected with a gate finger electrode 14a are arranged in view of the symmetry. Each gate electrode wiring 14 is connected with a gate bus line 17.

Description

  Embodiments described herein relate generally to a semiconductor device, and more particularly, to a field effect transistor (FET) having high output and low thermal resistance.

  In order to increase the output of a conventional FET, the cell arrangement is often configured by arranging the operation areas in parallel in a horizontal line as shown in FIG. 8 or FIG. In a GaAsFET fabricated on a GaAs (gallium arsenide) substrate, the low thermal conductivity of the GaAs material itself is the biggest obstacle to thermal design, and heat dissipation is ensured by reducing the thickness of the GaAs layer to about 30 μm. This is the current situation.

  With the advent of SiC (silicon carbide) and GaN (gallium nitride), which are semiconductor materials that replace GaAs, the power density is several times that of conventional devices, and the heat generation density increases accordingly. ing. SiC has excellent physical properties that its dielectric breakdown voltage and thermal conductivity are 10 times higher than GaAs. Therefore, compared with FETs of the same size, a power density of 10 times can be theoretically obtained by simply multiplying the operating voltage by 10 times.

  All SiC and GaN instead of GaAs use SiC as a supporting substrate. As described above, SiC has a higher thermal conductivity than GaAs and has a value close to that of a metal material. Therefore, the heat dissipation of a semiconductor substrate, which is a problem with GaAs or the like, is not regulated by its substrate thickness, and has a high power density. In order to efficiently dissipate heat on the SiC support substrate, it is important to arrange the FET cell that is a heat generating region. Therefore, as shown in FIG. 8 or FIG. 9, it is difficult to effectively dissipate heat generated due to high power density because heat diffusion cannot be performed in the longitudinal direction of the chip in the configuration arranged in a horizontal line. As a method of improving heat dissipation in the method of arranging in a horizontal line, the back surface of the heat generating area is processed thinly, and the drain or source electrode of the upper layer of the heat generating part is wide at the central part and narrow at the peripheral part, and further striped for heat dissipation There is something that forms. However, it does not fundamentally solve the heat generation due to the complicated design and high power density.

JP-A-11-87367

  Therefore, the present embodiment has been made in view of the above, and an object of the present embodiment is to prevent the heat resistance from increasing due to the concentrated arrangement of the heat generating regions, and to generate heat without increasing the chip area. Provided is a field effect transistor in which regions are dispersed and high frequency characteristics are not sacrificed.

  In order to solve the above problems, according to one aspect of the present embodiment, a field effect transistor in which a plurality of gate finger electrodes, a plurality of source finger electrodes, and a plurality of drain finger electrodes are formed on a substrate, A plurality of gate finger electrodes, the plurality of source finger electrodes, and the plurality of drain finger electrodes are grouped in a predetermined number, and each of the gate finger electrodes, the source finger electrodes, and the drain finger electrodes are arranged in the chip longitudinal direction. A plurality of cells arranged parallel to each other and provided with gaps between each other, and a plurality of the plurality of source finger electrodes arranged alternately in the plurality of gaps between these cells. Source electrode wiring and the plurality of gate finger electrodes are connected to each other. A plurality of gate electrode wirings, via holes provided in the plurality of source electrode wirings, and gate bus lines provided on the substrate and connecting the plurality of gate electrode wirings, The source electrode wiring connects the plurality of source finger electrodes in the cells on both sides, and each gate electrode wiring connects the plurality of gate finger electrodes in the cells on both sides. A field effect transistor is provided.

1 is a conceptual diagram of a semiconductor chip in a first embodiment. It is a conceptual diagram of the semiconductor chip in 2nd Embodiment. The figure shown about the bonding method to the package in 1st and 2nd embodiment. It is a conceptual diagram of the semiconductor chip in 3rd Embodiment. It is a conceptual diagram of the semiconductor chip in 4th Embodiment. It is a conceptual diagram of the semiconductor chip in 5th Embodiment. It is a conceptual diagram of the semiconductor chip in 6th Embodiment. It is a conceptual diagram of the conventional semiconductor chip used for the comparison with 1st Embodiment. It is a conceptual diagram of the conventional semiconductor chip used for the comparison with 3rd Embodiment.

  Hereinafter, embodiments will be described in detail. FIG. 1 is a conceptual diagram of a high-power FET semiconductor chip according to the first embodiment. First, six cells of unit FETs having a gate finger electrode having a length of 100 μm are combined into one cell 11. The size of the cell 11 is 100 μm × 120 μm. In the cell 11, four source finger electrodes 13 a are connected in a comb shape to a source electrode wiring 13 with a via hole 12, and in the cell electrode 14, six gate finger electrodes 14 a are connected in a comb shape. Furthermore, the drain electrode electrode 15a is connected to the drain electrode wiring 15 in a comb shape.

  In the conventional structure, as shown in FIG. 8, twelve cells 11 are connected in parallel to form an operation region length of 120 μm × 12 = 1440 μm. In the first embodiment, finger electrodes are arranged in parallel with the longitudinal direction of the semiconductor chip in the cell 11. When considering the same chip size as the conventional example, two cells can be arranged vertically and six cells can be arranged horizontally, and as a result, a gap can be formed between the cells 11 in the longitudinal direction. In view of symmetry, the source electrode wiring 13 with via holes 12 connected to the source finger electrode 13a, the gate electrode wiring 14 connected to the gate finger electrode 14a, and the drain electrode wiring 15 connected to the drain finger electrode 15a are formed in the gap. It has a structure arranged. Each drain electrode wiring 15 is connected to a drain bus line 16, and similarly each gate electrode wiring 14 is connected to a gate bus line 17.

  By arranging each cell 11 in the longitudinal direction, the gap between the cells is 144 μm, which is slightly larger than the substrate thickness of about 100 μm but about the same. As long as the heat radiation in the longitudinal direction, which has not been sufficiently achieved in the past, can be made about the thickness of the substrate connected to the heat sink material, the heat is effectively radiated to the lower heat sink while diffusing in the longitudinal and lateral directions. The chip shown in FIG. 8 and the chip according to the first embodiment of the present invention in which the chip size and the active region area are equally arranged are both mounted with AuSn (gold tin) on a package having a copper base of 1.2 mm thickness. When the thermal resistance was calculated under the same condition that the package was mounted on an aluminum heat sink having a thickness of 5 mm or more, the thermal resistance was reduced by about 20% in the first embodiment compared to the conventional example. It was planned.

  The effect of 2nd Embodiment is demonstrated using FIG. FIGS. 3A and 3B are diagrams showing bonding methods to pads in the first and second embodiments, respectively. The bonding wire 32 is connected to the drain bus line 33, and the drain bus line 33 is connected to the drain electrode wiring 34. For this reason, the wiring length becomes longer as the finger electrode is further away from the drain bus line 33. The difference in wiring length generated here cannot be ignored depending on the frequency used.

  In the second embodiment, the bonding wire 32 is directly connected to the center of the drain electrode wiring 34 to reduce the wiring length difference. By using such wiring, the drain output phases of the finger electrodes in each cell can be made to coincide with each other.

  FIG. 4 is a conceptual diagram of a high-power FET semiconductor chip in which a via hole is formed in the source finger electrode in the third embodiment. It is known that the heat dissipation effect is enhanced by forming the via hole 41 in the source finger electrode 13a. First, as in the first and second embodiments, unit FETs each having a finger electrode having a length of 100 μm are grouped together with six gate finger electrodes to form one cell 42. The size of the cell 42 is 100 μm × 170 μm because the via hole 41 is provided in the source finger and the size of the cell is increased. In the conventional structure, as shown in FIG. 9, twelve cells 42 are connected in parallel to form an operating region length of 170 μm × 12 = 2040 μm. In the third embodiment, the cell 42 has finger electrodes arranged in parallel in the longitudinal direction of the semiconductor chip. Considering the same chip size as in the conventional example, if one cell is arranged vertically and twelve cells are arranged horizontally, a gap can be formed between the cells 42 in the longitudinal direction, and the drain electrode wiring 43 is formed in the gap. And the gate wiring electrodes 44 are alternately arranged. Each drain electrode wiring 43 is connected to a drain bus line 45, and each gate electrode wiring 44 is connected to a gate bus line 46.

  By arranging each cell 42 in the longitudinal direction, the gap between the cells is 70 μm, which is about the same although it is smaller than the substrate thickness of about 100 μm. A chip having the same chip size and active region area as shown in FIG. 9 is bonded to a package having a copper die mount of 1.2 mm thickness for both the conventional and third embodiments with AuSn (gold tin). When the thermal resistance was calculated under the same condition that the package was mounted on an aluminum heat sink having a thickness of 5 mm or more, the thermal resistance was reduced by about 20% in the third embodiment compared to the conventional example. It was.

  FIG. 5 is a conceptual diagram of a high-power FET semiconductor chip according to the fourth embodiment. The basic cell arrangement is the same as in FIG. 4, but the connection of the drain electrode wiring 43 to the drain bus line 45 is eliminated, the drain electrode wiring 51 is used as a bonding pad, and a bonding wire is directly connected thereto. . For this reason, if the bonding wire lengths are equal, the occurrence of a signal output phase difference can be reduced.

  FIG. 6 is a conceptual diagram of a high-power FET semiconductor chip according to the fifth embodiment. The basic cell arrangement is the same as in FIG. 4 except that the gate bus line 46 is eliminated, the gate electrode wiring 44 is used as a gate electrode pad 61, and the area is enlarged to connect a bonding wire directly thereto. ing. Thereby, generation | occurrence | production of the phase difference of a signal input can be reduced.

  FIG. 7 is a conceptual diagram of a high-power FET semiconductor chip according to the sixth embodiment. The basic cell arrangement is the same as that in FIG. 4, but the gate bus line 46 is eliminated and the area is enlarged in order to use the gate electrode wiring 71 as a gate electrode pad. The drain bus line 43 is also eliminated, and the drain electrode wiring 72 is used as a drain pad.

  By connecting a bonding wire to the center of the gate electrode wiring 71 and the drain electrode wiring 72, the occurrence of signal input / output phase differences and output signal phase differences can be reduced.

  As described above, according to the field effect transistor according to the embodiment configured as described above, the cell finger direction is arranged parallel to the chip longitudinal direction, and a gap of about the substrate thickness is opened between the cell arrangements. By disposing, the heat generating region can be dispersed, and the thermal resistance can be reduced by 20% or more. In addition, since the electrode wiring or the pad electrode can be disposed in the gap generated to disperse the heat generation region, an increase in the chip area can be avoided. Dispersing and arranging such cells causes a phase difference in signal propagation. However, a phase difference is caused by equalizing the wiring length to the cells or by wiring by wire bonding at the center of the bonding pad. Since this can be avoided, the high frequency characteristics are not sacrificed.

  The present invention is not limited to the above-described embodiment as it is, and can be embodied without departing from the spirit of the invention at the stage of implementation. Although an example was calculated using an SiC substrate as an example, heat dispersion by cell arrangement and phase difference reduction by wire bonding can also be applied to FETs such as GaAs.

DESCRIPTION OF SYMBOLS 11, 42 ... Cell 12, 41 ... Via hole 13 ... Source electrode wiring 13a ... Source finger electrode 14, 44 ... Gate electrode wiring 14a ... Gate finger electrode 15, 22, 34, 43, 51, 72 ... Drain electrode wiring 15a ... Drain finger electrodes 16, 33, 45 ... Drain bus lines 17, 31, 46 ... Gate bus lines 32 ... Bonding wires 61, 71 ... Gate pads

Claims (3)

A field effect transistor in which a plurality of gate finger electrodes, a plurality of source finger electrodes, and a plurality of drain finger electrodes are formed on a substrate,
The plurality of gate finger electrodes, the plurality of source finger electrodes, and the plurality of drain finger electrodes are grouped in a predetermined number, and each of the gate finger electrodes, the source finger electrodes, and the drain finger electrodes are arranged in the chip longitudinal direction. A plurality of cells arranged in parallel with each other and provided with a gap about the substrate thickness of the substrate,
A plurality of source electrode wirings connected to the plurality of source finger electrodes and a plurality of gate electrode wirings connected to the plurality of gate finger electrodes, which are alternately arranged in the plurality of gaps between these cells,
Via holes respectively provided in the plurality of source electrode wirings;
A gate bus line provided on the substrate and connecting the plurality of gate electrode wirings;
Comprising
Each of the source electrode wirings connects the plurality of source finger electrodes in the cell on both sides,
Each of the gate electrode wirings connects the plurality of gate finger electrodes in the cell on both sides thereof. A drain electrode wiring disposed in each of the gaps where the plurality of gate electrode wirings are disposed, to which the plurality of drain finger electrodes are connected;
A drain bus line provided on the substrate and connecting the plurality of drain electrode wirings;
Further comprising
The field effect transistor according to claim 1, wherein each of the drain electrode wirings connects the plurality of drain finger electrodes in the cell on both sides thereof. A drain electrode wiring disposed in each of the gaps where the plurality of gate electrode wirings are disposed, to which the plurality of drain finger electrodes are connected;
2. The field effect transistor according to claim 1, wherein each of the drain electrode wirings is a wire bonding pad.

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