JP2007221933A - Charger for capacitor storage power supply - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a function equivalent to a power limiter function of a charger by a simple constitution and enable reduction in the power consumption of a parallel monitor and the size of a capacitor storage power supply. <P>SOLUTION: A charger for a capacitor storage power supply is configured to control a charging current for the capacitor storage power supply 7 that stores power in an electric double layer capacitor 71 and charge the power supply. This charger is provided with a signal generating means 2 that compares a current reference value for reducing a charging current I in inverse proportion to increase in the charging voltage Vc of the capacitor storage power supply 7 with the charging current I, and generates an error amplification signal. Pulse width modulation is carried out from a charging power supply 5 by a pulse width modulation means 4. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a charging device for a capacitor storage power source configured to charge a capacitor storage power source that stores power in an electric double layer capacitor by performing pulse width modulation from a charging power source by pulse width modulation means to control a charging current.

In a high-voltage, large-capacity storage power supply device configured by connecting a plurality of electric double layer capacitors in series, the terminal voltage varies greatly depending on the amount of charge / discharge. Therefore, when performing constant voltage charging such as a secondary battery, the efficiency is low, and a large charging current flows in the initial stage of charging, which may cause a problem with current resistance. Realizes charging. In addition, in an electricity storage power source composed of an electric double layer capacitor, in order to solve the problem due to the variation between capacitors connected in series, each electric double layer capacitor is bypassed with a predetermined reference voltage and a terminal voltage (charging voltage) is bypassed. Limited parallel monitors are connected. The parallel monitor limits the charging voltage to a predetermined value (within the withstand voltage range) by bypassing the charging current at a predetermined reference voltage, and reduces the variation in the charging voltage. If the parallel monitor of each electric double layer capacitor is bypassed in sequence, the power loss in the parallel monitor increases, and the parallel monitor has a current withstand upper limit value, avoiding bypass operation for a long time with a large current. It is necessary. In addition, in order to reduce wasteful power loss in the charging device, when the charging voltage of the entire power storage device by constant current charging exceeds a predetermined value, the charging current is decreased and constant power is obtained as the charging voltage increases. Thus, a power limiter function for switching to constant power charging is required (see, for example, Non-Patent Document 1, Patent Documents 1 and 2).
Okamura Ikuo, “Electric Double Layer Capacitor and Power Storage System”, Nikkan Kogyo Shimbun, September 30, 2005, 3rd edition, 1st edition, pages 134-139 Japanese Patent No. 2894444 Japanese Patent No. 3306325

  However, when the charge voltage exceeds a predetermined value as described above, when the power limiter function for switching to constant power charge so as to reduce the charge current as the charge voltage increases and to maintain a constant power is generally used, A power value is calculated by inputting a value and a current value, and control is performed using the calculation result. -Several hundreds A, hundreds to several kV, and the voltage varies in a wide range from near 0 V to the full charge voltage, so such a multiplier is expensive and requires adjustment. There is. As a result, the cost of the apparatus increases as the cost of the parts increases.

  The present invention solves the above-described problem, and realizes a function corresponding to the power limiter function of the charging device with a simple configuration, enabling reduction in power consumption of the parallel monitor and reduction of the capacity of the capacitor storage power source. It is.

  Therefore, the present invention provides a charging device for a capacitor storage power source configured to charge a capacitor storage power source that stores power in an electric double layer capacitor by performing pulse width modulation from a charging power source by pulse width modulation means to control a charging current. And a signal generating means for generating an error amplification signal by comparing the charging current with a current reference value for reducing the charging current in inverse proportion to the increase in the charging voltage of the capacitor storage power source.

  Further, the current reference value is generated by inverting the charging voltage of the capacitor storage power source and making it positive by an offset value, and the current reference value is generated by connecting the capacitor storage power source through a resistor to the inverting input terminal of the operational amplifier. A charge voltage detection signal is input, an offset value is input to a non-inverting input terminal, and a resistor is connected between the inverting input terminal and the output terminal. The error amplification signal is input to the pulse width modulation means through the error amplification signal of the constant current signal generation means for controlling the charging current to be constant and the OR logic circuit, and bypasses the charging current with a predetermined voltage to the electric double layer capacitor. A parallel monitor, and a switch circuit between the signal generating means and the OR logic circuit, and the switch according to a bypass operation signal of the parallel monitor. Controls switch circuit, characterized by being configured to control the validity / invalidity of the error amplification signal.

  According to the present invention, since the reference value that is inversely proportional to the increase in the charging voltage of the capacitor storage power source is generated, the reference value can be generated with a simple circuit configuration, and the circuit that controls the charging current based on this reference value And a constant-current charging circuit that controls the charging current to be constant, so that when the charging voltage of the capacitor storage power supply is charged to a predetermined value by constant-current charging, the charging current is inversely proportional to the increase in charging voltage. Can be realized with a simple circuit configuration. Therefore, it is possible to realize a charging device that switches from a constant current charging mode to a charging mode equivalent to constant power charging without using an expensive multiplier, and simple adjustment that only adjusts the reference value setting. Thus, it is possible to set the switching point, and it is possible to significantly reduce the cost of the parts and the apparatus.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing an embodiment of a charging device for a capacitor storage power source according to the present invention, and FIG. 2 is a diagram for explaining current diminishing charging (VI control). In the figure, 1 is a constant current signal generating circuit, 2 is a current decreasing signal generating circuit, 3 is a constant voltage signal generating circuit, 4 is a PWM control circuit, 5 is a charging power supply, 6 is a charging device, 7 is a capacitor storage power supply, D11 D21 and D31 are diodes, R is a current detection resistor, Vrefi is a current reference value setting circuit, Vrefv is a voltage reference value setting circuit, Voff-set is an offset value setting circuit, I is a charging current, and Vc is a charging voltage. .

  The capacitor storage power supply charging device according to the present embodiment shown in FIG. 1 charges and stores a capacitor storage power supply 7 in which a plurality of electric double layer capacitors are connected in series from the charging power supply 5 through the charging device 6. Each of the plurality of electric double layer capacitors constituting the capacitor storage power source 7 may be connected in parallel with a so-called parallel monitor that bypasses the charging current when the charging voltage increases to a predetermined reference voltage, for example. When charging, even if the charging voltage of each electric double layer capacitor is charged unevenly, by performing bypass operation sequentially from the parallel monitor of the electric double layer capacitor charged to a predetermined reference voltage, Bypassing the current, the charging voltage is limited to a predetermined reference voltage. Therefore, finally, when the full charge voltage of the electric double layer capacitor is set as a predetermined reference voltage, each electric double layer capacitor can be evenly charged to the full charge voltage.

  When a parallel monitor of an electric double layer capacitor charged to a predetermined reference voltage bypasses the charging current, the parallel monitor uses a power that is the product of the predetermined reference voltage and the charging current, that is, the voltage and current at the time of bypass. Is consumed. As a result, the longer the operation time of the parallel monitor and the greater the number, the greater the power loss and heat loss of the capacitor storage power supply 7. As a result, the parallel monitor has to be increased in capacity and structurally large in order to increase heat dissipation efficiency, and waste of power and waste of space are large, and it is difficult to realize downsizing of the capacitor storage power source 7. Therefore, in the charging device 6 according to the present embodiment, the initial stage in which any one of the plurality of electric double layer capacitors operates in parallel is determined based on the charging voltage of the capacitor storage power supply 7, and inversely proportional to the increase in the charging voltage. By reducing the charging current, the capacity and size of the parallel monitor can be reduced.

  The charging device 6 detects the charging current I and compares it with a predetermined current reference value Vrefi set by the current reference value setting circuit. The charging device 6 has a capacitor up to a predetermined voltage so that the charging current I is constant (constant current charging). When the power storage power supply 7 is charged, PWM (Pulse Width Modulation) control is performed so that the charging current is gradually decreased (current diminishing control: V-I control) in inverse proportion to the increase in the charging voltage. For example, the PWM control circuit 4, the constant current signal generation circuit 1, the current diminishing signal generation circuit 2, the constant voltage signal generation circuit 3, and error amplification signals from these signal generation circuits are supplied to the PWM control circuit 4 as specific configurations for that purpose. An OR logic circuit including diodes D11, D21, and D31 for selection switching input is provided.

  The constant current signal generating circuit 1 takes out the voltage drop between the terminals of the current detection resistor R inserted and connected in series with the charging circuit as a detection signal of the charging current I, and inputs this as a control object, as a reference value for the comparator Compared with the current reference value Vrefi set by the current reference value setting circuit, the error amplification circuit is configured to output the error amplification signal. Therefore, the error amplification signal output from the constant current signal generation circuit 1 has a larger output value if the input charging current I to be controlled is smaller than the current reference value Vrefi, and the charging current I is larger than the current reference value Vrefi. The output value becomes smaller. When this error amplification signal is input, the PWM control circuit 4 increases the charging current I when the charging current I is smaller than the current reference value Vrefi, and conversely when the charging current I is larger than the current reference value Vrefi. Since the pulse width (duty ratio) is controlled according to the magnitude of the input error amplification signal so as to decrease the charging current, the charging current is controlled so that the charging current I becomes constant based on the current reference value Vrefi as a result. The constant current charging control mode CC is executed.

  In contrast to the constant current signal generating circuit 1, the current diminishing signal generating circuit 2 is a current reference value that decreases the charging current I in inverse proportion to the increase in the charging voltage Vc of the capacitor storage power source 7 as shown in FIG. Vref (vi) is generated, the current reference value Vref (vi) is compared with the charging current I to be controlled, and an error amplification signal is output. For example, as shown in FIG. 2A, the current reference value Vref (vi) is obtained by inverting the charging voltage Vc of the capacitor storage power source 7 (Vout = −Vin) and making it positive by the offset value Voff-set (= Voff− set-Vin). Therefore, when this error amplification signal is input, the PWM control circuit 4 increases the charging current I when the charging voltage Vc of the capacitor storage power supply 7 is small, and the charging voltage Vc of the capacitor storage power supply 7 increases and reverses the increase. A current diminishing control mode V-I is executed in which the charging current is controlled to decrease the charging current I in proportion.

  The constant voltage signal generation circuit 3 detects the charging voltage Vc of the capacitor storage power supply 7, inputs this as the charging voltage Vc to be controlled, and compares it with the voltage reference value Vrefv preset by the voltage reference value setting circuit. An error amplification circuit that outputs the error amplification signal is configured. Therefore, the error amplification signal output from the constant voltage signal generation circuit 3 has an output value that is larger if the input charging voltage Vc to be controlled is smaller than the voltage reference value Vrefv, and the charging voltage Vc is larger than the voltage reference value Vrefv. The output value becomes smaller. When this error amplification signal is input, the PWM control circuit 4 increases the charging current I when the charging voltage Vc is smaller than the voltage reference value Vrefv, and conversely, when the charging voltage Vc is larger than the voltage reference value Vrefv. The constant voltage charging control mode CV is executed to control the charging current so as to reduce the current.

  The diodes D11, D21, and D31 are connected to the input of the PWM control circuit 4 with opposite polarities from the constant current signal generation circuit 1, the current diminishing signal generation circuit 2, and the constant voltage signal generation circuit 3 that output error amplification signals, respectively. Therefore, the smallest error amplification signal among the error amplification signals output from the constant current signal generation circuit 1, the current diminishing signal generation circuit 2, and the constant voltage signal generation circuit 3 is input to the PWM control circuit 4. A logic circuit is configured. Next, charge mode switching control (CC → VI → CV) performed by the OR logic circuit will be described with reference to FIG.

  First, in the initial stage of starting charging, the constant current charging control mode CC is executed with the diode D11 turned on and the diodes D21 and D31 turned off. That is, when the charging voltage Vc of the capacitor storage power source 7 is small in the initial stage and the PWM control circuit 4 is executing the constant current charging control mode CC based on the error amplification signal output from the constant current signal generating circuit 1, In both the current diminishing signal generating circuit 2 and the constant voltage signal generating circuit 3, even if the control target is smaller than the reference value to be compared and outputs an error amplification signal having a large value, the charging current I is charged to the capacitor storage power source 7 as well. Since the voltage Vc does not increase and the error amplification signal is stuck to the upper limit value, the diodes D21 and D31 are biased in the reverse direction and turned off.

  Next, by continuing constant current charging, the charging voltage Vc of the capacitor storage power source 7 increases, and the current reference value Vref (vi) in the current diminishing signal generation circuit 2 gradually decreases, so that the current reference value Vref ( When vi) becomes smaller than the current reference value Vrefi of the constant current signal generation circuit 1, the error amplification signal output from the current diminishing signal generation circuit 2 becomes smaller than the error amplification signal output from the constant current signal generation circuit 1. From this point, the diode D11 connected to the output of the constant current signal generation circuit 1 is turned off, the diode D21 connected to the output of the current diminishing signal generation circuit 2 is turned on, and the charging voltage of the capacitor storage power supply 7 is switched on. A current diminishing control mode V-I is executed in which the charging current is controlled to decrease the charging current I in inverse proportion to the increase in Vc. In FIG. 2B, this switching point is represented by a point at which the charging voltage Vc of the capacitor storage power source 7 becomes Vst.

  Further, when the charging voltage Vc of the capacitor storage power supply 7 increases and becomes larger than the voltage reference value Vrefv in the constant voltage signal generation circuit 3, the error amplification signal output from the constant voltage signal generation circuit 3 is converted into a current diminishing signal generation circuit. 2 is smaller than the error amplification signal output from 2, the diode D21 connected to the output of the current diminishing signal generation circuit 2 is turned off, and the diode D31 connected to the output of the constant voltage signal generation circuit 3 is turned on. Instead, a constant voltage charging control mode CV is executed in which the charging current is controlled so that the charging voltage Vc is smaller than the voltage reference value Vrefv. In FIG. 2B, this switching point is represented by a point where the charging voltage Vc of the capacitor storage power source 7 becomes Vfu.

  Next, a specific configuration of the signal generation circuit will be described. 3 is a diagram showing an embodiment of a constant current signal generating circuit and a current decreasing signal generating circuit, FIG. 4 is a diagram showing another embodiment of the current decreasing signal generating circuit, and FIG. 5 is an embodiment of a reference value setting circuit. 11, 21 and 22 are operational amplifiers, 23 is a logic processing circuit, 71 is an electric double layer capacitor, 72 is a parallel monitor, AS, AS1 and AS1 ′ are analog switches, and C11, C21 and Cr1 are capacitors. , R11, R21, R22, R23, Rr1 are resistors, Rrv, Rrv ′ are variable resistors, and + V is a bias power source.

  In FIG. 3, the constant current signal generation circuit 1 inputs the detection signal of the charging current I to its inverting input terminal − and inputs the current reference value Vrefi to the non-inverting input terminal + in the operational amplifier 11, and inputs the inverting input. An error amplifying circuit is configured by connecting a series circuit of a capacitor C11 and a resistor R11 between the terminal-and the output terminal. Similarly, the current diminishing signal generating circuit 2 inputs the detection signal of the charging current I to the inverting input terminal − and inputs the current reference value Vref (vi) to the non-inverting input terminal + in the operational amplifier 21. An error amplifier circuit is configured by connecting a series circuit of a capacitor C21 and a resistor R21 between the inverting input terminal − and the output terminal.

  Also, the current reference value Vref (vi) is a value that is inversely proportional to the increase in the charging voltage Vc of the capacitor storage power supply 7 as described above. For example, in the operational amplifier 22 as shown in FIG. A detection signal of the charging voltage Vc of the capacitor storage power supply 7 is input to the inverting input terminal − via the resistor R22, an offset value Voff-set is input to the non-inverting input terminal +, and the inverting input terminal − and the output terminal A subtracting circuit is configured by connecting a resistor R23 between the two. According to this subtraction circuit, a current reference value Vref (vi) of Voff-set + (Voff-set−Vc) R23 / R22 (where R23 = R22 is 2Voff-set−Vc) is taken out and Voff− When set is set to a value that matches Vst in FIG. 2B, when the charging voltage Vc of the capacitor storage power supply 7 increases to Voff-set, the reference values of the constant current signal generation circuit 1 and the current diminishing signal generation circuit 2 are set. Since the values are equal to each other, the setting is switched from here to the current decreasing control mode.

  In the embodiment shown in FIG. 3, the charging current is reduced in inverse proportion to the signal from the constant current signal generation circuit 1 that controls the charging current so as to be constant and the increase in the charging voltage Vc of the capacitor storage power source 7. The operation of the parallel monitor connected to each electric double layer capacitor of the capacitor storage power source 7 is automatically switched by the OR logic circuit of the diodes D11 and D21. FIG. 4 shows an embodiment configured to switch the control mode on the condition of.

  In the embodiment shown in FIG. 4, an analog switch AS is inserted in series between the output of the operational amplifier 21 in the current diminishing signal generating circuit 2 and the diode D 21 of the OR logic circuit, and the analog switch is output by the output of the logic processing circuit 23. AS is controlled. Here, the logic processing circuit 23 performs logic processing on the operation signal of the parallel monitor 72 connected to each electric double layer capacitor 71 of the capacitor storage power source 7. The analog switch AS is turned on on condition that one parallel monitor 72 is turned on. In this case, in the subtraction circuit shown in FIG. 3B, the gradient of the current reference value Vref (v−i) may be changed by changing the ratio of R23 and R22. Thus, constant current charging is continued until any one parallel monitor 72 is turned on, and after any one parallel monitor 72 is turned on, charging is performed as shown in FIG. The current is reduced and the mode is switched to the current diminishing control mode VI. If the Vst point (offset value Voff-set) shown in FIG. 2 (b) is set to be smaller in this way, the charging voltage of each electric double layer capacitor 71 of the capacitor storage power source 7 has a large variation. When the charging voltage Vc of the capacitor storage power supply 7 is small and the first parallel monitor performs a bypass operation, the control mode is switched at the timing shown in FIG. 4B, the variation is small, and the charging voltage Vc of the capacitor storage power supply 7 is When the first parallel monitor is increased and the bypass operation is performed, the switching of the control mode can be extended to the timing shown in FIG. 4B to increase the charging efficiency. Alternatively, the logic processing circuit 23 may be configured to determine that the number of parallel monitors 72 turned on is a predetermined number and turn on the analog switch AS according to the condition.

  Each of the reference value setting circuits described above can be configured by various known circuits. For example, it can be configured as shown in FIG. That is, as shown in FIG. 5A, a stabilized bias power source + V is divided by a voltage dividing circuit of a fixed resistor Rr1 and a variable resistor Rrv, a reference value Vref is taken out from the voltage dividing connection point, and a variable resistor Rrv is obtained. To adjust to a predetermined voltage. The capacitor Cr1 is connected in parallel to the variable resistor Rrv as a noise countermeasure. Further, as shown in FIG. 5B, a similar circuit may be connected in parallel via the analog switch AS1, and the reference value may be switched by turning on / off the analog switch AS1. For switching the reference value, the variable resistor Rrv ′ may be connected in parallel with the variable resistor Rrv via the analog switch AS1 ′. When the reference value is switched by the analog switches AS1 and AS1 ′ in this way, for example, when this is adopted in the current reference value setting circuit Vrefi, the constant current charging value is stepwise according to a predetermined condition. Since the switching can be performed, the charging current for constant current charging can be switched according to the operation of the parallel monitor 72 by using the output signal of the logic processing circuit 23 described above as a switching signal.

  FIG. 6 is a diagram showing an embodiment of a charging device including a PWM-controlled switching converter, in which 61 is a control circuit, 62 is an error signal generation circuit, C1 and C2 are capacitors, D is a diode, L is a coil, R is a current detection resistor, SW1 and SW2 are switch circuits, I is a charging current, Vc is a charging voltage, and Vi is a power supply voltage.

  In the charging apparatus shown in FIG. 6A, a charging control switch circuit SW and a choke coil L are connected in series between a charging power source 5 and a capacitor storage power source 7, and a diode D is connected in parallel to these series connection points. A step-down switching converter that connects a synchronous rectifier circuit and connects capacitors C1 and C2 in parallel on the input side and output side, and turns on / off the switch circuit SW by a PWM signal to supply a charging current. In order to detect the charging current, a current detection resistor R is inserted and connected in series. In the charging device shown in FIG. 6B, a charging control choke coil L and a switch circuit SW2 are connected in series between the charging power source 5 and the capacitor storage power source 7, and in parallel with these series connection points. The switch circuit SW1 is connected, and capacitors C1 and C2 are connected in parallel to the input side and the output side. The switch circuit SW1 is turned on / off by a PWM signal, and the switch circuit SW2 is turned off / off as a synchronous rectifier circuit. A step-up type switching converter that is turned on to supply a charging current is provided, and a current detection resistor R is inserted and connected in series to detect the charging current. The PWM control circuit 61 supplies the PWM signal to the switch circuits SW, SW1, and SW2, and the error signal generation circuit 62 supplies the PWM control circuit 61 with the charging current I, the charging voltage Vc of the capacitor storage power source 7, the reference value, and the offset value. Based on the above, the error amplification signal described above is supplied.

  In addition, this invention is not limited to said embodiment, A various deformation | transformation is possible. For example, in the above embodiment, the control modes of constant current charging CC, current diminishing charge VI, and constant voltage charging CV are provided and switched under predetermined conditions. Only by having the control mode of V-I, it is possible to charge to full charge with the current diminishing charge V-I, or to stop charging at the full charge voltage. Further, the constant current signal generating circuit, the current diminishing signal generating circuit, etc. can be appropriately designed not only with the circuit shown in FIG. 3 but also with an equivalent alternative circuit. For the capacitor storage power source, each electric double layer capacitor is monitored in parallel. However, it goes without saying that it may be one without a parallel monitor.

It is a figure which shows embodiment of the charging device for capacitor electrical storage power supplies which concerns on this invention. It is a figure explaining electric current gradual charge (VI control). It is a figure which shows embodiment of a constant current signal generation circuit and a current decreasing signal generation circuit. It is a figure which shows other embodiment of a current decreasing signal generation circuit. It is a figure which shows embodiment of a reference value setting circuit. It is a figure which shows embodiment of the charging device provided with the switching converter by which PWM control is carried out.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Constant current signal generation circuit, 2 ... Current decreasing signal generation circuit, 3 ... Constant voltage signal generation circuit, 4 ... PWM control circuit, 5 ... Charging power supply, 6 ... Charging apparatus, 7 ... Capacitor storage power supply, D11, D21, D31 ... Diode, R ... Current detection resistor, Vrefi ... Current reference value setting circuit, Vrefv ... Voltage reference value setting circuit, Voff-set ... Offset value setting circuit, I ... Charging current, Vc ... Charging voltage

Claims (5)

In a charging device for a capacitor storage power source configured to perform charging by controlling a charging current by performing pulse width modulation by a pulse width modulation unit from a charging power source with respect to a capacitor storage power source storing power in an electric double layer capacitor,
A capacitor storage power supply comprising signal generation means for generating an error amplification signal by comparing a charge current with a current reference value for reducing a charge current in inverse proportion to an increase in the charge voltage of the capacitor storage power supply. Charging device. 2. The charging device for a capacitor storage power source according to claim 1, wherein the current reference value is generated by inverting the charging voltage of the capacitor storage power source and making it positive by an offset value. The current reference value is obtained by inputting a detection signal of the charging voltage of the capacitor storage power source through a resistor to the inverting input terminal of the operational amplifier, inputting an offset value to the non-inverting input terminal, and connecting the inverting input terminal and the output terminal. 2. The charging device for a capacitor storage power source according to claim 1, wherein the charging device is taken out from a subtracting circuit configured by connecting a resistor therebetween. 2. The error amplification signal of the signal generation means is input to the pulse width modulation means through an error amplification signal of an constant current signal generation means for controlling the charging current to be constant and an OR logic circuit. Charging device for capacitor storage power supply. The electric double layer capacitor is provided with a parallel monitor that bypasses a charging current at a predetermined voltage, and a switch circuit is provided between the signal generating means and the OR logic circuit, and the switch circuit according to a bypass operation signal of the parallel monitor. 5. The charging device for a capacitor storage power source according to claim 4, wherein the charging / discharging control unit controls the validity / invalidity of the error amplification signal.

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