JP2009100532A - Charger for capacitor storage power supplies - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To continuously charge a capacitor with a charging current slightly smaller than a charging current when it is fully charged. <P>SOLUTION: A capacitor storage power supply is so constructed that power is stored by series-connecting multiple electrical double layer capacitors bypassing a charging current with a predetermined voltage and having a parallel monitor outputting a full charge signal. A charger for capacitor storage power supplies is so constructed as to carry out pulse width modulation on charging power by a pulse width modulating means to control charging current and charge the capacitor storage power supply. A current reference value (Vref), which is one factor for the pulse width modulating means to determine a pulse width, is so controlled that it varies according to the frequency of an F signal, or the logical sum of full charge signals from the multiple parallel monitors. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a charging device for a capacitor storage power source that stores a plurality of electric double layer capacitors connected in series with a parallel monitor that bypasses a charging current at a predetermined voltage.

  In a high-voltage, large-capacity storage power supply device configured by connecting a plurality of electric double layer capacitors in series, the terminal voltage varies greatly depending on the amount of charge / discharge. Therefore, when performing constant voltage charging such as a secondary battery, the efficiency is low, and a large charging current flows in the initial stage of charging, which may cause a problem with current resistance. Realizes charging. In addition, in an electric storage power source composed of an electric double layer capacitor, in order to solve the problem due to the variation between individual capacitors connected in series, each electric double layer capacitor is bypassed with a predetermined reference voltage and a terminal voltage (charging voltage) is bypassed. ) Is connected to the parallel monitor.

The parallel monitor limits the charging voltage to a predetermined value (within the withstand voltage range) by bypassing the charging current at a predetermined reference voltage, and reduces the variation in the charging voltage. When the parallel monitor of each electric double layer capacitor sequentially performs a bypass operation, the power loss in the parallel monitor increases. Since the parallel monitor has a withstand current upper limit value, it is necessary to avoid a long-time bypass operation with a large current. (For example, refer nonpatent literature 1 and patent literature 1).
Ikuo Okamura “Electric Double Layer Capacitor and Power Storage System” March 31, 1999, first edition, first edition, published by Nikkan Kogyo Shimbun, pages 135, 145-159 Japanese Patent No. 3306325

  An outline of the parallel monitor as described above will be described. FIG. 7 is a diagram showing an outline of the circuit configuration of the parallel monitor. In FIG. 7, C is an electric double layer capacitor, CMP is a comparator, D is a diode, Tr is a transistor, and Vr is a set voltage. As an indispensable condition for configuring a power storage device by combining a plurality of large-capacity capacitors, there is a problem of equalization of burden voltage that occurs when capacitors are connected in series. The parallel monitor is connected between terminals of a plurality of capacitors connected in series constituting the power storage device, and has a comparator that compares the charging voltage of each capacitor with a set voltage. It is a voltage monitoring and control device that bypasses or detects a full charge and transmits a full charge signal, so that the maximum charge is possible within the withstand voltage range of the capacitor. For example, as shown in FIG. 7, the voltage of the capacitor C is monitored by comparing with the set voltage Vr by the comparator CMP. When the voltage of the capacitor C exceeds the set voltage Vr, the transistor Tr is turned on to bypass the charging current.

  A charging device for charging an electric double layer capacitor provided with a parallel monitor as described above in series will be described. FIG. 8 is a diagram schematically showing a charging device for a plurality of electric double layer capacitors provided with a parallel monitor. 8, C1, C2,... Cn are electric double layer capacitors connected in series, M1, M2,... Cn connected in parallel to the electric double layer capacitors C1, C2,. Mn represents a parallel monitor, and CH represents a charging device. The parallel monitors M1, M2,... Mn bypass the current applied to any one of the electric double layer capacitors C1, C2,. Then, the fact that the predetermined voltage value is reached is output to the charging device CH as a full charge signal.

  Since the parallel monitor has a rated current value (current resistance upper limit value), when any one of the electric double layer capacitors C1, C2,... Cn becomes a predetermined voltage value and starts to bypass the current, The charging device CH reduces the charging current to the withstand current value of the parallel monitor. The value is, for example, about several A, and is much smaller than the charging current, for example, about 10-60A. Since the full charge signal is output from the parallel monitor in accordance with the start of current bypass, the charging device CH reduces the charge current to the withstand current value of the parallel monitor when receiving the full charge signal.

  By the way, the electric double layer capacitor has an internal resistance component in addition to the capacitor component, and it is not known from the outside of the capacitor how much the component is present. FIG. 9 shows an equivalent circuit including the internal resistance component of the electric double layer capacitor. Since the capacitor has such an internal resistance component, even if the terminal voltage of the capacitor reaches the full charge voltage, it actually includes a voltage drop due to the internal resistance, and as described above, the charge current is tolerated. As soon as the current value is decreased (Vr decreases as the voltage drop decreases, Vr + Vc, which is the terminal voltage, does not reach the full charge voltage), the full charge signal is not output. It was. The voltage drop due to the internal resistance increases as the current value increases. If the charge current is reduced to the previous withstand voltage value according to the output of the full charge signal from the parallel monitor, the resistance of the parallel monitor is much smaller than the normal charge current for the capacitor that has reached the full charge voltage. It will be necessary to charge little by little at the current value.

  In order to quickly charge the electric double layer capacitor, the amount of current is increased. However, due to the problems described above, when charging with a large current, a capacitor that must be charged with a small current is used. As a result, there was a problem that the charging time could not be shortened due to the remaining capacity.

  The present invention solves the above-mentioned problem, and the invention according to claim 1 includes a plurality of electric double layer capacitors including a parallel monitor that bypasses a charging current at a predetermined voltage and outputs a full charge signal. In the capacitor storage power supply charging device configured to perform charging by controlling the charging current by performing pulse width modulation from the charge power supply by the pulse width modulation means to the capacitor storage power supply that is connected in series and stored, the pulse width modulation means The current reference value, which is one element that determines the pulse width in, is controlled so as to change according to the frequency of the F signal that is the logical sum of the full charge signals from the plurality of parallel monitors.

  According to a second aspect of the present invention, in the capacitor storage power supply charging device according to the first aspect, the current reference value is controlled so as to gradually decrease in accordance with the frequency of the F signal.

  According to a third aspect of the present invention, there is provided the capacitor storage power supply charging device according to the first or second aspect, wherein the signal generating means for generating an error amplification signal by comparing the current reference value with a charging current. It is characterized by providing.

  According to the present invention, with respect to a capacitor that has apparently reached a full charge voltage due to the internal resistance component of the capacitor, the capacitor is connected with a charging current that is slightly smaller than the charging current when the full charge is reached by gradually decreasing the current reference value. It becomes possible to continue charging, and the capacitor can be charged efficiently. Further, since it becomes possible to continue charging the capacitor with a charging current slightly smaller than the charging current when full charge is reached, charging is performed little by little with the withstand current value Is of the parallel monitor that is much smaller than the capacitor charging current. This can be avoided and the capacitor can be charged efficiently.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing an embodiment of a charging device for a capacitor storage power source according to the present invention, and FIG. 2 is a diagram for explaining current diminishing charging (VI control). In the figure, 1 is a constant current signal generating circuit, 2 is a current decreasing signal generating circuit, 3 is a constant voltage signal generating circuit, 4 is a PWM control circuit, 5 is a charging power supply, 6 is a charging device, 7 is a capacitor storage power supply, D11 , D21, D31 are diodes, R is a current detection resistor, Vrefi is a current reference value setting circuit, Vrefv is a voltage reference value setting circuit, Voff-set is an offset value setting circuit, I is a charging current, Vc is a charging voltage, PM1 Thru | or PMn show a parallel monitor.

  The capacitor storage power supply charging device according to the present embodiment shown in FIG. 1 charges and stores a capacitor storage power supply 7 in which a plurality of electric double layer capacitors are connected in series from the charging power supply 5 through the charging device 6. Each of the plurality of electric double layer capacitors constituting the capacitor storage power source 7 is connected in parallel with so-called parallel monitors PM1 to PMn that bypass the charging current when the charging voltage increases to a predetermined reference voltage. When charging, even if the charging voltage of each electric double layer capacitor is charged unevenly, by performing bypass operation sequentially from the parallel monitor of the electric double layer capacitor charged to a predetermined reference voltage, Bypassing the current, the charging voltage is limited to a predetermined reference voltage. Therefore, finally, when the full charge voltage of the electric double layer capacitor is set as a predetermined reference voltage, each electric double layer capacitor can be evenly charged to the full charge voltage.

  When the parallel monitors PM1 to PMn of the electric double layer capacitors charged to a predetermined reference voltage bypass the charging current, the parallel monitor calculates the product of the predetermined reference voltage and the charging current, that is, the voltage and the current when bypassing. The power consisting of is consumed by heat. As a result, the longer the operation time of the parallel monitor and the greater the number, the greater the power loss and heat loss of the capacitor storage power supply 7. As a result, the parallel monitor has to be increased in capacity and structurally large in order to increase heat dissipation efficiency, and waste of power and waste of space are large, and it is difficult to realize downsizing of the capacitor storage power source 7. Therefore, in the charging device 5 according to the present embodiment, the initial stage in which any one of the plurality of electric double layer capacitors operates in parallel is determined based on the charging voltage of the capacitor storage power source 7, and is inversely proportional to the increase in the charging voltage. By reducing the charging current, the capacity and size of the parallel monitor can be reduced.

  Further, a full charge signal (see FIG. 7) is output from the parallel monitors PM1 to PMn of the electric double layer capacitors charged to a predetermined reference voltage. The full charge signals output from the electric double layer capacitors are logically summed and output as an F signal for the capacitor storage power supply 7 as a whole. Such an F signal is input to the current reference value setting circuit Vrefi and the offset value setting circuit Voff-set, and is used for setting the respective reference voltages.

  The charging device 5 detects the charging current I and compares it with a predetermined current reference value Vrefi set by the current reference value setting circuit, the charging current I becomes constant (constant current charging), and the capacitor storage power supply up to a predetermined voltage When 7 is charged, PWM (Pulse Width Modulation) control is performed so that the charging current is decreased in inverse proportion to the increase of the charging voltage (current decreasing control: V-I control). For example, the PWM control circuit 4, the constant current signal generation circuit 1, the current diminishing signal generation circuit 2, the constant voltage signal generation circuit 3, and error amplification signals from these signal generation circuits are supplied to the PWM control circuit 4 as specific configurations for that purpose. An OR logic circuit including diodes D11, D21, and D31 for selection switching input is provided.

  The constant current signal generating circuit 1 takes out the voltage drop between the terminals of the current detection resistor R inserted and connected in series with the charging circuit as a detection signal of the charging current I, and inputs this as a control object, as a reference value for the comparator Compared with the current reference value Vrefi set by the current reference value setting circuit, the error amplification circuit outputs an error amplification signal. Therefore, the error amplification signal output from the constant current signal generation circuit 1 has a larger output value if the input charging current I to be controlled is smaller than the current reference value Vrefi, and the charging current I is larger than the current reference value Vrefi. The output value becomes smaller. When this error amplification signal is input, the PWM control circuit 4 increases the charging current I when the charging current I is smaller than the current reference value Vrefi, and conversely when the charging current I is larger than the current reference value Vrefi. Since the pulse width (duty ratio) is controlled according to the magnitude of the input error amplification signal so as to decrease the charging current, the charging current is controlled so that the charging current I becomes constant based on the current reference value Vrefi as a result. The constant current charging control mode CC is executed.

  In contrast to the constant current signal generating circuit 1, the current diminishing signal generating circuit 2 is a current reference value that decreases the charging current I in inverse proportion to the increase in the charging voltage Vc of the capacitor storage power source 7 as shown in FIG. Vref (vi) is generated, the current reference value Vref (vi) is compared with the charging current I to be controlled, and an error amplification signal is output. For example, as shown in FIG. 2A, the current reference value Vref (vi) is inverted by charging the capacitor storage power supply 7 (Vout = −Vin), and is made positive by the offset value Voff−set (= Voff-set-Vin). Therefore, when this error amplification signal is input, the PWM control circuit 4 increases the charging current I when the charging voltage Vc of the capacitor storage power supply 7 is small, and the charging voltage Vc of the capacitor storage power supply 7 increases and reverses the increase. A current diminishing (V-I) control mode CP ′ is executed in which the charging current is controlled to decrease the charging current I in proportion.

  The constant voltage signal generation circuit 3 detects the charging voltage Vc of the capacitor storage power source 7, inputs this as the charging voltage Vc to be controlled, and compares it with the voltage reference value Vrefv preset by the voltage reference value setting circuit. An error amplification circuit that outputs the error amplification signal is configured. Therefore, the error amplification signal output from the constant voltage signal generation circuit 3 has an output value that is larger if the input charging voltage Vc to be controlled is smaller than the voltage reference value Vrefv, and the charging voltage Vc is larger than the voltage reference value Vrefv. The output value becomes smaller. When this error amplification signal is input, the PWM control circuit 4 increases the charging current I when the charging voltage Vc is smaller than the voltage reference value Vrefv, and conversely, when the charging voltage Vc is larger than the voltage reference value Vrefv. The constant voltage charging control mode CV is executed to control the charging current so as to reduce the current.

  The diodes D11, D21, and D31 are connected to the input of the PWM control circuit 4 with opposite polarities from the constant current signal generation circuit 1, the current diminishing signal generation circuit 2, and the constant voltage signal generation circuit 3 that output error amplification signals, respectively. Therefore, the smallest error amplification signal among the error amplification signals output from the constant current signal generation circuit 1, the current diminishing signal generation circuit 2, and the constant voltage signal generation circuit 3 is input to the PWM control circuit 4. A logic circuit is configured. Next, the charge mode switching control (CC → CP ′ → CV) performed by the OR logic circuit will be described with reference to FIG.

  First, in the initial stage of starting charging, the constant current charging control mode CC is executed with the diode D11 turned on and the diodes D21 and D31 turned off. That is, when the charging voltage Vc of the capacitor storage power source 7 is small in the initial stage and the PWM control circuit 4 is executing the constant current charging control mode CC based on the error amplification signal output from the constant current signal generating circuit 1, In both the current diminishing signal generating circuit 2 and the constant voltage signal generating circuit 3, even if the control target is smaller than the reference value to be compared and outputs an error amplification signal having a large value, the charging current I is charged to the capacitor storage power source 7 as well. Since the voltage Vc does not increase and the error amplification signal is stuck to the upper limit value, the diodes D21 and D31 are biased in the reverse direction and turned off.

  Next, by continuing constant current charging, the charging voltage Vc of the capacitor storage power source 7 increases, and the current reference value Vref (vi) in the current diminishing signal generation circuit 2 gradually decreases, so that the current reference value When Vref (v−i) becomes smaller than the current reference value Vrefi of the constant current signal generation circuit 1, the error amplification signal output from the current diminishing signal generation circuit 2 is more than the error amplification signal output from the constant current signal generation circuit 1. Get smaller. From this point, the diode D11 connected to the output of the constant current signal generation circuit 1 is turned off, the diode D21 connected to the output of the current diminishing signal generation circuit 2 is turned on, and the charging voltage of the capacitor storage power supply 7 is switched on. A control mode CP ′ for decreasing current (VI) is executed, in which the charging current is controlled to decrease the charging current I in inverse proportion to the increase in Vc. In FIG. 2B, this switching point is represented by a point at which the charging voltage Vc of the capacitor storage power source 7 becomes Vst.

  Further, when the charging voltage Vc of the capacitor storage power supply 7 increases and becomes larger than the voltage reference value Vrefv in the constant voltage signal generation circuit 3, the error amplification signal output from the constant voltage signal generation circuit 3 is converted into a current diminishing signal generation circuit. 2 is smaller than the error amplification signal output from 2, the diode D21 connected to the output of the current diminishing signal generation circuit 2 is turned off, and the diode D31 connected to the output of the constant voltage signal generation circuit 3 is turned on. Instead, a constant voltage charging control mode CV is executed in which the charging current is controlled so that the charging voltage Vc is smaller than the voltage reference value Vrefv. In FIG. 2B, this switching point is represented by a point at which the charging voltage Vc of the capacitor storage power source 7 becomes Vfu.

  Next, a specific configuration of the signal generation circuit will be described. 3 is a diagram showing an embodiment of a constant current signal generating circuit and a current decreasing signal generating circuit, FIG. 4 is a diagram showing another embodiment of the current decreasing signal generating circuit, and FIG. 5 is an embodiment of a reference value setting circuit. 11, 21, 22 are operational amplifiers, 23 is a logic processing circuit, 71 is an electric double layer capacitor, 72 is a parallel monitor, AS, AS1, AS1 ′ are analog switches, C11, C21, C31, Cr1 Is a capacitor, R11, R21, R22, R23, R31, R32, R33, R34, R35, Rr1 are resistors, Rrv, Rrv ′ are variable resistors, Tr is a transistor, and + V is a bias power supply.

  In FIG. 3, the constant current signal generation circuit 1 inputs a detection signal of the charging current I to its inverting input terminal − and inputs the current reference value Vrefi to the non-inverting input terminal + in the inverting input terminal − of the operational amplifier 11. An error amplifying circuit is configured by connecting a series circuit of a capacitor C11 and a resistor R11 between the terminal-and the output terminal. Similarly, the current diminishing signal generating circuit 2 inputs the detection signal of the charging current I to its inverting input terminal − and inputs the current reference value Vref (v−i) to the non-inverting input terminal + in the operational amplifier 21. Thus, an error amplifier circuit is configured by connecting a series circuit of a capacitor C21 and a resistor R21 between the inverting input terminal − and the output terminal.

  The current reference value Vref (vi) is a value that is inversely proportional to the increase in the charging voltage Vc of the capacitor storage power supply 7 as described above. For example, as shown in FIG. , The detection signal of the charging voltage Vc of the capacitor storage power supply 7 is input to the inverting input terminal − via the resistor R22, the offset value Voff-set is input to the non-inverting input terminal +, and the inverting input terminal − and the output A subtracting circuit is configured by connecting a resistor R23 between the terminals. According to this subtraction circuit, a current reference value Vref (vi) of Voff−set + (Voff−set−Vc) R23 / R22 (where R23 = R22 is 2Voff−set−Vc) is taken out. When Voff-set is set to a value that coincides with Vst in FIG. 2B, when the charging voltage Vc of the capacitor storage power supply 7 increases to Voff-set, the constant current signal generation circuit 1 and the current diminishing signal generation circuit 2 Since the reference value becomes the same value, the setting is switched from here to the current diminishing control mode.

  In the embodiment shown in FIG. 3, the charging current is reduced in inverse proportion to the signal from the constant current signal generation circuit 1 that controls the charging current so as to be constant and the increase in the charging voltage Vc of the capacitor storage power source 7. The operation of the parallel monitor connected to each electric double layer capacitor of the capacitor storage power source 7 is automatically switched by the OR logic circuit of the diodes D11 and D21. FIG. 4 shows an embodiment configured to switch the control mode on the condition of.

  In the embodiment shown in FIG. 4, an analog switch AS is inserted in series between the output of the operational amplifier 21 in the current diminishing signal generating circuit 2 and the diode D 21 of the OR logic circuit, and the analog switch is output by the output of the logic processing circuit 23. AS is controlled. Here, the logic processing circuit 23 performs logic processing on the full charge signal F of the parallel monitor 72 connected to each electric double layer capacitor 71 of the capacitor storage power source 7, and for example, by performing OR logic processing, The analog switch AS is turned on on condition that one of the parallel monitors 72 is turned on. The parallel monitor 72 is connected in parallel to each capacitor. When the full charge of the capacitor is detected, the parallel monitor 72 bypasses the charge current to perform initialization while suppressing the voltage rise, and when full charge is reached, the full charge voltage is determined. The full charge signal F is sent out by. By performing OR logic processing on such a full charge signal F, constant current charging is continued until any one parallel monitor 72 is turned on, and after any one parallel monitor 72 is turned on, As shown in FIG. 4B, the charging current is reduced and the mode is switched to the current diminishing (V-I) control mode. If the Vst point (offset value Voff-set) shown in FIG. 2 (b) is further set in this way, the charging voltage of each electric double layer capacitor 71 of the capacitor storage power supply 7 has a large variation. When the charging voltage Vc of the capacitor storage power supply 7 is small and the first parallel monitor performs a bypass operation, the control mode is switched at the timing shown in FIG. 4B, the variation is small, and the charging voltage Vc of the capacitor storage power supply 7 is When the first parallel monitor is increased and the bypass operation is performed, the switching of the control mode can be extended to the timing shown in FIG. 4B to increase the charging efficiency. Alternatively, the logic processing circuit 23 may be configured to determine that the number of parallel monitors 72 turned on is a predetermined number and turn on the analog switch AS according to the condition.

  Next, each reference value setting circuit will be described. First, the current reference value setting circuit Vrefi and the offset value setting circuit Voff-set will be described with reference to FIGS. The current reference value setting circuit unit Vrefi and the offset value setting circuit unit Voff-set receive the current reference value Vrefi, depending on the on-duty ratio of the F signal, when the F signal as the entire capacitor storage power supply 7 is input. A circuit is used in which the offset value Voff-set (hereinafter sometimes collectively referred to as Vref) gradually decreases.

  In the present invention, the reference value setting circuit as described above is used, and the current reference value Vrefi and the offset value Voff-set are gradually reduced according to the on-duty ratio of the F signal. Accordingly, it is possible to continue charging the capacitor with a charging current slightly smaller than the charging current when full charge is reached. In the current reference value setting circuit unit Vrefi (or the offset value setting circuit unit Voff-set) in FIG. 5A, a resistor R36 is connected between the base of the transistor Tr serving as a switching element and the input terminal. R35 is connected in series between the base and the ground line. The emitter of the transistor Tr is connected to the ground line, and resistors R31, R32, and R34 are connected between the collector and the power source + V. The resistor R23, the capacitor C31, and the like constitute a filter circuit, and the voltage across the capacitor C31 is output as the current reference value Vref.

  When the pulse signal of the F signal is applied to the input terminal of the current reference value setting circuit Vrefi configured as described above, the transistor Tr is turned on and off in synchronization with the pulse signal, and the transistor is synchronized with the pulse signal. A current flows through Tr. Accordingly, the voltage −Vref− across the capacitor C31 has a profile voltage as shown in FIG. That is, the current reference value setting circuit Vrefi operates such that the current reference value Vrefi decreases as the on-duty ratio of the F signal increases.

  By using the reference value setting circuit as described above, in the present invention, the charging current when the full charge is reached by the gradual decrease of the current reference value with respect to the capacitor that apparently reaches the full charge voltage due to the internal resistance component of the capacitor. The capacitor can be continuously charged with a slightly smaller charging current, and the capacitor can be efficiently charged. Further, since it becomes possible to continue charging the capacitor with a charging current slightly smaller than the charging current when full charge is reached, charging is performed little by little with the withstand current value Is of the parallel monitor that is much smaller than the capacitor charging current. This can be avoided and the capacitor can be charged efficiently.

  The voltage reference value setting circuit Vrefv can be constituted by various known circuits, for example, as shown in FIG. That is, as shown in FIG. 5C, the stabilized bias power source + V is divided by the voltage dividing circuit of the fixed resistor Rr1 and the variable resistor Rrv, the reference value Vref is taken out from the voltage dividing connection point, and the variable resistor Rrv is obtained. To adjust to a predetermined voltage. The capacitor Cr1 is connected in parallel to the variable resistor Rrv as a noise countermeasure. Further, as shown in FIG. 5D, a similar circuit may be connected in parallel via the analog switch AS1, and the reference value may be switched by turning on / off the analog switch AS1. For switching the reference value, the variable resistor Rrv ′ may be connected in parallel with the variable resistor Rrv via the analog switch AS1 ′. When the reference value is switched by the analog switches AS1 and AS1 ′ in this way, for example, when this is adopted in the current reference value setting circuit Vrefi, the constant current charging value is stepwise according to a predetermined condition. Since the switching can be performed, the charging current for constant current charging can be switched according to the operation of the parallel monitor 72 by using the output signal of the logic processing circuit 23 described above as a switching signal.

  FIG. 6 is a diagram showing an embodiment of a charging device including a PWM-controlled switching converter, in which 61 is a control circuit, 62 is an error signal generation circuit, C1 and C2 are capacitors, D is a diode, L is a coil, R is a current detection resistor, SW1 and SW2 are switch elements, I is a charging current, Vc is a charging voltage, and Vi is a power supply voltage.

  In the charging device shown in FIG. 6A, a charging control switch element SW and a choke coil L are connected in series between a charging power supply 5 and a capacitor storage power supply 7, and a diode D is connected in parallel to these series connection points. Is connected to capacitors C1 and C2 in parallel on the input side and the output side, and includes a step-down type switching converter that turns on / off the switch element SW by a PWM signal and supplies a charging current, In order to detect the charging current, a current detection resistor R is inserted and connected in series. Further, in the charging device shown in FIG. 6B, a charging control choke coil L and a switch element SW2 are connected in series between the charging power source 5 and the capacitor storage power source 7, and in parallel with these series connection points. The switch element SW1 is connected, and capacitors C1 and C2 are connected in parallel to the input side and the output side. The switch element SW1 is turned on / off by the PWM signal, and the switch element SW2 is turned off / on in the opposite phase to charge. A step-up type switching converter that supplies current is provided, and a current detection resistor R is inserted and connected in series to detect a charging current. The PWM control circuit 61 supplies the PWM signal to the switch elements SW, SW1, and SW2, and the error signal generation circuit 62 supplies the PWM control circuit 61 with the charging current I, the charging voltage Vc of the capacitor storage power source 7, the reference value, and the offset value. Based on the above, the error amplification signal described above is supplied.

  In addition, this invention is not limited to said embodiment, A various deformation | transformation is possible. For example, in the above embodiment, the control modes of constant current charge CC, current reduction charge CP ′, and constant voltage charge CV are provided and switched under predetermined conditions. Only by having the control mode of ′, it is possible to charge to the full charge by the current reduction charge CP ′, or to stop the charge at the full charge voltage. Further, it goes without saying that the constant current signal generation circuit, the current diminishing signal generation circuit, and the like are not limited to the circuit shown in FIG.

It is a figure which shows embodiment of the charging device for capacitor electrical storage power supplies which concerns on this invention. It is a figure explaining electric current gradual charge (VI control). It is a figure which shows embodiment of a constant current signal generation circuit and a current decreasing signal generation circuit. It is a figure which shows other embodiment of a current decreasing signal generation circuit. It is a figure which shows embodiment of a reference value setting circuit. It is a figure which shows embodiment of the charging device provided with the switching converter by which PWM control is carried out. It is a figure which shows the outline of a circuit structure of a parallel monitor. It is a figure which shows the outline of the charging device of the several electric double layer capacitor provided with the parallel monitor. The equivalent circuit including the internal resistance component of an electric double layer capacitor is shown.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Constant current signal generation circuit, 2 ... Current decreasing signal generation circuit, 3 ... Constant voltage signal generation circuit, 4 ... PWM control circuit, 5 ... Charging power supply, 6 ... Charging Device: 7 ... Capacitor storage power source, D11, D21, D31 ... Diode, R ... Current detection resistor, Vrefi ... Current reference value setting circuit, Vrefv ... Voltage reference value setting circuit, Voff -Set ... offset value setting circuit, I ... charge current, Vc ... charge voltage, PM1 to PMn ... parallel monitor

Claims (3)

Pulse width modulation means by pulse width modulation means from a charging power supply to a capacitor storage power source that stores a plurality of electric double layer capacitors connected in series with a parallel monitor that bypasses the charging current at a predetermined voltage and outputs a full charge signal In the charging device for the capacitor storage power source configured to modulate and control the charging current to perform charging,
The current reference value, which is one factor that determines the pulse width in the pulse width modulation means, is controlled so as to change according to the frequency of the F signal that is the logical sum of the full charge signals from the plurality of parallel monitors. A charging device for a capacitor storage power source. 2. The charging device for a capacitor storage power source according to claim 1, wherein the current reference value is controlled so as to gradually decrease in accordance with the frequency of the F signal. 3. The charging device for a capacitor storage power source according to claim 1, further comprising: a signal generating unit that generates an error amplification signal by comparing the current reference value with a charging current. 4.

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