JP2010220373A - Balancing circuit of energy storage element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a balancing circuit of energy storage elements capable of miniaturizing the balancing circuit by reducing the number of semiconductor switching elements and diodes, when voltages of a plurality of energy storage elements connected in series are equalized with low loss. <P>SOLUTION: In the balancing circuit of the energy storage elements, the semiconductor switching elements SW1-SW4 and diodes D1-D4, which are connected in the reverse parallel to the semiconductor switching elements SW1-SW4, are connected in parallel to the energy storage elements C1-C4, and inductors L1-L3 are connected between the connection points of the energy storage elements C1-C4 and those of the semiconductor switching elements SW1-SW4. An average voltage V<SB>ave</SB>of all the energy storage elements C1-C4 connected in series and a voltage of each of the energy storage elements are compared to turn on the switching element connected in parallel to the energy storage elements having a voltage higher than the average voltage V<SB>ave</SB>. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a storage element balance circuit for equalizing voltages of a plurality of capacitors, batteries, and other storage elements that are charged and discharged in a batch.

  In a power supply in which a plurality of power storage elements are connected in series, it is necessary to equalize the voltages of the power storage elements in order to effectively use power and extend the life. Usually, in order to equalize the voltages of the power storage elements connected in series, a balance resistor is connected in parallel with the power storage elements. In this case, the charge of the high potential power storage elements is consumed by the resistance. Therefore, there is a problem that generated loss increases. Therefore, as a technique for equalizing the voltages of a plurality of power storage elements with low loss, for example, a circuit described in Patent Document 1 has been proposed.

  FIG. 16 shows a conventional example of a balance circuit of a storage element. In FIG. 16, C21, C22, C23, C24 are capacitors, storage devices such as batteries, L21, L22, L32 are inductors, SW21, SW22, SW23, SW24, SW31, SW32 are semiconductor switching devices, D21, D22, D23, D24, D31, and D32 are diodes connected to the semiconductor switching element in antiparallel.

  In FIG. 16, four power storage elements C21 to C24 having the same capacity are connected in series, and a series circuit of semiconductor switching elements SW21 to SW24 is connected in parallel with the series circuit. One end of the inductor L21 is connected to a connection point between the storage elements C21 and C22, and the other end of the inductor L21 is connected to a connection point between the semiconductor switching elements SW21 and SW22. Similarly, one end of the inductor L22 is connected to a connection point between the storage elements C23 and C24, and the other end of the inductor L22 is connected to a connection point between the semiconductor switching elements SW23 and SW24. Furthermore, the series circuit of the storage elements C22 and C23 is connected in parallel with the series circuit of the semiconductor switching elements SW31 and SW32, one end of the inductor L32 is connected to the connection point of the storage elements C22 and C23, and the inductor L32 The other end is connected to the connection point of the semiconductor switching elements SW31 and SW32.

In such a configuration, attention is paid to three sets of series circuits each including two storage elements C21 and C22, C22 and C23, and C23 and C24, and the voltages of the two storage elements are compared for each set. Thus, the semiconductor switching elements corresponding to the high-voltage storage elements are turned on / off to equalize the voltage of the storage elements for each set.
For example, if the voltage of the storage element C21 is higher than that of the storage element C22 in the combination of the storage element C21 and the storage element C22, the semiconductor switching element SW21 is turned on. When semiconductor switching element SW21 is turned on, a closed loop of power storage element C21 → semiconductor switching element SW21 → inductor L21 → power storage element C21 is formed, and energy is transferred from power storage element C21 to inductor L21. Thereafter, when the semiconductor switching element SW21 is turned off, the energy stored in the inductor L21 is transferred to the power storage element C22 through the diode D22. By operating in this way, the charge moves from the high-potential storage element C21 to the storage element C22, and the voltage of the storage element C21 and the voltage of the storage element C22 are equalized.

  On the other hand, in the set of the storage element C21 and the storage element C22, when the voltage of the storage element C22 is high and the voltage of the storage element C21 is low, the semiconductor switching element SW22 is turned on / off to store power from the storage element C22. The charge moves to the element C21, and the voltage of the energy storage element C21 and the voltage of the energy storage element C22 are equalized. In addition, the combination of the storage element C22 and the storage element C23 and the combination of the storage element C23 and the storage element C24 operate in the same manner as described above so that the voltages of the two storage elements are equalized for each set. become.

JP 7-322516 A

  According to the above prior art, it is possible to equalize the voltages of the plurality of power storage elements with low loss, but in order to equalize the voltages of the four power storage elements C21, C22, C23, C24, Six semiconductor switching elements SW21, SW22, SW23, SW24, SW31, SW32 and six diodes D21, D22, D23, D24, D31, D32 are required. Such a conventional technique has a problem that the circuit configuration is complicated and large because semiconductor switching elements and diodes more than the number of power storage elements are required.

  The present invention provides a balance of power storage elements that can reduce the number of semiconductor switching elements and diodes and reduce the size of the balance circuit when equalizing the voltages of a plurality of power storage elements connected in series with low loss. An object is to provide a circuit.

  In order to achieve the above object, the present invention provides a balance circuit for power storage elements that equalizes voltages of a plurality of power storage elements connected in series, and the same number of power storage elements as the plurality of power storage elements connected in series. A series connection circuit of semiconductor switching elements in which a number of diodes are connected in reverse parallel is connected in parallel, and an inductor is connected between the connection point of the storage element and the connection point of the semiconductor switching element, and the series connection is performed. The semiconductor switching element is controlled by comparing an average voltage of the entire storage element or a predetermined fixed voltage with a voltage of each storage element.

  Further, in a storage element balance circuit for equalizing the voltages of a plurality of power storage elements connected in series, semiconductor switching in which the plurality of power storage elements connected in series and the same number of diodes as the power storage elements are connected in reverse parallel A series connection circuit of elements is connected in parallel, an inductor is connected between a connection point of the power storage element and a connection point of the semiconductor switching element, and the uppermost stage of the plurality of power storage elements connected in series An inductor is provided between the positive electrode of the power storage element and the positive electrode of the semiconductor switching element, and a jumper pin for short-circuiting the inductor is provided, and the negative electrode and the semiconductor of the lowermost power storage element of the plurality of power storage elements connected in series A jumper pin is provided between the negative electrode of the switching element to constitute a power storage module.

  According to this invention, a plurality of power storage elements connected in series and a series connection circuit of semiconductor switching elements in which the same number of diodes as the power storage elements are connected in reverse parallel are connected in parallel, and the connection point of the power storage elements An inductor is connected between each connection point of the semiconductor switching elements, and the semiconductor switching element is controlled by comparing an average voltage of the whole power storage elements connected in series or a predetermined fixed voltage with a voltage of each power storage element. As a result, the loss generated in the balance circuit can be reduced, and the balance circuit can be reduced in size.

In this way, by equalizing the voltage of each power storage element and suppressing the voltage variation of the power storage element, the remaining capacity of each power storage element decreases at substantially the same rate of decrease, and all the storage batteries reach the discharge end voltage almost simultaneously. Therefore, the dischargeable energy stored in each power storage element can be used effectively, and the decrease in the discharge duration of the power storage element can be suppressed.
Further, a plurality of power storage elements connected in series and a series connection circuit of semiconductor switching elements in which the same number of diodes as the power storage elements are connected in reverse parallel are connected in parallel, and the connection points of the power storage elements and the semiconductor switching elements An inductor is connected between each of the connection points, and an inductor is provided between the positive electrode of the uppermost storage element of the plurality of storage elements connected in series and the positive electrode of the semiconductor switching element, and the inductor is short-circuited. A plurality of power storage modules configured by providing a jumper pin between the negative electrode of the lowermost power storage element of the plurality of power storage elements connected in series and the negative electrode of the semiconductor switching element. When the power storage elements are connected in series, a power source having a desired capacity can be easily configured.

Circuit diagram showing an embodiment of the present invention Operation explanatory diagram showing the first operation of the present invention FIG. 2 is a timing chart showing waveforms at various parts in the operation of FIG. Operation explanatory diagram showing the second operation of the present invention FIG. 4 is a timing chart showing waveforms at various parts in the operation of FIG. Operation explanatory diagram showing the third operation of the present invention FIG. 6 is a timing chart showing waveforms at various parts in the operation of FIG. Operation explanatory diagram showing the fourth operation of the present invention FIG. 8 is a timing chart showing waveforms at various parts in the operation of FIG. Operation explanatory diagram showing the fifth operation of the present invention FIG. 10 is a timing chart showing waveforms at various parts in the operation of FIG. Block diagram showing a specific example of the control of the present invention Circuit diagram showing another embodiment of the present invention Circuit diagram when using Fig. 13 in series connection Block diagram showing a specific example of the control of FIG. Circuit diagram showing a conventional balance circuit

  FIG. 1 is a circuit diagram showing an embodiment of the present invention. In FIG. 1, C1, C2, C3, and C4 are storage elements such as capacitors and batteries, L1, L2, and L3 are inductors, SW1, SW2, SW3, and SW4 are semiconductor switching elements, and D1, D2, D3, and D4 are semiconductors, respectively. It is a diode connected in antiparallel to the switching elements SW1, SW2, SW3, SW4.

  In this figure, four storage elements C1 to C4 having the same capacity are connected in series, a series connection circuit of the storage elements C1 to C4, and a series connection circuit of the same number of semiconductor switching elements SW1 to SW4 as the storage elements, Are connected in parallel. One end of the inductor L1 is connected to the connection point between the power storage elements C1 and C2, and the other end of the inductor L1 is connected to the connection point between the semiconductor switching elements SW1 and SW2. Similarly, one end of the inductor L2 is connected to the connection point of the storage elements C2 and C3, the other end of the inductor L2 is connected to the connection point of the semiconductor switching elements SW2 and SW3, and one end of the inductor L3 is connected to the storage element C3. While being connected to the connection point of C4, the other end of the inductor L3 is connected to the connection point of the semiconductor switching elements SW3 and SW4.

This invention having the above structure, calculates the average voltage V _ave per one storage element than the total voltage of the series-connected storage element, through the inductor in the capacitor of a voltage higher than the average voltage V _ave By switching semiconductor switching elements connected in parallel, the voltages of the storage elements connected in series are equalized. Embodiments of the present invention will be described below with reference to FIGS. In this embodiment, the case where four power storage elements are in series is shown. However, the number of series is not limited, and may be three or more in series.

FIG. 2 is an operation explanatory diagram showing the first operation, and shows a case where the voltage of the power storage element C1 is higher than that of the other power storage elements C2-4. FIG. 3 is a timing chart showing the waveforms of the respective parts at this time. (A), (b), (c) and (d) show gate signals of the semiconductor switching elements SW1, SW2, SW3 and SW4, respectively. , (E), (f), (g), and (h) are currents i _(SW1) , i _(SW2) , i _{(SW3 )} flowing through the semiconductor switching elements SW1, SW2, SW3, SW4 or diodes D1, D2, D3, D4, respectively. ₎ , I _(SW4) , and (i), (j), and (k) indicate currents i _(L1) , i _(L2) , and i _(L3) flowing through the inductors L1, L2, and L3, respectively. is there.

  2 and 3, when the semiconductor switching element SW1 connected in parallel to the power storage element C1 is turned on at time t1, the power storage element C1 → the semiconductor switching element SW1 → the inductor L1 → A closed loop of the storage element C1 is formed, and energy is transferred from the storage element C1 to the inductor L1. Thereafter, when the semiconductor switching element SW1 is turned off at time t2, the energy stored in the inductor L1 is transferred to the storage elements C2, C3, C4 through the diodes D2, D3, D4 as shown by the arrows in FIG. The By operating in this way, the charge moves from the high-potential storage element C1 to the storage elements C2, C3, C4, and the voltages of the storage elements C1, C2, C3, C4 are equalized.

FIG. 4 is an operation explanatory diagram showing the second operation, and shows a case where the voltage of the power storage element C2 is higher than those of the other power storage elements C1, C3, and C4. FIG. 5 is a timing chart showing waveforms of the respective parts at this time.
4 and 5, when the semiconductor switching element SW2 connected in parallel to the power storage element C2 is turned on at time t1, as shown by the arrow in FIG. 4A, the power storage element C2 → the inductor L1 → the semiconductor switching element SW2 → A closed loop of inductor L2 → power storage element C2 is formed, and energy is transferred from power storage element C2 to inductors L1 and L2. Thereafter, when the semiconductor switching element SW2 is turned off at time t2, as shown by the arrow in FIG. 4B, the energy stored in the inductor L1 is transferred to the power storage element C1 through the diode D1 and is also stored in the inductor L2. The energy is transferred to the storage elements C3 and C4 through the diodes D3 and D4. By operating in this way, the charge moves from the high-potential storage element C2 to the storage elements C1, C3, C4, and the voltages of the storage elements C1, C2, C3, C4 are equalized.

FIG. 6 is an operation explanatory diagram showing the third operation, and shows a case where the voltages of the power storage elements C1 and C3 are higher than those of the other power storage elements C2 and C4. FIG. 7 is a timing chart showing waveforms of the respective parts at this time.
6 and 7, when the semiconductor switching element SW1 connected in parallel to the power storage element C1 and the semiconductor switching element SW3 connected in parallel to the power storage element C3 are turned on at time t1, they are indicated by arrows in FIG. 4 (a). Thus, the closed loop of the storage element C1 → the semiconductor switching element SW1 → the inductor L1 → the storage element C1 and the closed storage loop of the storage element C3 → the inductor L2 → the semiconductor switching element SW3 → the inductor L3 → the storage element C3 are formed. The energy is transferred to the inductor L1, and the energy is transferred from the power storage element C3 to the inductors L2 and L3. Thereafter, when the semiconductor switching elements SW1 and SW3 are turned off at time t2, as shown by arrows in FIG. 6B, energy stored in the inductors L1 and L2 is transferred to the power storage element C2 through the diode D2, and the inductor The energy stored in L3 is transferred to the storage element C4 through the diode D4. By operating in this manner, charges move from the high potential power storage elements C1, C3 to the power storage elements C2, C4, and the voltages of the power storage elements C1, C2, C3, C4 are equalized.

FIG. 8 is an operation explanatory diagram showing the fourth operation, and shows a case where the voltages of the power storage elements C1 and C2 are higher than those of the other power storage elements C3 and C4. FIG. 9 is a timing chart showing the waveforms of the respective parts at this time.
8 and 9, when the semiconductor switching element SW1 connected in parallel to the power storage element C1 and the semiconductor switching element SW2 connected in parallel to the power storage element C2 are turned on at time t1, they are indicated by arrows in FIG. 8 (a). As described above, energy is transferred from the power storage elements C1 and C2 to the inductors L1 and L2. Thereafter, when the semiconductor switching elements SW1 and SW2 are turned off at time t2, as shown by arrows in FIG. 8B, the energy accumulated in the inductors L1 and L2 is transferred to the power storage elements C3 and C4 through the diodes D2, D3, and D4. To be migrated. By operating in this way, charges move from the high potential power storage elements C1, C2 to the power storage elements C3, C4, and the voltages of the power storage elements C1, C2, C3, C4 are equalized.

FIG. 10 is an operation explanatory diagram showing the fifth operation, and shows a case where the voltages of the power storage elements C1, C2, and C3 are higher than those of the power storage element C4. FIG. 11 is a timing chart showing the waveforms of the respective parts at this time.
10 and 11, semiconductor switching element SW1 connected in parallel to power storage element C1 at time t1, semiconductor switching element SW2 connected in parallel to power storage element C2, and semiconductor switching element connected in parallel to power storage element C3 When SW3 is turned on, energy is transferred from the power storage elements C1, C2, and C3 to the inductors L1, L2, and L3 as indicated by arrows in FIG. Thereafter, when the semiconductor switching elements SW1, SW2, and SW3 are turned off at time t2, as shown by arrows in FIG. 10B, the energy stored in the inductors L1, L2, and L3 passes through the diodes D2, D3, and D4, and the storage element. Transition to C4. By operating in this way, charges move from the high potential power storage elements C1, C2, C3 to the power storage element C4, and the voltages of the power storage elements C1, C2, C3, C4 are equalized.

  Next, FIG. 12 is a block diagram showing a specific example of the control circuit of the present invention. 11, 21, 31, 41 are control circuits for controlling the semiconductor switching elements SW1, SW2, SW3, SW4, respectively. 22, 32, 42 are multipliers, 31, 32, 33, 43 are comparators, 41, 42, 43, 44 are pulse generators, and 51, 52, 53, 54 are AND circuits. In FIG. 12, the same members as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted.

In the control circuit 11 that controls the semiconductor switching element SW1, the voltage detection value V _C1-4 of the entire storage elements C1 to C4 connected in series is multiplied by ¼ by the multiplier 21 to detect the detection value of the voltage of the entire storage element. It calculates the average voltage V _ave per one storage element from V _C1-4, compared by the comparator 31 and the detection value V _C1 of the terminal voltage of the average voltage V _ave and the power storage device C1, the voltage of the storage element C1 When V _C1 is higher than the average voltage V _ave , an active signal (H in this example when V _C1 > _¼ × V _C1-4 ) is output. The output signal of the comparator 31 and the output signal of the pulse generator 41 are input to the AND circuit 51, and the AND circuit 51 outputs the gate signal G1 of the semiconductor switching element SW1.

Here, since the inductor L1 is saturated when the on-pulse width of the semiconductor switching element SW1 is long, the pulse signal of the pulse generator 41 is a high-frequency pulse signal PulseA, and an AND condition between the high-frequency pulse signal PulseA and the output signal of the comparator 31 Thus, the gate signal G1 of the semiconductor switching element SW1 is formed.
The control circuits 12, 13, and 14 have the same configuration as the control circuit 11, but when all the semiconductor switching elements SW1 to SW4 are simultaneously turned on, the power storage elements C1 to C4 are short-circuited by the semiconductor switching elements SW1 to SW4. Therefore, the high-frequency pulse signal distributes at least two switching timings of the semiconductor switching elements SW1 to SW4 so that all the semiconductor switching elements SW1 to SW4 are not turned on simultaneously. At this time, when the voltages of a plurality of adjacent storage elements among the storage elements C1 to C4 connected in series are higher than the average voltage _Vave , it is more efficient to simultaneously turn on the semiconductor switching elements corresponding to the storage elements. Therefore, it is desirable to configure the pulse distribution to be minimized. In the case of FIG. 12, only the high frequency pulse signal PulseB of the pulse generator 44 of the control circuit 14 is distributed.

In the above, in order to equalize the voltages of all the storage elements C1 to C4, the average voltage V _ave is used as the command value to be compared with the terminal voltage of the storage element, but only the overcharge protection of the storage element is performed. In order to prevent the voltage of the storage element from becoming an overvoltage, the semiconductor switching element connected in parallel via the storage element and the inductor is turned on and the voltage of the storage element is lowered so that the storage element voltage does not become an overvoltage. I will let you. In this case, a predetermined overvoltage level (fixed voltage) is used as a command value to be compared with the terminal voltage of the storage element, instead of the average voltage V _{ave of the} entire storage element.

  FIG. 13 is a circuit diagram showing another embodiment of the present invention, and the same members as those in FIG. In FIG. 13, reference numeral 61 denotes a power storage module obtained by modularizing a plurality of power storage elements C1 to C4 connected in series. An inductor L0 is connected between the positive electrode of the uppermost power storage element C1 and the positive electrode of the semiconductor switching element SW1. A jumper pin JP1 for short-circuiting the inductor L0 is provided, and a jumper pin JP2 is provided between the negative electrode of the lowermost power storage element C4 and the negative electrode of the semiconductor switching element SW4. In this embodiment, the power storage elements are shown as four power storage modules 61 in series, but the number of power storage elements in series is not limited.

  FIG. 13 shows an example in which the power storage module 61 is used alone, and a circuit equivalent to FIG. 1 is obtained by short-circuiting the jumper pins JP1 and JP2. FIG. 14 shows a specific example in which a plurality of power storage modules 61 are connected in series. The uppermost power storage module 61 shorts the jumper pin JP1 and opens the jumper pin JP2. The lowermost power storage module 61 opens the jumper pin JP1 and shorts the jumper pin JP2. Although not shown, the middle storage module 61 opens both jumper pins JP1 and JP2. Thus, by modularizing a plurality of power storage elements connected in series, when a plurality of power storage elements are connected in series, a power source having a desired capacity can be easily configured.

Next, FIG. 15 is a block diagram showing a specific example of the control of FIG. 14, in which insulation amplifiers 71 and 72 are provided, and resistors R1 to R4 are provided. In addition, the description about the member which attached | subjected the same code | symbol is abbreviate | omitted. Further, FIG. 15 shows a case where four power storage modules 61 are connected in series, but the number of power storage modules in series is not limited.
In the power storage modules 61 connected in series, the total voltage of each power storage module 61 is sent out by the insulation amplifier 71, and the output of the insulation amplifier 71 of each power storage module 61 is divided by resistors R1 to R4. The average voltage V _ave of the whole voltage is obtained. The obtained average voltage V _ave is returned to each power storage module 61 by the insulation amplifier 72, so that the average voltage V _ave of each power storage element obtained from the voltage across the power storage modules 61 connected in series is By setting the command value to be compared with the terminal voltage of the power storage element, the balance control circuit in each power storage module 61 can be obtained. Since the balance control at this time is the same as the control described in FIG. 12, the description thereof is omitted here.

In this way, by performing balance control using the average voltage _Vave of each storage element obtained from the voltage of the entire storage module 61 as a command, the voltage variation of the storage elements is connected in series regardless of the number of charging modules 61 in series. It is possible to suppress all of the storage elements.

C1, C2, C3, C4 ... Power storage elements L0, L1, L2, L3 ... Inductors SW1, SW2, SW3, SW4 ... Semiconductor switching elements D1, D2, D3, D4 ... Diodes 11, 21 , 31, 41... Control circuit 21, 22, 32, 42... Multiplier 31, 32, 33, 43 ... comparator 41, 42, 43, 44 ... pulse generator 51, 52, 53, 54 ... AND circuit JP1, JP2 ... Jumper pin 61 ... Power storage module 71, 72 ... Insulation amplifier

Claims (9)

  In a storage element balance circuit for equalizing voltages of a plurality of power storage elements connected in series, a plurality of power storage elements connected in series and a semiconductor switching element in which the same number of diodes as the power storage elements are connected in reverse parallel A series connection circuit is connected in parallel, an inductor is connected between the connection point of the storage element and the connection point of the semiconductor switching element, and the average voltage of the whole storage element connected in series and the voltage of each storage element And the semiconductor switching element is controlled to balance the storage element.   2. The balance circuit for a storage element according to claim 1, wherein a semiconductor switching element connected in parallel to the storage element having a voltage higher than the average voltage via an inductor is turned on.   In a storage element balance circuit for equalizing voltages of a plurality of power storage elements connected in series, a plurality of power storage elements connected in series and a semiconductor switching element in which the same number of diodes as the power storage elements are connected in reverse parallel A series connection circuit is connected in parallel, an inductor is connected between a connection point of the power storage element and a connection point of the semiconductor switching element, and a predetermined fixed voltage is compared with a voltage of each power storage element. A balance circuit for an electric storage element, characterized by controlling a semiconductor switching element.   4. The balance circuit for a storage element according to claim 3, wherein a semiconductor switching element connected in parallel to the storage element having a voltage higher than the fixed voltage via an inductor is turned on.   In a storage element balance circuit for equalizing voltages of a plurality of power storage elements connected in series, a plurality of power storage elements connected in series and a semiconductor switching element in which the same number of diodes as the power storage elements are connected in reverse parallel A series connection circuit is connected in parallel, an inductor is connected between a connection point of the storage element and a connection point of the semiconductor switching element, and the storage element at the uppermost stage of the plurality of storage elements connected in series An inductor is provided between the positive electrode of the semiconductor switching element and the positive electrode of the semiconductor switching element, and a jumper pin for short-circuiting the inductor provided between the positive electrode of the uppermost storage element and the positive electrode of the semiconductor switching element is provided, and is connected in series. A jumper pin between the negative electrode of the lowermost storage element and the negative electrode of the semiconductor switching element. Balance circuit of the power storage device characterized by constituting the power storage modules provided.   6. The balance circuit for a power storage element according to claim 5, wherein a plurality of the power storage modules are connected in series, and an overall voltage of each power storage module is sent through a first insulation amplifier, so that each power storage module is insulated. An output of an amplifier is divided by a resistor to obtain an average voltage of the entire voltage of each power storage module, and the average voltage is returned to each power storage module via a second insulation amplifier. circuit.   7. The storage element balance circuit according to claim 6, wherein a semiconductor switching element connected in parallel via an inductor to the storage element in the storage module having a voltage higher than the average voltage is turned on. Balance circuit.   8. The storage element balance circuit according to claim 1, wherein the semiconductor switching element is controlled by a high-frequency pulse signal. 9. The balance circuit for a storage element according to claim 1, wherein the timing at which the semiconductor switching element is turned on is distributed to at least two.

Images