JP2007208230A - Dicing method of laminated substrates - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a dicing method of laminated substrates allowing an electrode pad to be easily exposed outside in a dicing process even in the case when the electrode pad is located inside the lamination. <P>SOLUTION: A method of dicing laminated substrates has: a step for forming a plurality of semiconductor wafers 3 of a semiconductor device; a step for laminating a semiconductor substrate 8 of the roughly same size as the semiconductor wafer 3 on the surface side of the semiconductor wafer with a spacer 7 in between; a step for performing half-cut dicing in such a manner that a dicing line 9 crosses a region between an electrode pad 4 and an element 6 in the same semiconductor device from the surface side of the semiconductor substrate; and a half-cut dicing step on the basis of the dicing line 5 separated into individual semiconductor devices from the surface side of the semiconductor wafer 3. Thereby, the electrode pad 4 can be easily exposed outside in the dicing step even in the case when the electrode pad 4 is inside the lamination. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to a wafer dicing method in a semiconductor element using a bonded substrate.

  Many semiconductor integrated circuit elements are formed on a silicon substrate in a wafer state by being vertically and horizontally aligned, and the silicon substrate on which the elements are formed is cut by a dicing technique and divided into chips of individual elements.

  On the other hand, there is a semiconductor integrated circuit device manufactured using a wafer bonding technique or the like, which has a structure in which a silicon substrate on which the device is formed and a simple silicon wafer, or a silicon substrate on which the device is formed and a glass substrate are bonded together. ing. Even in such a semiconductor device, a method of dividing the chip into individual chips after element formation and substrate bonding is employed.

When the bonded substrate is divided into chips, dicing is performed from the surface on the silicon substrate side where the element is formed first to the junction between both substrates, and then dicing is performed from the surface side of the other substrate. Such a structure and dicing method are disclosed in, for example, Japanese Patent Application Laid-Open No. 2001-352078.

JP 2001-352078 A

When a silicon wafer or a glass substrate is bonded to the back side of the silicon substrate on which the element is formed, the above-described conventional dicing method can be applied as it is, but the silicon wafer is attached to the surface side on which the element is formed. When bonded, it cannot be applied as it is.

When a diaphragm structure or an infrared sensitive film such as an infrared detecting element is formed on the surface, a silicon wafer may be bonded to the element forming side before dicing in order to protect it from dirt caused by cutting water during dicing. Conceivable. And this silicon wafer makes use of the characteristic of transmitting the infrared rays, and maintains the bonded state even in the chip after dicing. However, since the electrode pad provided on the element forming side is also covered with the silicon wafer as it is, the electrode pad is exposed by cutting the pasted substrate with a wide dicing width or by cutting twice. It is necessary to adopt a dicing method. Further, as a problem at the time of dicing in the bonded substrate, there is a case where cutting waste enters and adheres to the electrode pad or the like as a full cut. In the cleaning process, once adhered contamination is difficult to remove, which leads to discoloration of the electrode pad, and there is also concern about the influence on wire bonding.

  Japanese Patent Laid-Open No. 6-213708 describes a structure in which a silicon lid is previously placed on an infrared sensor in order to protect the infrared sensitive side of the infrared sensor from damage during dicing. Here, a silicon lid having a size that protects only the infrared sensitive part is prepared in advance, and the electrode pad is exposed by placing it on a necessary part, but this method complicates the manufacturing process. End up.

JP-A-6-213708

  In the semiconductor element formed on the wafer using the bonded substrate, the present invention provides a bonded substrate that can be easily exposed to the outside by a dicing process even when there is an electrode pad inside the bonded substrate. An object is to provide a dicing method.

  In order to achieve the above object, a method for dicing a bonded substrate is a semiconductor device composed of a rectangular chip, in which an element is formed and an electric signal from the element provided in at least one direction of the rectangle. Forming a plurality of semiconductor devices having electrode pads for outputting to the outside on a semiconductor wafer aligned at least in the row direction, and forming a semiconductor substrate having substantially the same size as the semiconductor wafer on the semiconductor wafer. A step of interposing a spacer on the surface side where the semiconductor element is formed, with a spacer provided surrounding the element region, and a step of bonding the electrode pad in the same semiconductor device from the surface side of the semiconductor substrate; And a half-cut dicing for separating in a row direction so that a dicing line of the semiconductor substrate crosses a region between the semiconductor element and the element And Ishingu step, from the surface side of the semiconductor wafer, and having a second dicing step of performing half-cut dicing based on the dicing line is separated into individual semiconductor devices in the row direction

  A plurality of the semiconductor devices are formed on the semiconductor wafer in alignment in the row and column directions, and further on dicing lines separated into individual semiconductor devices in the column direction from the surface side of the semiconductor substrate. A third dicing step for performing half-cut dicing, and a fourth dicing step for performing half-cut dicing based on dicing lines separated into individual semiconductor devices in the column direction from the surface side of the semiconductor wafer. It is characterized by having.

  Further, a plurality of the semiconductor devices are formed to be aligned in the row and column directions on the semiconductor wafer, and the spacers are continuously formed integrally with each other in the semiconductor devices arranged in the column direction. And a full-cut dicing process in which dicing reaching the spacer is performed on the semiconductor substrate and the semiconductor wafer based on dicing lines separated into individual semiconductor devices in a column direction.

  The plurality of semiconductor devices are formed in alignment in the row and column directions on the semiconductor wafer, and the electrode pads are respectively formed on at least two adjacent sides of the rectangle. A fifth cut is performed from the front surface side of the semiconductor substrate for separating in a column direction so that a dicing line of the semiconductor substrate crosses a region between the electrode pad and the element in the same semiconductor device. It has a dicing process and a sixth dicing process in which half-cut dicing is performed based on dicing lines separated into individual semiconductor devices in the column direction from the surface side of the semiconductor wafer.

  The element is an infrared detection element having an infrared absorption film formed on a surface thereof, and the substrate (the semiconductor substrate) to be placed thereon has an antireflection film, a light bandpass filter, or a substrate surface including one side or both sides. It is a silicon substrate on which any one of the light cutoff filters is formed.

    According to the manufacturing method of the present invention, in a semiconductor device formed on a wafer using a bonded substrate, even when there is an electrode pad inside the bonded substrate, it can be easily exposed to the outside by a dicing process. it can.

  Preferred embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a plan view showing a bonded substrate in a wafer state according to an embodiment of the present invention. 2A to 2D are process diagrams of a method for dividing a semiconductor device in a cross section taken along the line AB in FIG.

  As shown in FIG. 1, a plurality of semiconductor devices each having a rectangular chip shape are formed on a substrate 1 in the row and column directions. The substrate 1 shows a substrate after bonding, and is approximately the same size as the semiconductor wafer bonded to the surface of the semiconductor wafer on which the elements are formed and the semiconductor wafer on which the elements are formed. And a silicon substrate.

Next, with reference to FIGS. 2A to 2D, a method for manufacturing a semiconductor device according to the embodiment of the present invention will be described. As described above, the semiconductor device 2 is already formed on the semiconductor wafer 3, and each semiconductor device 2 is provided with the element 6 and the electrode pad 4. The element 6 is an infrared detecting element such as a thermopile, and as shown in FIG. 2, the membrane is formed on the surface of the silicon substrate so as to be supported by a heat insulating structure such as a diaphragm, and is formed on the membrane. And an infrared absorbing film. In the present embodiment, the element 6 is described as a structure having only an infrared detection element, but circuit elements such as a changeover switch and an amplifier may be mounted together on the same substrate, and these are collectively defined as an element. You can also.

As shown in FIG. 2A, the boundary of each semiconductor device 2 is a position indicated by a broken line, and this broken line also represents a dicing line at the time of singulation. Further, the protrusion formed on the surface of each semiconductor device 2 indicates an electrode pad 4 connected to the element 6 and outputting a signal therefrom.

Then, as shown in FIG. 2B, the semiconductor wafer 3 and the silicon substrate 8 are bonded together with an epoxy resin 7 with the element forming surface of the semiconductor wafer inside, and this epoxy resin 7 is shown in FIG. As shown, the element 6 is provided so as to surround the electrode pad 4 so as to protrude outside. In the present embodiment, the epoxy resin 7 is used as an adhesive and as a means for securing a space between the substrates. However, the same effect can be obtained with a structure in which an adhesive is applied to the top and bottom of a silicon resin or metal. Replacement is also possible. Further, the silicon substrate 8 may be formed by forming either an antireflection film, a light bandpass filter or a light cut-off filter on the surface thereof, or may be a Si / Ge / ZnS substrate. The thickness is preferably thin in view of the transmittance of infrared light, but is preferably 100 μm to 1 mm for handling. Further, in the present embodiment, the upper substrate (silicon substrate 8) has a flat plate shape without unevenness, but an upper space of the element 6 formed on the surface of the lower substrate (semiconductor wafer 3) is secured. Therefore, a shape having a recess recessed only in the region located directly above the element 6 may be used.

  Thereafter, as shown in FIG. 2C, dicing from the silicon substrate 8 side is performed. In the dicing process, first, the first cut portion 9 is formed by attaching the silicon substrate 8 to the tape from the semiconductor wafer 3 side and dicing the silicon substrate 8 from the exposed surface side along the Y direction of FIG. Dicing is performed at a position where the dicing line crosses the region between the electrode pad 4 and the element 6 in the same semiconductor device 2. That is, the region of the silicon substrate 8 located on the electrode pad 4 is connected to the silicon substrate region on the adjacent element, and the electrode pad 4 is exposed when separated.

  The dicing is half cut so that the remaining region 10 of the silicon substrate 8 has a thickness of about 20 μm to 200 μm. Although the epoxy resin 7 is formed on the electrode pad 4 of the semiconductor wafer 3, if dicing is performed according to the thickness of the silicon substrate 8, the semiconductor wafer 3 may be damaged due to an error caused by the accuracy of the entire apparatus. There is. Therefore, considering the parallelism including the parallelism of the dicing table, the consumption of the dicing blade, the thickness error of the sensor substrate, the resin thickness, the upper substrate thickness, and the thickness of the adhesive tape for dicing, the above silicon substrate It is necessary to form eight remaining regions 10.

  After the cutting according to the dicing line provided along the Y direction is completed, the cutting along the X is performed. In the X direction, the thickness of the remaining region 10 of the silicon substrate 8 is 20 μm as in the Y direction described above. The half-cut is about ~ 200 μm. The dicing line along the X direction is parallel to the paper surface of FIG. 2, and a specific structure cannot be shown in FIG. 2, but a supplementary explanation will be given with reference to FIG. FIG. 4 is a plan view of the bonded substrate similarly to FIG. 1, but is an enlarged view of only four elements and their peripheral parts for ease of explanation.

The electrode pad 4, the element 6, and the epoxy resin 7 in FIG. 2 correspond to the electrode pad 14, the element region 16, and the epoxy resin 17 in FIG. Reference numeral 18 denotes an internal metal wiring that electrically connects each element and the electrode pad. As the internal metal wiring, a wiring made of metal such as Al, Al alloy, Cu alloy or the like can be used, and the use of such a material is the same in the internal metal wiring in the second to fifth embodiments described later. . Reference numerals 20 and 21 indicated by broken lines in the figure are dicing lines 20 and 21 along the Y direction of the silicon substrate 8 (upper substrate), and reference numeral 22 indicated by a one-dot chain line in the figure is the semiconductor wafer 3 ( This is a dicing line 22 along the Y direction of the lower substrate. A broken line 24 is a dicing line 24 in the X direction. Since no bonding pad is disposed in the X direction, the dicing line is located at the same position in both the silicon substrate 8 (upper substrate) and the semiconductor wafer 3 (lower substrate). Since these are provided, these are collectively shown as a dicing line 24.

  Next, dicing from the semiconductor wafer 3 side is performed. Affixed to the tape from the silicon substrate 8 side, the semiconductor wafer 3 is diced along the dicing line 5 along the Y direction in FIG. This dicing is half cut so that the thickness of the remaining region 10 is about 20 μm to 200 μm, similarly to the silicon substrate 8 side.

After the cutting along all the dicing lines along the Y direction is completed, the line along the X direction is cut, and the thickness of the remaining region 10 of the silicon substrate 8 in the X direction is 20 μm as in the Y direction described above. The half-cut is about ~ 200 μm.

  When the substrate is attached upside down, the scribe area provided on the surface of the lower substrate (semiconductor wafer 3) becomes invisible, but it can be confirmed by using an infrared camera. Also, the reference scribe line can be cut in advance by aligning the upper and lower substrates in the X and Y directions, and the individual pitch can be cut based on the scribe line. Furthermore, instead of a full cut after the substrates are pasted together, both substrates are cut in advance along the reference line, and then both substrates are stacked and pasted along the cut, and then the individual pitch based on the cut position. Can also be cut.

  After the dicing of the semiconductor wafer 3 and the silicon substrate 8, based on the first cutting part 9 and the second cutting part 11, the semiconductor elements 2a to 2d are separated into pieces by a breaking process. Similarly, each of the semiconductor elements 2a to 2d has a structure in which silicon substrates 8a to 8d individually separated are bonded to each other through an epoxy resin. FIG. 2D shows a state after braking.

  FIG. 3 is a perspective view showing the outer shape of the chip of the semiconductor device singulated using the singulation method according to the embodiment of the present invention. As an example, the semiconductor device 2b in FIG. A chip made of a silicon substrate 8b is shown. The surfaces cut in the Y direction are aligned with the upper and lower substrates (semiconductor element 2b and silicon substrate 8b), but the surfaces cut in the X direction are shifted and are provided on the semiconductor device 2b. The electrode pad 4 is exposed. The semiconductor chip is connected to the exposed electrode pad 4 to the outside by a conventionally known technique such as wire bonding or a flexible substrate.

  FIG. 5 is a plan view of a bonded substrate according to the second embodiment of the present invention. Although reference numerals are omitted, the electrode pad 14, the element region 16, the epoxy resin 17, and the internal metal wiring 18 shown in FIG. 4 are the same in the structure shown in FIG. Also, the dicing lines 31a, 31b, 32a, and 32b along the Y direction correspond to the dicing lines 20, 21, 22, and 23 in FIG. 4, respectively, and the dicing method is the same.

  An important point different from FIG. 4 in the present embodiment is that the epoxy resin is formed continuously and integrally with each other in the semiconductor device arranged in the vertical direction in the drawing, and further, with respect to the silicon substrate and the semiconductor wafer. In the case of separation into individual semiconductor devices in the vertical direction, full-cut dicing reaching the epoxy resin is performed based on the dicing lines 30a, 30b, and 30c. When there is no electrode in that direction and resin is present in the entire dicing area, there is no need to consider the adhesion of contaminants caused by cutting water sneaking, and dicing reaching the epoxy resin can be performed.

FIG. 6 is a plan view of a bonded substrate according to the third embodiment of the present invention.
Although the reference numbers are omitted, the electrode pad 14, the element region 16, the epoxy resin 17, and the internal metal wiring 18 shown in FIG. 4 are the same in the structure shown in FIG. Further, the dicing lines 41b, 41d, 42a, and 42b in the Y direction correspond to the dicing lines 20, 21, 22, and 23 in FIG. 4, respectively, and the dicing method is the same. In the present embodiment, the difference from FIG. 4 is that the electrode pads are arranged not only on the right side but also on the side facing the paper, so that the dicing on the facing side (left side) is the same as on the right side. This is performed at a position where the dicing line 41 a crosses the region between the electrode pad and the element region 16.

  FIG. 7 is a plan view of a bonded substrate according to the fourth embodiment of the present invention. Although the reference numbers are omitted, the electrode pad 14, the element region 16, the epoxy resin 17, and the internal metal wiring 18 shown in FIG. 4 are the same in the structure shown in FIG. The dicing lines 52b, 52d, 53a, and 53b in the Y direction correspond to the dicing lines 20, 21, 22, and 23 in FIG. 4, respectively, and the dicing method is the same.

The difference from FIG. 4 in the present embodiment is that the electrode pads are arranged not only on the right side of the paper but also in all four directions on the facing side and the upper and lower sides. Similarly, it is performed at a position where the dicing line crosses the region between the electrode pad and the element region. That is, the dicing lines 52a, 52b, 52c and 52d in the Y direction and the dicing lines 51a, 51b, 51c and 51d in the X direction with respect to the silicon substrate are defined as crossing the region between the electrode pad and the element region. It is.

  FIG. 8 is a plan view of a bonded substrate according to the fifth embodiment of the present invention. Although the reference numbers are omitted, the electrode pad 14, the element region 16, the epoxy resin 17, and the internal metal wiring 18 shown in FIG. 4 are the same in the structure shown in FIG. Further, the dicing lines 41b, 41d, 42a, and 42b in the Y direction correspond to the dicing lines 20, 21, 22, and 23 in FIG. 4, respectively, and the dicing method is the same. In the present embodiment, the difference from FIG. 4 is that the electrode pad is arranged not only on the right side but also on the lower side with respect to the paper surface. It is performed at a position where the dicing lines 61a and 61b cross the area between the area 16 and the area 16.

  According to the dicing method in the individualized manufacturing method of the present embodiment, the water at the time of cutting did not enter the element surface inside the bonded substrate, and the braking could be carried out smoothly. In other words, in a semiconductor element formed on a wafer using a bonded substrate, even if there is an electrode pad inside the bonded substrate, it can be easily exposed to the outside by a dicing process.

It is a top view which shows the bonded substrate of the wafer state concerning embodiment of this invention. FIG. 2 is a process diagram of a method for singulating a semiconductor device in a cross section taken along line AB in FIG. 1. It is a perspective view which shows the chip | tip external shape of the semiconductor device singulated using the singulation method concerning embodiment of this invention. It is the top view which expanded the bonding board | substrate shown by FIG. 1 partially. It is a top view of the bonding board | substrate concerning 2nd embodiment of this invention. It is a top view of the bonding board | substrate concerning 3rd embodiment of this invention. It is a top view of the bonding board | substrate concerning the 4th embodiment of this invention. It is a top view of the bonding board | substrate concerning the 5th Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 2 Semiconductor device 3 Semiconductor wafer 4 Electrode pad 5 Dicing line 6 Element 7 Epoxy resin 8 Silicon substrate 9 1st cutting part 10 and 12 Left area 11 2nd cutting part

Claims (5)

A plurality of semiconductor devices each comprising a rectangular chip, each having a region where an element is formed, and an electrode pad that is provided in at least one direction of the rectangle and outputs an electric signal from the element to the outside Forming a semiconductor wafer aligned at least in the row direction;
Bonding a semiconductor substrate of approximately the same size as the semiconductor wafer on the surface side of the semiconductor wafer on which the semiconductor element is formed, with a spacer provided surrounding the element region, with a gap therebetween; ,
First half-cut dicing is performed to separate in a row direction from the surface side of the semiconductor substrate so that a dicing line of the semiconductor substrate crosses a region between the electrode pad and the element in the same semiconductor device. Dicing process,
A dicing method for a bonded substrate, comprising: a second dicing step in which half-cut dicing is performed based on dicing lines separated into individual semiconductor devices in a row direction from the surface side of the semiconductor wafer. A plurality of the semiconductor devices are formed in alignment in the row and column directions on the semiconductor wafer,
Furthermore, from the surface side of the semiconductor substrate, a third dicing step for performing half-cut dicing based on dicing lines separated into individual semiconductor devices in the column direction;
The bonded substrate according to claim 1, further comprising: a fourth dicing step of performing half-cut dicing based on dicing lines separated into individual semiconductor devices in a column direction from the surface side of the semiconductor wafer. Dicing method. A plurality of the semiconductor devices are formed in alignment in the row and column directions on the semiconductor wafer, and the spacers are formed integrally in a semiconductor device aligned in the column direction.
And a full-cut dicing process for dicing the semiconductor substrate and the semiconductor wafer to reach the spacer based on dicing lines separated into individual semiconductor devices in a column direction. Item 8. A method for dicing a laminated substrate according to Item 1. A plurality of the semiconductor devices are formed in alignment in the row and column directions on the semiconductor wafer, and the electrode pads are respectively formed on at least two adjacent sides of the rectangle,
Further, half-cut dicing is performed to separate the region between the electrode pad and the element in the same semiconductor device from the surface side of the semiconductor substrate in the column direction so that the dicing line of the semiconductor substrate crosses the region. Five dicing processes,
The bonded substrate according to claim 1, further comprising: a sixth dicing step of performing half-cut dicing based on a dicing line separated into individual semiconductor devices in a column direction from the surface side of the semiconductor wafer. Dicing method.   The element is an infrared detection element having an infrared absorption film formed on a surface thereof, and the semiconductor substrate is a silicon substrate having an antireflection film, a light bandpass filter, or a light cut-off filter formed on the surface thereof. The method for dicing a bonded substrate according to claim 1, wherein:

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