JP2007194298A - Semiconductor device, and method of manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To allow heat generated on a semiconductor layer to escape efficiently, and to form a semiconductor layer arranged on an insulator. <P>SOLUTION: After forming a first semiconductor layer 12 and a second one 13 on a semiconductor substrate 11, the first semiconductor layer 12 is removed by etching to form a cavity 20 between the semiconductor substrate 11 and the second semiconductor layer 13. The semiconductor substrate 11 and the second semiconductor layer 13 are oxidized thermally, thus forming an oxide film 21 on the upper and lower surfaces in the cavity 20 between the semiconductor substrate 11 and the second semiconductor layer 13, and forming a heat conductor layer 30 in the cavity 20. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and is particularly suitable for application to a field effect transistor formed on an SOI (Silicon On Insulator).

  Field effect transistors formed on an SOI substrate are attracting attention because of their ease of element isolation, latch-up freeness, and low source / drain junction capacitance. In particular, since a fully depleted SOI transistor can operate at low power consumption and at high speed and can be easily driven at a low voltage, research for operating the SOI transistor in a fully depleted mode has been actively conducted. Here, as the SOI substrate, for example, as disclosed in Patent Documents 1 and 2, a SIMOX (Separation by Implanted Oxgen) substrate or a bonded substrate is used.

Non-Patent Document 1 discloses a method by which an SOI transistor can be formed at a low cost by forming an SOI layer over a bulk substrate. In the method disclosed in Non-Patent Document 1, a Si / SiGe layer is formed on a Si substrate, and only the SiGe layer is selectively removed using a difference in selectivity between Si and SiGe. A cavity is formed between the Si substrate and the Si layer. Then, by performing thermal oxidation of Si exposed in the cavity, an SiO ₂ layer is embedded between the Si substrate and the Si layer, and a BOX layer is formed between the Si substrate and the Si layer.
JP 2002-299951 A Japanese Patent Application Laid-Open No. 2000-124092 T.A. Sakai et al. “Separation by Bonding Si Islands (SBSI) for LSI Applications”, Second International SiGe Technology and Device Meeting, Meeting Abstract, pp. 230-231, May (2004)

  However, in order to manufacture a SIMOX substrate, it is necessary to ion-implant high concentration oxygen into a silicon wafer. In order to manufacture a bonded substrate, it is necessary to bond two silicon wafers. For this reason, the SOI transistor has a problem that the cost is increased as compared with a field effect transistor formed in a bulk semiconductor. Furthermore, the back gate structure and the double gate structure have a drawback that they are difficult in terms of process and cost.

In addition, in ion implantation and bonding, there is a large variation in the thickness of the SOI layer, and when the SOI layer is thinned to produce a fully depleted SOI transistor, there are problems such as a large variation in characteristics of the field effect transistor. there were.
On the other hand, in the method disclosed in Non-Patent Document 1, since the SOI layer through which the current flows is covered with the SiO ₂ layer, the thermal conductivity around the SOI layer is reduced, and the escape field of the heat generated in the SOI layer is eliminated. Therefore, there has been a problem that characteristic deterioration and device destruction due to self-heating may occur.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device capable of forming a semiconductor layer disposed on an insulator while efficiently releasing heat generated in the semiconductor layer. Is to provide.

  In order to solve the above-described problem, according to a semiconductor device of one embodiment of the present invention, a semiconductor layer formed by epitaxial growth on a semiconductor substrate, and the semiconductor substrate so as to be sandwiched between upper and lower oxide layers, A thermal conductor layer embedded between the semiconductor layer; a gate electrode formed on the semiconductor layer; and a source / drain layer formed on the semiconductor layer and disposed on a side of the gate electrode. It is characterized by providing.

  As a result, an SOI transistor can be formed without using an SOI substrate, and a thermal conductor layer is embedded between the semiconductor substrate and the semiconductor layer so that the upper and lower sides are sandwiched between oxide layers. While suppressing the increase of the interface state of the semiconductor layer, the heat generated in the semiconductor layer can be efficiently released, and the increase in cost is suppressed, and the characteristic deterioration or device destruction caused by the self-heating of the SOI transistor Can be prevented.

According to the semiconductor device of one embodiment of the present invention, the thermal conductor layer is a PZT film, a perovskite crystal, a metal layer, or an alloy layer.
As a result, by embedding the thermal conductor layer between the semiconductor substrate and the semiconductor layer, the semiconductor layer can be disposed on the insulator, and the thermal conductivity around the semiconductor layer can be improved. Thus, it is possible to prevent characteristic deterioration and device destruction due to self-heating of the SOI transistor.

  According to the method for manufacturing a semiconductor device of one embodiment of the present invention, the step of forming the first semiconductor layer on the semiconductor substrate and the second semiconductor layer having an etching rate smaller than that of the first semiconductor layer A step of forming on one semiconductor layer; a step of forming a support for supporting the second semiconductor layer on the semiconductor substrate; and an exposed portion for exposing a part of the first semiconductor layer from the second semiconductor layer. Forming a cavity between the semiconductor substrate and the second semiconductor layer by selectively etching the first semiconductor layer through the exposed portion, thereby removing the cavity from which the first semiconductor layer has been removed. Forming an oxide film on the upper and lower surfaces of the cavity, and forming a thermal conductor layer embedded in the cavity so that the upper and lower sides are sandwiched between the oxide films. It is characterized by that.

  This makes it possible to remove the first semiconductor layer while leaving the second semiconductor layer, to form a cavity under the second semiconductor layer, and to support the second semiconductor layer with the support. The covering allows the second semiconductor layer to be supported on the semiconductor substrate by the support even when the cavity is formed under the second semiconductor layer. Further, by providing an exposed portion that exposes a part of the first semiconductor layer, the etching gas or the etchant is brought into contact with the first semiconductor layer even when the second semiconductor layer is stacked on the first semiconductor layer. The first semiconductor layer can be removed while leaving the second semiconductor layer, and a thermal conductor layer embedded in the cavity is formed so that the upper and lower sides are sandwiched by the oxide film. It becomes possible to do. For this reason, it becomes possible to arrange | position a 2nd semiconductor layer on an insulating layer, reducing generation | occurrence | production of the defect of a 2nd semiconductor layer, and without impairing the quality of a 2nd semiconductor layer, a 2nd semiconductor layer and a semiconductor substrate It is possible to achieve insulation between the second conductor layer and the heat generated in the second conductor layer while efficiently suppressing increase in the interface state of the second semiconductor layer. As a result, it is possible to form an SOI transistor on the second semiconductor layer while suppressing an increase in cost, and it is possible to prevent characteristic deterioration and device destruction due to self-heating of the SOI transistor. Become.

According to the method for manufacturing a semiconductor device of one embodiment of the present invention, the thermal conductor layer is coated with a liquid phase material in the cavity, and the liquid phase material is subjected to at least one heat treatment step. It is formed by firing or crystallization.
According to the method for manufacturing a semiconductor device of one embodiment of the present invention, the thermal conductor layer is formed by a sol-gel method or a spin-on method.

According to the method for manufacturing a semiconductor device of one embodiment of the present invention, the thermal conductor layer is formed by a metal organic decomposition method or a chemical vapor deposition method.
This makes it possible to form a thermal conductor layer between the semiconductor substrate and the semiconductor layer while ensuring the embeddability of the thermal conductor layer by using a general-purpose semiconductor manufacturing process. Even when the semiconductor layer is disposed on the semiconductor layer, heat generated in the semiconductor layer can be efficiently released while suppressing the complexity of the manufacturing process.

According to the method for manufacturing a semiconductor device of one embodiment of the present invention, the semiconductor substrate and the second semiconductor layer are Si, and the first semiconductor layer is SiGe.
As a result, it is possible to increase the etching rate of the first semiconductor layer compared to the semiconductor substrate and the second semiconductor layer while allowing lattice matching between the semiconductor substrate, the second semiconductor layer, and the first semiconductor layer. . For this reason, it becomes possible to form the second semiconductor layer with good crystal quality on the first semiconductor layer, and insulation between the second semiconductor layer and the semiconductor substrate is achieved without impairing the quality of the second semiconductor layer. It becomes possible.

In addition, according to the method for manufacturing a semiconductor device according to one aspect of the present invention, the SiGe is removed by wet etching using hydrofluoric acid, hydrofluoric acid superwater, ammonia perwater, or hydrofluoric acid perwater. To do.
Thereby, it becomes possible to secure a selection ratio between Si and SiGe, and SiGe can be removed while suppressing Si etching damage.

  Further, according to the method for manufacturing a semiconductor device according to one aspect of the present invention, the step of forming the thermal conductor layer embedded in the cavity includes the step of forming the thermal conductor layer so that the cavity is embedded. The step of depositing on the entire surface of the semiconductor substrate and at least one of isotropic etching and anisotropic etching are used so that the thermal conductor layer remains under the second semiconductor layer. And a step of selectively removing the upper thermal conductor layer.

Thereby, in order to embed the thermal conductor layer in the cavity, even when the thermal conductor layer is deposited on the entire surface of the semiconductor substrate, the unnecessary thermal conductor remains while the thermal conductor layer remains in the cavity. The layer can be removed, and the thermal conductor layer can be embedded between the semiconductor substrate and the semiconductor layer while suppressing the complexity of the manufacturing process.
Further, according to the method of manufacturing a semiconductor device according to one aspect of the present invention, the step of forming the thermal conductor layer embedded in the cavity includes the step of forming the thermal conductor layer so that the cavity is embedded. A step of depositing on the entire surface of the semiconductor substrate, and back-etching the entire surface of the thermal conductor layer so that the thermal conductor layer remains under the second semiconductor layer. And a step of removing the layer.

  Accordingly, even when the thermal conductor layer is deposited on the entire surface of the semiconductor substrate in order to embed the thermal conductor layer in the cavity, the entire surface of the thermal conductor layer is simply back-etched. An unnecessary thermal conductor layer can be removed while leaving the layer in the cavity, and the thermal conductor layer can be embedded between the semiconductor substrate and the semiconductor layer while suppressing the complexity of the manufacturing process. It becomes possible.

Hereinafter, a semiconductor device manufacturing method according to an embodiment of the present invention will be described with reference to the drawings.
FIGS. 1A to 12A are plan views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIGS. 1B to 12B are FIGS. Sectional views cut along lines A1-A1 ′ to A12-A12 ′ in FIG. 12A, and FIGS. 1C to 12C show B1- in FIG. 1A to FIG. It is sectional drawing cut | disconnected by B1'-B12-B12 'line | wire, respectively.

  In FIG. 1, a first semiconductor layer 12 is formed on a semiconductor substrate 11 by epitaxial growth, and a second semiconductor layer 13 is formed on the first semiconductor layer 12 by epitaxial growth. The first semiconductor layer 12 can be made of a material having an etching rate larger than that of the semiconductor substrate 11 and the second semiconductor layer 13, and the material of the semiconductor substrate 11, the first semiconductor layer 12 and the second semiconductor layer 13 can be used. For example, a combination selected from Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, ZnSe, and the like can be used. In particular, when the semiconductor substrate 11 is Si, it is preferable to use SiGe as the first semiconductor layer 12 and Si as the second semiconductor layer 13. Thereby, it is possible to ensure the lattice matching between the first semiconductor layer 12 and the second semiconductor layer 13 while ensuring the selection ratio between the first semiconductor layer 12 and the second semiconductor layer 13. it can. Further, as the first semiconductor layer 12, a single crystal semiconductor layer, a polycrystalline semiconductor layer, an amorphous semiconductor layer, or a porous semiconductor layer may be used. Instead of the first semiconductor layer 12, a metal oxide film such as γ-aluminum oxide capable of forming a single crystal semiconductor layer by epitaxial growth may be used. Moreover, the film thickness of the 1st semiconductor layer 12 and the 2nd semiconductor layer 13 can be about 1-200 nm, for example.

  Then, a base oxide film 14 is formed on the surface of the second semiconductor layer 13 by thermal oxidation of the second semiconductor layer 13. Then, an antioxidant film 15 is formed on the entire surface of the base oxide film 14 by a method such as CVD. As the antioxidant film 15, for example, a silicon nitride film can be used. In addition to the function of preventing the second semiconductor layer 13 from being oxidized, as a stopper layer for a planarization process by CMP (Chemical Mechanical Polishing). It can also function.

  Next, as shown in FIG. 2, the semiconductor substrate 11 is patterned by patterning the antioxidant film 15, the base oxide film 14, the second semiconductor layer 13, and the first semiconductor layer 12 using a photolithography technique and an etching technique. A groove 16 is formed to expose a part of the groove. When a part of the semiconductor substrate 11 is exposed, the etching may be stopped on the surface of the semiconductor substrate 11, or the semiconductor substrate 11 may be over-etched to form a recess in the semiconductor substrate 1. . Further, the arrangement position of the groove 16 can correspond to a part of the element isolation region of the second semiconductor layer 13.

  Next, as shown in FIG. 3, a cap layer 17 is formed on the side walls of the first semiconductor layer 12 and the second semiconductor layer 13 by a method such as CVD. Here, as the cap layer 17, for example, a silicon oxide film or a silicon film can be used. Then, a part of the first semiconductor layer 12 and the second semiconductor layer 13 is thermally oxidized with the cap layer 17 formed on the side walls of the first semiconductor layer 12 and the second semiconductor layer 13. Here, after the cap layer 17 is formed, the first semiconductor layer 12 and the second semiconductor layer 13 are subjected to thermal oxidation, thereby suppressing outward diffusion of components contained in the first semiconductor layer 12. Therefore, a semiconductor / oxide film interface with few interface states can be formed at least on the side wall of the second semiconductor layer 13. At the same time, it is possible to prevent the surroundings from being contaminated by components contained in the first semiconductor layer 12.

  Next, as shown in FIG. 4, a support 18 embedded in the groove 16 is formed so as to cover the entire surface of the substrate by a method such as CVD. The support 18 is also formed on the side walls of the first semiconductor layer 12 and the second semiconductor layer 13 in the groove 16, and can support the second semiconductor layer 13 on the semiconductor substrate 11. The support 18 formed so as to cover the entire substrate needs to support the second semiconductor layer 13 while maintaining the flatness by suppressing the bending of the second semiconductor layer 13 and the like. Therefore, it is preferable to set the film thickness to 400 nm or more in order to ensure the mechanical strength. Further, as the material of the support 18, an insulator such as a silicon oxide film can be used.

  Next, as shown in FIG. 5, by patterning the support 18, the antioxidant film 15, the base oxide film 14, the second semiconductor layer 13, and the first semiconductor layer 12 using photolithography technology and etching technology, A groove 19 exposing a part of the first semiconductor layer 12 is formed. Here, the arrangement position of the groove 19 can correspond to a part of the element isolation region of the second semiconductor layer 13.

  When a part of the first semiconductor layer 12 is exposed, the etching may be stopped on the surface of the first semiconductor layer 12, or the first semiconductor layer 12 is over-etched to form a recess in the first semiconductor layer 12. May be formed. Alternatively, the surface of the semiconductor substrate 11 may be exposed through the first semiconductor layer 12 in the groove 19. Here, by stopping the etching of the first semiconductor layer 12 halfway, it is possible to prevent the surface of the semiconductor substrate 11 in the groove 19 from being exposed. Therefore, when the first semiconductor layer 12 is removed by etching, the time during which the semiconductor substrate 11 in the groove 19 is exposed to the etching solution or the etching gas can be reduced, and the overetching of the semiconductor substrate 11 in the groove 19 can be reduced. Can be suppressed.

Next, as shown in FIG. 6, the first semiconductor layer 12 is removed by etching by bringing an etching gas or an etchant into contact with the first semiconductor layer 12 through the groove 19, and the semiconductor substrate 11 and the second semiconductor layer are removed. A cavity 20 is formed between the first and second cavities 13.
Here, by providing the support 18 in the groove 16, the second semiconductor layer 13 can be supported on the semiconductor substrate 11 even when the first semiconductor layer 12 is removed, and the groove 16. By providing the groove 19 separately, the etching gas or the etchant can be brought into contact with the first semiconductor layer 12 below the second semiconductor layer 13. Therefore, it is possible to form a cavity between the second semiconductor layer 13 and the semiconductor substrate 11 without impairing the quality of the second semiconductor layer 13.

  When the semiconductor substrate 11 and the second semiconductor layer 13 are Si and the first semiconductor layer 12 is SiGe, hydrofluoric acid (a mixed solution of hydrofluoric acid, nitric acid, and water) is used as the etchant for the first semiconductor layer 12. preferable. Thereby, it is possible to remove the first semiconductor layer 12 while suppressing overetching of the semiconductor substrate 11 and the second semiconductor layer 13. Further, as the etchant for the first semiconductor layer 12, hydrofluoric acid overwater, ammonia overwater, hydrofluoric acid overwater, or the like may be used.

  Further, before the first semiconductor layer 12 is removed by etching, the first semiconductor layer 12 may be made porous by a method such as anodic oxidation, or by ion implantation into the first semiconductor layer 12, The first semiconductor layer 12 may be made amorphous, or a P-type semiconductor substrate may be used as the semiconductor substrate 11. Thereby, the etching rate of the first semiconductor layer 12 can be increased, and the etching area of the first semiconductor layer 12 can be expanded.

  Next, as shown in FIG. 7, by oxidizing the semiconductor substrate 11 and the second semiconductor layer 13, oxide films are formed on the upper and lower surfaces in the cavity 20 between the semiconductor substrate 11 and the second semiconductor layer 13. 21 is formed. The film thickness of the oxide film 21 can be set to 100 mm, for example. As a result, it is possible to dispose the second semiconductor layer 13 on the insulator while suppressing an increase in the interface state of the second semiconductor layer 13, and to suppress the deterioration of the subthreshold slope value. An SOI transistor can be formed in the layer 13.

  In the method of FIG. 7, the oxide film 21 is formed on the upper and lower surfaces in the cavity 20 between the semiconductor substrate 11 and the second semiconductor layer 13 by performing thermal oxidation of the semiconductor substrate 11 and the second semiconductor layer 13. Although the forming method has been described, an insulating film may be formed on the upper and lower surfaces in the cavity 20 between the semiconductor substrate 11 and the second semiconductor layer 13 by the CVD method. Thereby, it is possible to form a material other than the oxide film on the upper and lower surfaces in the cavity 20 between the semiconductor substrate 11 and the second semiconductor layer 13 while preventing the film reduction of the second semiconductor layer 13. Become.

  Further, by making the arrangement positions of the grooves 16 and 19 correspond to the element isolation regions of the second semiconductor layer 13, it is possible to perform element isolation in the horizontal direction and the vertical direction of the second semiconductor layer 13, and By embedding the support 18 therein, it is not necessary to secure the support 18 that supports the second semiconductor layer 13 on the semiconductor substrate 1 in the active region. Therefore, an SOI transistor can be formed while suppressing an increase in the number of processes, and an increase in chip size can be suppressed, so that the cost of the SOI transistor can be reduced.

  Next, as shown in FIG. 8, a high thermal conductive material is embedded in the cavity 20 in which the oxide film 21 is formed by a method such as a sol-gel method, a metal organic decomposition method, a chemical vapor deposition method, or a spin-on method. Thus, the heat conductor layer 30 is formed in the cavity 20 in which the oxide film 21 is formed. As the heat conductor layer 30, for example, a PZT film or a perovskite crystal may be used, or a metal such as Al, Cu, W, Mo, Ta, Ti, or Zr may be used. In addition, a metal nitride such as TaN or TiN may be used, or an alloy such as W silicide or Ni silicide may be used. For example, when a PZT film is formed as a heat conductor layer, a PZT solution is applied in the cavity 20 where the oxide film 21 is formed and baked at 150 ° C. to 300 ° C., and then 500 ° C. to 700 ° C. Recrystallization is performed by applying a heat treatment process of a certain degree.

Thus, by using a general-purpose semiconductor manufacturing process, the thermal conductor layer 30 can be formed between the semiconductor substrate 11 and the second semiconductor layer 13 while ensuring the embeddability of the thermal conductor layer 30. Even when the second semiconductor layer 13 is disposed on the insulator, heat generated in the second semiconductor layer 13 can be efficiently released while suppressing the complication of the manufacturing process.
Next, as shown in FIG. 9, the thermal conductor layer 30 is selectively etched using isotropic etching such as wet etching or plasma etching, anisotropic etching, or an appropriate combination thereof. (2) The surface and side walls of the support 18 and the heat conductor layer 30 on the side walls of the second semiconductor layer 13 are removed while leaving the heat conductor layer 30 under the semiconductor layer 13.

  The entire surface of the heat conductor layer 30 is back-etched while using isotropic etching or an appropriate combination of isotropic etching and anisotropic etching, so that the heat conductor layer 30 is formed below the second semiconductor layer 13. Alternatively, the heat conductor layer 30 on the surface and side walls of the support 18 and the side walls of the second semiconductor layer 13 may be removed so as to remain. Accordingly, even when the thermal conductor layer 30 is deposited on the entire surface of the semiconductor substrate 11 in order to embed the thermal conductor layer 30 in the cavity 20, the entire surface of the thermal conductor layer 30 is simply back-etched. Thus, the unnecessary heat conductor layer 30 can be removed while leaving the heat conductor layer 30 in the cavity 20, and the semiconductor substrate 11 and the second semiconductor layer can be reduced while suppressing the complexity of the manufacturing process. It is possible to embed the thermal conductor layer 30 between them.

Next, as shown in FIG. 10, a buried insulating film 22 buried in the groove 19 is formed so as to cover the entire surface of the support 18 by a method such as CVD. For example, an insulator such as a silicon oxide film can be used as the buried insulating film 22.
Next, as shown in FIG. 11, the buried insulating film 22 and the support 18 are thinned by a method such as CMP or etch back, and planarization by CMP is stopped using the antioxidant film as a stopper layer. Subsequently, the surface of the second semiconductor layer 13 is exposed by removing the base oxide film 14 and the antioxidant film 15.

  Next, as illustrated in FIG. 12, the second semiconductor layer 13 is patterned by using a photolithography technique and an etching technique, thereby forming an opening 31 in the second semiconductor layer 13 that exposes a part of the oxide film 21. To do. Then, the gate insulating film 23 is formed on the surface of the second semiconductor layer 13 by performing thermal oxidation of the surface of the second semiconductor layer 13. Then, a polycrystalline silicon layer is formed on the second semiconductor layer 13 on which the gate insulating film 23 is formed by a method such as CVD. Then, the gate electrode 24 is formed on the second semiconductor layer 13 by patterning the polycrystalline silicon layer using a photolithography technique and an etching technique.

  Next, by using the gate electrode 24 as a mask, impurities such as As, P, and B are ion-implanted into the second semiconductor layer 13 to thereby form LDDs composed of low-concentration impurity introduction layers respectively disposed on both sides of the gate electrode 24. A layer is formed on the second semiconductor layer 13. Then, an insulating layer is formed on the second semiconductor layer 13 on which the LDD layer is formed by a method such as CVD, and the insulating layer is etched back using anisotropic etching such as RIE. Sidewalls 25 are formed on the side walls. Then, impurities such as As, P, and B are ion-implanted into the second semiconductor layer 13 using the gate electrode 24 and the sidewall 25 as a mask, thereby introducing high-concentration impurities respectively disposed on the side of the sidewall 25. A source layer 26 a and a drain layer 26 b made of layers are formed in the second semiconductor layer 13.

  Next, an interlayer insulating layer 32 is deposited on the gate electrode 24 by a method such as CVD. Then, a back gate contact electrode 33 d embedded in the interlayer insulating layer 32 and the oxide film 21 and connected to the thermal conductor layer 30 through the opening 30 is formed on the interlayer insulating layer 32. Further, a source contact electrode 33 a, a drain contact electrode 33 b and a gate contact electrode 33 c embedded in the interlayer insulating layer 32 and connected to the source layer 26 a, the drain layer 26 b and the gate electrode 24 are formed on the interlayer insulating layer 32.

  As a result, it is possible to dispose the second semiconductor layer 13 on the insulating layer while reducing the occurrence of defects in the second semiconductor layer 13, so that the quality of the second semiconductor layer 13 is not impaired. 13 and the semiconductor substrate 11 can be insulated, and heat generated in the second semiconductor layer 13 is efficiently released while suppressing an increase in the interface state of the second semiconductor layer 13. Can do. As a result, it is possible to form an SOI transistor on the second semiconductor layer 13 while suppressing an increase in cost, and it is possible to prevent characteristic deterioration and device destruction due to self-heating of the SOI transistor. It becomes.

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Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 Semiconductor substrate, 12 1st semiconductor layer, 13 2nd semiconductor layer, 14 Base oxide film, 15 Antioxidation film, 16, 19 Groove, 17 Cap layer, 18 Support body, 20 Cavity part, 21 Oxide film, 22 Embedded insulation Body, 23 gate insulating film, 24 gate electrode, 25 sidewall, 26a source layer, 26b drain layer, 30 thermal conductor layer, 31 opening, 33a source contact, 33b drain contact, 33c gate contact, 33d back gate contact

Claims (10)

A semiconductor layer formed by epitaxial growth on a semiconductor substrate;
A thermal conductor layer embedded between the semiconductor substrate and the semiconductor layer so as to be sandwiched between upper and lower oxide layers;
A gate electrode formed on the semiconductor layer;
A semiconductor device comprising: a source / drain layer formed on the semiconductor layer and disposed on a side of the gate electrode.   2. The semiconductor device according to claim 1, wherein the thermal conductor layer is a PZT film, a perovskite crystal, a metal layer, or an alloy layer. Forming a first semiconductor layer on a semiconductor substrate;
Forming a second semiconductor layer having a lower etching rate than the first semiconductor layer on the first semiconductor layer;
Forming a support for supporting the second semiconductor layer on the semiconductor substrate;
Forming an exposed portion for exposing a part of the first semiconductor layer from the second semiconductor layer;
Forming a cavity from which the first semiconductor layer is removed between the semiconductor substrate and the second semiconductor layer by selectively etching the first semiconductor layer through the exposed portion;
Forming oxide films on the upper and lower surfaces of the cavity,
Forming a thermal conductor layer embedded in the cavity so that the upper and lower sides are sandwiched between the oxide films.   4. The thermal conductor layer is formed by applying a liquid phase material in the cavity and baking or crystallizing the liquid phase material in at least one heat treatment step. Semiconductor device manufacturing method.   4. The method of manufacturing a semiconductor device according to claim 3, wherein the thermal conductor layer is formed by a sol-gel method or a spin-on method.   4. The method of manufacturing a semiconductor device according to claim 3, wherein the thermal conductor layer is formed by a metal organic decomposition method or a chemical vapor deposition method.   7. The method of manufacturing a semiconductor device according to claim 3, wherein the semiconductor substrate and the second semiconductor layer are Si, and the first semiconductor layer is SiGe.   The method of manufacturing a semiconductor device according to claim 3, wherein the SiGe is removed by wet etching using hydrofluoric acid, hydrofluoric acid perwater, ammonia perwater, or hydrofluoric acid perwater. . Forming the thermal conductor layer embedded in the cavity,
Depositing a heat conductor layer on the entire surface of the semiconductor substrate so as to be embedded in the cavity;
By using at least one of isotropic etching and anisotropic etching, the thermal conductor layer on the semiconductor substrate is selectively removed so that the thermal conductor layer remains under the second semiconductor layer. The method for manufacturing a semiconductor device according to claim 3, further comprising a step of: Forming the thermal conductor layer embedded in the cavity,
Depositing a heat conductor layer on the entire surface of the semiconductor substrate so as to be embedded in the cavity;
Back-etching the entire surface of the heat conductor layer to remove the heat conductor layer on the semiconductor substrate so that the heat conductor layer remains under the second semiconductor layer. A method for manufacturing a semiconductor device according to any one of claims 3 to 9.

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