JP2007179042A5

JP2007179042A5 -

Info

Publication number: JP2007179042A5
Application number: JP2006325739A
Authority: JP
Filing date: 2006-12-01
Publication date: 2010-01-21
Anticipated expiration: 2026-12-01

Claims

A transistor, a storage capacitor, a first switch, a second switch, and a third switch;
One of the source electrode and the drain electrode of the transistor is electrically connected to the pixel electrode, and one of the source electrode and the drain electrode is electrically connected to the third wiring through the third switch,
The other of the source electrode and the drain electrode of the transistor is electrically connected to the first wiring,
A gate electrode of the transistor is electrically connected to a second wiring through the second switch, and the gate electrode is electrically connected to a fourth wiring through the first switch;
One of the source electrode and the drain electrode of the transistor is electrically connected to the gate electrode of the transistor through the storage capacitor.

In claim 1 ,
Any third wiring, before the first switch controlling the first wiring through the third switch to control the switch of the wiring to the wiring and the next line to control the third switch to control the wire line A semiconductor device characterized by the above.

In claim 1 or 2 ,
Wherein a said first switch to said third switch is a transistor.

A transistor, a storage capacitor, a first switch, a second switch, a third switch, and a fourth switch;
One of the source electrode and the drain electrode of the transistor is electrically connected to the pixel electrode, and one of the source electrode and the drain electrode is electrically connected to the third wiring through the third switch,
The other of the source electrode and the drain electrode of the transistor is electrically connected to the first wiring,
The gate electrode of the transistor, the second is wired electrically connected via the fourth switch and the second switch, and the gate electrode through the fourth switch and the first switch Electrically connected to the fourth wiring,
One of the source electrode and the drain electrode of the transistor is electrically connected to the gate electrode of the transistor through the storage capacitor and the fourth switch.

A transistor, a storage capacitor, a first switch, a second switch, a third switch, and a fourth switch;
One of the source electrode and the drain electrode of the transistor is electrically connected to the pixel electrode, and one of the source electrode and the drain electrode is electrically connected to the third wiring through the third switch,
The other of the source electrode and the drain electrode of the transistor is electrically connected to the first wiring,
The gate electrode of the transistor, and through said second switch is a second wiring electrically connected, and the gate electrode is the fourth wiring through the fourth switch and the first switch Electrically connected,
One of the source electrode and the drain electrode of the transistor is electrically connected to the gate electrode of the transistor through the storage capacitor and the fourth switch.

A transistor, a storage capacitor, a first switch, a second switch, a third switch, and a fourth switch;
One of the source electrode and the drain electrode of the transistor is electrically connected to the pixel electrode, and one of the source electrode and the drain electrode is electrically connected to the third wiring through the third switch,
The other of the source electrode and the drain electrode of the transistor is electrically connected to the first wiring through the fourth switch,
A gate electrode of the transistor is electrically connected to a second wiring through the second switch, and the gate electrode is electrically connected to a fourth wiring through the first switch;
One of the source electrode and the drain electrode of the transistor is electrically connected to the gate electrode of the transistor through the storage capacitor.

A transistor, a storage capacitor, a first switch, a second switch, a third switch, and a fourth switch;
One of the source electrode and the drain electrode of the transistor is electrically connected to the pixel electrode through the fourth switch, and one of the source electrode and the drain electrode is connected to the fourth switch and the third switch. Electrically connected to the third wiring via
The other of the source electrode and the drain electrode of the transistor is electrically connected to the first wiring,
A gate electrode of the transistor is electrically connected to a second wiring through the second switch, and the gate electrode is electrically connected to a fourth wiring through the first switch;
One of the source electrode and the drain electrode of the transistor is electrically connected to the gate electrode of the transistor through the fourth switch and the storage capacitor.

In any one of Claims 4 thru | or 7 ,
The semiconductor device, wherein the third wiring is the same as a wiring for controlling the third switch.

In any one of Claims 4 thru | or 7 ,
Any third wiring, before the first wiring for controlling the switch to interconnect to control the fourth switch and a first control switch wiring or wiring for controlling the fourth switch of the next line after the line A semiconductor device characterized by the above.

In any one of Claims 4 thru | or 9 ,
Wherein a first switch to the fourth switch are transistors.

In any one of Claims 4 thru | or 9,
The semiconductor device is characterized in that a channel length of the transistor is larger than a channel width of the transistor.

In any one of Claims 4 thru | or 9,
A channel length of the transistor is 10 μm to 50 μm.

In any one of Claims 4 thru | or 9,
The transistor has a channel length of 15 μm to 40 μm.

In any one of Claims 4 thru | or 9 ,
The semiconductor device is a thin film transistor.

In any one of Claims 4 thru | or 9 and 14 ,
The semiconductor device is an N-channel transistor.

In any one of claims 4 to 9, 14 and 15 ,
A semiconductor device, wherein the semiconductor layer of the transistor is made of an amorphous semiconductor film.

In any one of Claims 4 thru | or 9 and 14 thru | or 16 ,
A semiconductor device, wherein the semiconductor layer of the transistor is made of amorphous silicon.

In any one of claims 4 to 9, 14 and 15 ,
A semiconductor device, wherein the semiconductor layer of the transistor is made of a crystalline semiconductor film.

In any one of Claims 4 thru | or 9 and 14 thru | or 18 ,
The semiconductor device is characterized in that the potential supplied to the second wiring is higher than the potential supplied to the third wiring, and the difference is larger than the threshold voltage of the transistor.

In any one of Claims 4 thru | or 9 and 14 ,
The semiconductor device is a P-channel transistor.

In any one of claims 4 to 9, 14 and 20 ,
The potential supplied to the second wiring is lower than the potential supplied to the third wiring, and the difference is larger than the absolute value of the threshold voltage of the transistor. apparatus.

One of the source electrode and the drain electrode is electrically connected to the first wiring, the other of the source electrode and the drain electrode is electrically connected to the third wiring, and the gate electrode is the second wiring and the fourth wiring. A transistor electrically connected to
A holding capacitor for holding a gate-source voltage of the transistor;
Means for applying a first potential supplied to the second wiring and a second potential supplied to the third wiring to the storage capacitor to hold the first voltage in the storage capacitor; ,
Means for discharging the voltage of the holding capacitor to a second voltage;
A potential obtained by adding a third voltage to the first potential is applied to the storage capacitor from the fourth wiring, and a fifth voltage obtained by adding the second voltage and the fourth voltage is applied to the storage capacitor. Means for holding,
And a means for supplying a current set to the transistor in accordance with the fifth voltage to a load.

One of the source electrode and the drain electrode is electrically connected to the first wiring, the other of the source electrode and the drain electrode is electrically connected to the third wiring, and the gate electrode is the second wiring and the fourth wiring. A transistor electrically connected to
A holding capacitor for holding a gate-source voltage of the transistor;
Means for applying a first potential supplied to the second wiring and a second potential supplied to the third wiring to the storage capacitor to hold the first voltage in the storage capacitor; ,
Means for discharging the voltage of the storage capacitor to the threshold voltage of the transistor;
A potential obtained by adding a second voltage to the first potential is applied to the storage capacitor from the fourth wiring, and a fourth voltage obtained by adding the threshold voltage of the transistor and a third voltage is added to the storage capacitor. Means for holding in the holding capacity;
And means for supplying a current set to the transistor in accordance with the fourth voltage to a load.

According to claim 22 or 23,
The transistor is an N-channel transistor,
The semiconductor device according to claim 1, wherein the first potential is higher than the second potential, and a difference between the first potential is larger than a threshold voltage of the transistor.

In claim 22 or 23 ,
The transistor is a P-channel transistor,
The semiconductor device according to claim 1, wherein the first potential is lower than the second potential, and the difference is larger than an absolute value of a threshold voltage of the transistor.

In any one of claims 22 to 25 ,
The semiconductor device according to claim 1, wherein the load is a light emitting element.

In any one of claims 1 to 26 ,
The semiconductor device, wherein the storage capacitor is a capacitor.

A pixel including a transistor, a first switch, a second switch, a first wiring, and a second wiring;
One of a source electrode and a drain electrode of the transistor is electrically connected to the pixel electrode and the second switch;
The other of the source electrode and the drain electrode of the transistor is electrically connected to the first wiring,
A gate electrode of the transistor is electrically connected to the second wiring through the first switch;
The semiconductor device is characterized in that a signal in accordance with the gradation of the pixel is input to the gate electrode of the transistor.

Display device characterized by having the semiconductor device according to any one of claims 1 to 28.

An electronic apparatus comprising the display device according to claim 29 in a display portion.