JP2007175181A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a game machine capable of making a player interested in a game even if the game of the player becomes monotonous because the game state is a special game state (an FT (Free Time) game state). <P>SOLUTION: The game machine 1 counts the number of times of determination of failure as an internally elected winning role when the game state is the special game state, and a privilege is given to the player based on the counted number of times. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a gaming machine.

  Conventionally, a plurality of reels in which a plurality of symbols are drawn on each peripheral surface, and a symbol display window that is provided in correspondence with each reel and displays a part of the symbols drawn on the peripheral surface of each reel; The reels rotate based on the player's input of game value such as medals and the operation of the start lever (hereinafter referred to as “start operation”), and the player operates the stop button (hereinafter referred to as “start operation”). Based on the “stop operation”), a gaming machine (so-called “pachi-slot”) in which each reel is stopped and a symbol is displayed in a symbol display window until one symbol is played is known. The gaming machine is a combination of symbols (hereinafter referred to as a “combination”) that satisfies a condition for giving a player a predetermined gaming value or for shifting a gaming state from one gaming state to another gaming state. Is displayed on the active line of the symbol display window, the processing corresponding to the combination is performed. Hereinafter, a combination that is stopped and displayed on the effective line of the symbol display window may be referred to as a display combination.

  The role includes replay that enables replay without newly adding game value, and a big bonus (hereinafter referred to as “BB”) that changes the game state to a game state that is more advantageous to the player than the normal game state. )) And losing.

  In addition, based on the player's start operation, the mainstream gaming machine currently draws one or more roles from among a group of roles that are configured in advance within the gaming machine (hereinafter referred to as “internal lottery”). )), And the reel stop control is performed based on the winning combination (hereinafter referred to as “internal winning combination”) and the player's stop operation. In particular, when the internal winning combination is a replay, the replay is controlled to be a display combination regardless of the timing at which the player performs a stop operation.

  Furthermore, the gaming machine has a normal gaming state (hereinafter sometimes referred to as a “general gaming state”) as a gaming state that affects the internal lottery, and internal winning of replay with a higher probability than the normal gaming state. Some have a special gaming state (hereinafter, sometimes referred to as “FT (free time) gaming state”).

In such a gaming machine, the number of games for transitioning the gaming state to the FT gaming state is determined by lottery, and there is a condition for transitioning the gaming state to the FT gaming state before the unit game of the number of gaming is performed. A gaming machine that transitions the gaming state to the FT gaming state when satisfied, or a gaming machine that determines the number of games that can be played when the gaming state is the FT gaming state by lottery (for example, Patent Document 1).
JP 2002-360787 A

  However, in the above-mentioned gaming machine, when the gaming state is the FT gaming state, it is assumed that the replay is internally won with a high probability, and further, when the replay is internally won, the player performs a stop operation at any timing However, since replay serves as a display role, the player's game becomes monotonous and the player's interest may be gradually lost.

  The present invention has been made in view of the above problems, and even if the player's game becomes monotonous because the game state is a special game state, it is possible to improve the interest of the player. An object is to provide a game machine that can be used.

  In order to solve the above-described problems, the gaming machine according to the present invention has variable display means (for example, reels 3L, 3C, 3R and display windows 4L, 4C described later) having a plurality of variable display units for variably displaying a plurality of symbols. 4R), a stop operation means (for example, stop buttons 7L, 7C, 7R, which will be described later) used for stopping variable display of the variable display section, and a lottery from a predetermined role group including a loser. Based on the winning combination determining means (for example, main CPU 31, random number generator 36 and sampling circuit 37, which will be described later), the operation timing for the stop operation means, and the internal winning combination determined by the winning combination determining means. Stop control means for stopping variable display of each variable display section (for example, a main CPU 31, a motor drive circuit 39, and stepping motors 49L, 49 described later) 49R), and the game state is determined according to a condition in which a role (for example, replay) that enables replay without a new game value being input is more likely than the normal game state (for example, general game state). Counting means (for example, an image control microcomputer 72 to be described later) counts the number of times that the winning combination determination means determines the lost as an internal winning combination in the special gaming state (for example, FT gaming state) in which the lottery is performed. ) And privilege granting means (for example, a liquid crystal display device 5, an image control microcomputer 72 and an image control IC 76 described later) for granting a privilege based on the number of times counted by the counting means.

  With this configuration, in the gaming machine according to the present invention, the lottery means according to the condition that the counting means wins with a high probability that the game state can be re-played without newly adding a game value compared to the normal game state. In the special gaming state in which the winning combination determining means counts the number of times that the winning combination is determined as an internal winning combination, and the privilege granting means grants a privilege based on the counted number.

  Therefore, according to the gaming machine of the present invention, even if the player's game becomes monotonous because the gaming state is the special gaming state, the loss is determined as the internal winning combination during the special gaming state. By giving a privilege to the player based on the number of times played, the player's interest can be improved.

  In addition, in the gaming machine according to the present invention, the privilege granting unit generates a two-dimensional code by encoding information advantageous to the player (for example, an image control microcomputer 72 described later), Code display means for displaying the two-dimensional code generated by the code generation means (for example, an image control microcomputer 72 and a liquid crystal display device 5 to be described later).

  With this configuration, the gaming machine of the present invention displays a two-dimensional code generated by encoding information advantageous to the player as a privilege to the player based on the number of times counted by the counting means.

  Therefore, according to the gaming machine of the present invention, since a two-dimensional code generated by encoding information advantageous to the player is displayed, the player can use the two-dimensional code as a portable terminal device with a camera function. By capturing and decoding the information, it is possible to acquire information advantageous to the user, and to improve the interest.

  In addition, the gaming machine according to the present invention is characterized by comprising number display means (for example, an image control microcomputer 72 and a liquid crystal display device 5 described later) for displaying the number of times counted by the counting means.

  With this configuration, the gaming machine of the present invention displays the number of times counted by the counting means.

  Therefore, according to the gaming machine of the present invention, it is possible to visually notify the player of the number of times by displaying the number of times that the loss is determined as an internal winning combination when the gaming state is the special gaming state. And the interest of the player can be improved.

  Therefore, according to the gaming machine of the present invention, even if the player's game becomes monotonous because the gaming state is the special gaming state, the loss is determined as the internal winning combination during the special gaming state. By giving a privilege to the player based on the number of times played, the player's interest can be improved.

  The gaming machine of the present invention will be specifically described below with reference to the drawings. In the following embodiment, as a gaming machine of the present invention, a gaming machine having three rotating reels that variably display symbols, in addition to coins, medals, tokens, etc., a card given to a player A description will be given using a game machine capable of playing using a game value such as a so-called pachislot machine. Further, in the following embodiments, a pachislot gaming machine will be described as an example, but the gaming machine of the present invention is not limited, and a pachinko machine or a slot machine may be used.

  First, an overview of the gaming machine according to the present embodiment will be described with reference to FIG. FIG. 1 is a perspective view of the gaming machine 1 according to the present embodiment.

  As shown in FIG. 1, the gaming machine 1 includes a cabinet 1a that houses reels 3L, 3C, and 3R, a main control circuit 60 (see FIG. 4) that will be described later, and the like, and a front surface that can be opened and closed with respect to the cabinet 1a. And a door 1b.

  A panel display portion 2a and a liquid crystal display portion 2b are formed as substantially vertical surfaces on the front surface of the central portion of the cabinet 1a. Three reels 3L, 3C, and 3R are rotatably provided in a horizontal row inside the front of the central portion of the cabinet 1a (the back of the liquid crystal display portion 2b). On the three reels 3L, 3C, 3R, a symbol row composed of a plurality of types of symbols is drawn on each outer peripheral surface. The symbols of the reels 3L, 3C, and 3R can be seen through the symbol display windows 4L, 4C, and 4R. The reels 3L, 3C, and 3R are controlled by a main control circuit 60 (see FIG. 4) described later so as to rotate at a constant speed (for example, 80 revolutions / minute), and the reels in the symbol display windows 4L, 4C, and 4R are controlled. The symbols drawn on the reels 3L, 3C, 3R vary as the reels rotate. Note that the reels 3L, 3C, 3R and the symbol display windows 4L, 4C, 4R of the present embodiment constitute variable display means of the present invention.

  In addition, the gaming machine 1 receives a winning that serves as a reference for determining success or failure of winning based on the symbols displayed on the symbol display windows 4L, 4C, and 4R when the rotation of the reels 3L, 3C, and 3R is stopped. A line is provided. As the winning lines, a top line 8b, a center line 8c and a bottom line 8d are provided in the horizontal direction, and a cross-up line 8a and a cross-down line 8e are provided in the oblique direction.

  The five winning lines 8a to 8e are basically operated by operating a 1-BET button 11, a 2-BET button 12, and a maximum BET button 13, which will be described later, or by inserting medals into the medal slot 22. Each one, three, and five are activated (hereinafter, the activated winning line is referred to as an activated line). Which winning line is activated is displayed by lighting of BET lamps 9a, 9b, 9c, which will be described later. The determination of the display combination, which will be described later, is performed based on the combination of symbols displayed along this effective line.

  A substantially horizontal pedestal 10 is formed below the panel display 2a and the liquid crystal display 2b. On the left side of the pedestal 10, a 1-BET button 11, a 2-BET button 12, and a maximum BET button 13 for betting credited medals by a push button operation are provided. The 1-BET button 11 is inserted with one of the credited medals by a single pressing operation. The 2-BET button 12 is inserted with two of the credited medals by a single pressing operation. The maximum BET button 13 is a single push operation, and three of the credited medals {that is, the maximum number that can be inserted in a unit game (hereinafter referred to as “maximum number of inserted sheets”)} Is inserted. By operating these BET buttons 11, 12, and 13, the above-described winning line is activated.

  On the right side of the pedestal portion 10, a medal slot 22 is provided. The above-described winning line is activated according to the medal inserted into the medal slot 22.

  A C / P button 14 is provided on the left side of the front surface of the pedestal 10 to switch between credit (Credit) / payout (Pay) of medals acquired by the player in the game. The payout mode or the credit mode is switched by the player's operation on the C / P button 14. In the credit mode, when a winning is established, medals for the number of payouts corresponding to the winning are credited. In the payout mode, when a winning is established, medals corresponding to the payout are paid out from the medal payout opening 15 at the lower front, and the medals paid out from the medal payout opening 15 are stored in the medal receiving section 16. .

  Speakers 21 </ b> L and 21 </ b> R are provided on the left and right above the medal receiving portion 16. The speakers 21L and 21R output game sounds such as performance sounds and notification sounds according to the game situation.

  A start lever 6 is provided on the right side of the C / P button 14. The start lever 6 rotates the reels 3L, 3C, and 3R by a player's start operation, and starts changing the symbols displayed in the symbol display windows 4L, 4C, and 4R.

  Three stop buttons 7L, 7C, and 7R for stopping the rotation of the three reels 3L, 3C, and 3R by the player's stop operation are located on the right side of the start lever 6 at the center of the front surface of the pedestal 10, respectively. Is provided. Here, when the three reels 3L, 3C, and 3R are rotating, the first stop of the rotation of the reels is referred to as a first stop, which is performed after the first stop and the two reels are rotated. The second stop of the rotation of the reel that is performed when the operation is performed is referred to as the second stop, which is performed after the second stop, and is performed last when the rotation of the remaining one reel is performed. Stopping the rotation of the reel is referred to as a third stop. Note that the stop buttons 7L, 7C, and 7R of the present embodiment constitute stop operation means of the present invention.

  An LED 101 and a lamp 102 are provided on the upper portion of the front door 1b. The LED 101 and the lamp 102 emit light in a light emission pattern according to the game situation, and effects and notifications are performed.

  The panel display unit 2 a includes a WIN lamp 17, BET lamps 9 a to 9 c, a payout number display unit 18, and a credit display unit 19.

  The WIN lamp 17 notifies the player that the symbol combination related to the operation of the bonus is displayable (for example, a BB carryover state described later) by lighting. The 1-BET lamp 9a, the 2-BET lamp 9b, and the maximum BET lamp 9c are turned on in accordance with the number of medals inserted in order to play a unit game (that is, the inserted number). The 1-BET lamp 9a is turned on when the number of inserted sheets is one and one winning line 8c is activated. The 2-BET lamp 9b is turned on when the number of inserted coins is two and the three pay lines 8b, 8c, 8d are activated. The maximum BET lamp 9c is turned on when the number of inserted coins is three and all winning lines 8a to 8e are activated.

  The payout number display unit 18 and the credit display unit 19 are each composed of a 7-segment LED, and display the payout number of medals at the time of winning and the number of stored medals.

  The liquid crystal display unit 2b is disposed on the front side of the reels 3L, 3C, and 3R when viewed from the front side, and displays an image and is displayed on the reels 3L, 3C, and 3R in the symbol display windows 4L, 4C, and 4R. The displayed design is displayed transparently. Further, the liquid crystal display unit 2 b displays various images displayed by the liquid crystal display device 5.

  The liquid crystal display unit 2b has an effect display area 23, a frame image having a predetermined shape so as to surround the symbol display windows 4L, 4C, and 4R, and a background image constituting a predetermined image or a background in the image at the time of the effect. Display images that contain. In addition, the effect display area 23 includes a two-dimensional code display area 200 and a number display area 210 for displaying a value of a loss count counter described later.

  The two-dimensional code display area 200 displays a two-dimensional code. The two-dimensional code is a code having information in the horizontal and vertical directions, that is, in a two-dimensional direction, and information can be acquired by reading using an optical reading unit or the like.

  Here, with reference to FIG. 2, in this embodiment, an example from when a two-dimensional code is photographed by a mobile phone until a predetermined image is acquired will be described. FIG. 2 is a diagram illustrating the mobile phone 300 that has captured the two-dimensional codes 201 and 202 and the mobile phone 300 that has acquired predetermined image data 211 and a moving image 212 in the present embodiment.

  As shown in FIG. 2, the player captures the two-dimensional code 201 or the two-dimensional code 202 by photographing the two-dimensional code displayed in the two-dimensional code display area 200 with the mobile phone 300 with a camera function. Next, the player obtains URL information by decoding the two-dimensional code 201 or the two-dimensional code 202, and further shows small seven symbols via the Internet from a predetermined server indicated by the URL information. Image data 211 or moving image data 212 showing a large seven symbols can be acquired. In this embodiment, the gaming machine 1 provides the player with image data and moving image data. However, in the present invention, data other than image data such as audio data is stored in a predetermined server. You may provide this.

  In addition, the liquid crystal display device 5 of this embodiment comprises the code display means and the frequency display means of this invention.

  Next, with reference to FIG. 3, the symbol row arranged on the reels 3L, 3C, 3R will be described. FIG. 3 is a diagram illustrating an arrangement of symbols drawn on the reels 3L, 3C, and 3R of the gaming machine 1 according to the present embodiment.

  A reel sheet is mounted on the outer peripheral surface of each reel 3L, 3C, 3R, and a symbol row in which 21 types of symbols are arranged on the reel sheet is drawn. Specifically, a symbol row composed of symbols of white 7, cherry, watermelon, bell, replay and blank is drawn.

  For each symbol, a code number “00 to 20” for specifying the position of each symbol is determined in advance, and stored as a data table in the ROM 32 of the main control circuit 60 described later with reference to FIG. .

  Next, with reference to FIG. 4, the circuit configuration of the gaming machine 1 including a peripheral device (actuator) electrically connected to the main control circuit 60, the sub control circuit 61, the main control circuit 60 or the sub control circuit 61 will be described. To do. FIG. 4 is a diagram showing a circuit configuration of the gaming machine 1.

  The main control circuit 60 includes a microcomputer 30 disposed on a circuit board as a main component, and is added to a circuit for random number sampling. The microcomputer 30 includes a main CPU 31 and ROM 32 and RAM 33 which are storage means.

  The main CPU 31 is connected to a clock pulse generation circuit 34, a frequency divider 35, a random number generator 36, and a sampling circuit 37. Note that the main CPU 31 of this embodiment constitutes a winning combination determining unit and a stop control unit of the present invention.

  The clock pulse generation circuit 34 and the frequency divider 35 generate a reference clock pulse. The random number generator 36 generates random numbers within a certain range. The sampling circuit 37 extracts (samples) one random number value from the random number generated by the random number generator 36. Note that the random number generator 36 and the sampling circuit 37 of the present embodiment constitute the winning combination determining means of the present invention.

  Further, in the gaming machine 1, the random value extracted in the unit game is stored in a random value storage area of the RAM 33 described later. Then, by using a random value stored in the random value storage area of the RAM 33 for each unit game, an internal lottery process described later is performed to determine an internal winning combination.

  In addition, as a means for random number sampling, you may make it the structure which performs random number sampling within the microcomputer 30, ie, on the operation program of the main CPU31. In that case, the random number generator 36 and the sampling circuit 37 can be omitted, or can be left as a backup for the random number sampling operation.

  The ROM 32 of the microcomputer 30 stores a program (for example, see FIGS. 14 to 22 described later), various tables (for example, see FIG. 3 and FIGS. 6 to 10 described later), bonus check data (for example, see FIG. Various control commands (commands) to be transmitted to the sub-control circuit 61 are stored.

  Various information obtained by the processing of the main CPU 31 is set in the RAM 33. For example, information specifying the extracted random number value, gaming state, number of FT games, number of payouts, etc. is set. These pieces of information are transmitted to the sub-control circuit 61 by the aforementioned command.

  In the circuit of FIG. 4, the main actuators whose operation is controlled by a control signal from the microcomputer 30 are BET lamps 9a, 9b, 9c, a WIN lamp 17, a payout number display unit 18, a credit display unit 19, and a hopper 40. There are stepping motors 49L, 49C, 49R and the like. The exchange of signals between these actuators and the main CPU 31 is performed via the I / O port 38.

  In addition, each circuit for controlling the operation of each actuator described above is connected to the output unit of the microcomputer 30 in response to a control signal output from the main CPU 31. Each circuit includes a motor drive circuit 39, a lamp drive circuit 45, a display unit drive circuit 48, and a hopper drive circuit 41.

  The lamp driving circuit 45 controls the drive of the BET lamps 9a, 9b, 9c and the WIN lamp 17. Thereby, the BET lamps 9a, 9b, 9c and the WIN lamp 17 are turned on and off.

  The display unit drive circuit 48 drives and controls the payout number display unit 18 and the credit display unit 19. As a result, various information (such as the number of credits) is displayed on the payout number display unit 18 and the credit display unit 19.

  The hopper drive circuit 41 drives and controls the hopper 40. Thereby, the medal accommodated in the hopper 40 is paid out.

  The motor drive circuit 39 drives and controls the stepping motors 49L, 49C, 49R. As a result, the reels 3L, 3C, and 3R are rotated and stopped. Note that the motor drive circuit 39 and the stepping motors 49L, 49C, 49R of the present embodiment constitute the variable display means and stop control means of the present invention.

  Also, each switch and each circuit for generating an input signal that triggers outputting a control signal to each circuit and each actuator described above are connected to the input section of the microcomputer 30. Each switch and circuit includes a start switch 6S, stop switches 7LS, 7CS, 7RS, 1-BET switch 11S, 2-BET switch 12S, maximum BET switch 13S, C / P switch 14S, medal sensor 22S, reel position detection. There are a circuit 50 and a payout completion signal circuit 51.

  The start switch 6S detects a player's start operation with respect to the start lever 6, and outputs a start signal instructing the start of the unit game to the microcomputer 30. At this time, in order to perform automatic stop, the microcomputer 30 sets an automatic stop timer based on the input start signal and measures a predetermined time (for example, 40 seconds).

  This automatic stop means that when a stop signal from the stop switch 7LS, 7CS, 7RS is not detected within a predetermined time counted based on the input start signal, the microcomputer 30 This means that the reels 3L, 3C, and 3R are controlled to stop by outputting a control signal to the motor drive control circuit 39 without being based on the player's stop operation. Further, when the microcomputer 30 performs this automatic stop, the reels 3L, 3C, 3R are arranged so that the combination of symbols stopped on the active line is the most unfavorable aspect for the player, that is, loses. Command to stop the rotation of.

  The stop switches 7LS, 7CS, and 7RS detect the player's stop operation on the stop buttons 7L, 7C, and 7R, respectively, and stop the rotation of the reels 3L, 3C, and 3R corresponding to the detected stop buttons 7L, 7C, and 7R. A stop signal to be commanded is output to the microcomputer 30. Note that the stop switches 7LS, 7CS, and 7RS of the present embodiment constitute stop operation means of the present invention.

  The BET switches 11S to 13S detect a player's insertion operation for each BET button, and output a signal instructing insertion of one, two, or three medals from the credited medals to the microcomputer 30. .

  The C / P switch 14S detects a player's switching operation on the C / P button 14, and outputs a signal for switching the credit mode or the payout mode to the microcomputer 30. When the credit mode is switched to the payout mode, a signal for instructing the payout of medals credited to the gaming machine 1 is output to the microcomputer 30.

  The medal sensor 22S detects medals inserted into the medal insertion slot 22 by the player's insertion operation, and outputs a signal indicating that a medal has been inserted to the microcomputer 30.

  The reel detection circuit 50 detects a pulse signal from the reel rotation sensor and generates a signal for detecting the position of the symbol on each reel 3L, 3C, 3R.

  The payout completion signal circuit 51 indicates that the payout of medals is completed when the number of medals detected by the medal detection unit 40S (that is, the number of medals paid out from the hopper 40) reaches the designated number. For generating a signal.

  The sub-control circuit 61 performs various processes such as determination and execution of effect contents based on various commands output from the main control circuit 60 such as a start command described later. The sub control circuit 61 does not input commands, information, or the like to the main control circuit 60, and communication is performed in one direction from the main control circuit 60 to the sub control circuit 61.

  The main actuators whose operation is controlled by a control signal from the sub control circuit 61 include the liquid crystal display device 5, the speakers 21L and 21R, the LED 101, and the lamp 102. The sub-control circuit 61 determines and displays an image displayed on the liquid crystal display device 5 based on the determined content of the effect, determines and outputs the lighting pattern of the LED 101 and the lamp 102, and the effect sound output from the speakers 21L and 21R. Control of sound and sound effects and output.

  Details of the configuration of the sub control circuit 61 in the present embodiment will be described later.

  In the gaming machine 1, when a signal for starting a unit game is output from the start switch 6S by a player's operation on the start lever 6 on condition that a medal is inserted, a control signal is output to the motor drive circuit 39, and stepping is performed. The rotation of the reels 3L, 3C, 3R is started by drive control of the motors 49L, 49C, 49R (for example, excitation to each phase). At this time, the number of pulses output to the stepping motors 49L, 49C, 49R is counted, and the counted value is set in a predetermined area of the RAM 33 as a pulse counter. In the gaming machine 1, when the “16” pulse is output, the reels 3L, 3C, and 3R move by one symbol. The number of symbols moved is counted, and the counted value is set in a predetermined area of the RAM 33 as a symbol counter. That is, every time the pulse counter counts “16”, the symbol counter is updated by “1”.

  A reel index is obtained from the reels 3L, 3C, and 3R for each rotation and is output to the main CPU 31 via the reel position detection circuit 50. With the output of the reel index, the pulse counter and the symbol counter set in the RAM 33 are cleared to “0”. In this way, the symbol position within one rotation range is specified for each reel 3L, 3C, 3R.

  Here, in the ROM 32, a symbol arrangement table (see FIG. 3) is stored in the ROM 32 in order to associate the rotational positions of the reels 3L, 3C, and 3R with the symbols drawn on the outer peripheral surface of the reel. ing. In this symbol arrangement table, the code numbers from “00” to “20”, which are sequentially given for each fixed rotation pitch of each of the reels 3L, 3C, and 3R, with the position where the reel index is output as a reference, A symbol code for identifying the type of symbol provided corresponding to each code number is associated.

  When a start signal is output from the start switch 6S, a random number value is extracted by the random number generator 36 and the sampling circuit 37. In the gaming machine 1, when the random value is extracted, it is stored in the random value storage area of the RAM 33. Then, an internal lottery process, which will be described later, is performed based on the random number value stored in the random value storage area, and an internal winning combination is determined.

  After the reels 3L, 3C, and 3R have reached constant speed rotation, when a stop signal is output from the stop switches 7LS, 7CS, and 7RS by a stop operation, based on the output stop signal and the determined internal winning combination, A control signal for stopping and controlling the reels 3L, 3C, 3R is output to the motor drive circuit 39. The motor drive circuit 39 drives and controls the stepping motors 49L, 49C, 49R, and stops the rotation of the reels 3L, 3C, 3R.

  In addition, when the predetermined time has elapsed after the reels 3L, 3C, and 3R have reached constant speed rotation and the automatic stop timer becomes “0”, the automatic stop is performed. Therefore, the reels 3L, 3L, A control signal for stopping and controlling 3C and 3R is output to the motor drive circuit 39.

  When the reels 3L, 3C, and 3R are controlled to stop, a table that determines the stop positions of the reels 3L, 3C, and 3R that are selected by the stop operation for each gaming state and for each internal winning combination (hereinafter referred to as a table). The stop position determination table is stored in the ROM 32. The control signal for controlling the stop of the reels 3L, 3C, 3R is selected based on the gaming state and the determined internal winning combination, and the stop position determination table is selected and the selected stop position determination table and the stop operation are selected. Based on this, a predetermined symbol of each reel 3L, 3C, 3R is output to the motor drive circuit 39 so as to be displayed in the symbol display windows 4L, 4C, 4R. However, as described above, when the automatic stop is performed, the control signal for controlling the stop of the reels 3L, 3C, and 3R indicates that the combination of symbols stopped on the effective line is the most disadvantageous to the player. As shown in FIG.

  When the rotation of all the reels 3L, 3C, 3R is stopped, the display combination retrieval process is performed based on the combination of symbols displayed at a predetermined position (for example, the center line 8c). The display combination is searched based on a symbol combination table (see FIG. 6 described later) stored in the ROM 32. In this symbol combination table, a symbol combination related to a display combination and a corresponding payout are set.

  When it is determined by the display combination search that a combination of symbols related to winning is displayed, a control signal is output to the hopper driving circuit 41 and the hopper 40 is driven to pay out medals. At this time, the medal detection unit 40S counts the number of medals to be paid out from the hopper 40, and when the count value reaches the designated number, the payout completion signal circuit 51 outputs a signal indicating completion of the medal payout. The Thereby, a control signal is output to the hopper drive circuit 41, and the drive of the hopper 40 is stopped.

  When the credit mode is switched by the C / P switch 14S, if it is determined that the winning symbol combination is displayed, the payout amount corresponding to the winning symbol combination is stored in the credit of the RAM 33. Add to the number counter. Further, a control signal is output to the display unit driving circuit 48 and the value of the credit number counter is displayed on the credit display unit 19. Here, there is a case where a medal payout or a credit performed when a combination of symbols related to winning is displayed is simply referred to as “payout”.

  Next, the circuit configuration of the sub-control circuit 61 will be described with reference to FIG. FIG. 5 is a diagram showing a circuit configuration of the sub control circuit of the gaming machine 1.

  As shown in FIG. 5, the sub control circuit 61 includes an image control circuit 70 and a sound / lamp control circuit 90. The image control circuit 70 controls the liquid crystal display device 5. The sound / lamp control circuit 90 controls sound output from the speakers 21L and 21R and lighting of the LED 101 and the lamp 102.

  The image control circuit 70 includes a serial port 71, an image control microcomputer 72, a program ROM 73, a work RAM 74, a calendar IC 75, an image control IC 76, an image ROM 79, and a video RAM 80.

  The serial port 71 receives a command output from the main control circuit 60. The serial port 71 outputs a command generated by the image control microcomputer 72 to the sound / lamp control circuit 90.

  The image control microcomputer 72 performs display control of the liquid crystal display device 5 based on a program stored in the program ROM 73. Specifically, the image control microcomputer 72 receives a command indicating a gaming state, an internal winning combination, and the like from the main control circuit 60, and data related to date and time (hereinafter referred to as “date and time data”) from the calendar IC 75. Is stored in the work RAM 74. The image control microcomputer 72 executes the program while referring to the game state identifier, winning combination identifier, date / time data, and the like stored in the work RAM 74, whereby the liquid crystal display device 5, the speakers 21L and 21R, the LED 101, the lamp 102, and the like. The effect identifier and the effect data for defining the contents of the effect are determined.

  Further, the image control microcomputer 72 outputs a control command to the sound / lamp control circuit 90 via the serial port 71 based on the determined effect identifier and effect data.

  Further, in the present embodiment, the image control microcomputer 72 encodes URL information that is information provided to the player (hereinafter referred to as “encoding”) in order to display the two-dimensional code on the liquid crystal display device 5. The two-dimensional code generated is stored in the work RAM 74. Further, the image control microcomputer 72 extracts information such as a position for displaying the two-dimensional code from the program ROM 73 (hereinafter referred to as “two-dimensional code display information”) and transmits it to the image control IC 76.

  Note that the image control microcomputer 72 of the present embodiment constitutes a privilege giving means, a code display means, a counting means, and a frequency display means of the present invention.

  The program ROM 73 stores programs such as an image control program executed by the image control microcomputer 72 (for example, see FIGS. 23 to 25 and FIGS. 27 to 34 described later) and various tables.

  The work RAM 74 is used as temporary work storage means when the image control microcomputer 72 executes each program. For example, the work RAM 74 generates a command transmitted from the main control circuit 60, an identifier during game play, an effect identifier, a game state identifier, a winning combination identifier, a carryover combination identifier, a display combination identifier, an FT game number counter, and a lost count counter. Information such as a two-dimensional code is stored.

  The calendar IC 75 stores date / time data input from an operation unit (not shown) of the gaming machine. The image control microcomputer 72 executes various effects using the date / time data. Note that the data stored in the aforementioned work RAM 74 and calendar IC 75 is data to be backed up.

  An image control IC 76 (hereinafter also referred to as VDP) includes a control RAM 77 that stores image data, date / time data, and the like transmitted from the image control microcomputer 72, and a D / A converter 78 that converts the image data into an image signal. It is equipped with.

  The image control IC 76 performs display control for the liquid crystal display device 5. When receiving an image display command or the like from the image control microcomputer 72, the image control IC 76 reads image data stored in the image ROM 79 or the work RAM 74 in order to display an image on the liquid crystal display device 5. In the present embodiment, the image control IC 76 reads a two-dimensional code generated in the work RAM 74 in an encoding process (see FIG. 32) described later, and when the two-dimensional code is generated, a loss count counter described later. A numeric image indicating the value of is read from the image ROM 79.

  The image control IC 76 sequentially superimposes the image data read from the image ROM 79 or the work RAM 74 from the background image located at the rear to the two-dimensional code image and the numeric image located at the front, and stores them in the video RAM 80 to be described later. The data is synthesized and supplied to the D / A converter 78 at a predetermined timing. The D / A converter 78 converts the image data into an image signal and supplies it to the liquid crystal display device 5. As a result, a two-dimensional code and a numerical image are displayed on the liquid crystal display device 5. Note that the image control IC 76 of the present embodiment constitutes a privilege giving means, a code display means, and a frequency display means of the present invention.

  The control RAM 77 is used as temporary storage means when the image control microcomputer 72 executes an image control program. Various variables such as a VDP counter are assigned to the control RAM 77 of the present embodiment. This VDP counter is incremented based on a clock signal transmitted from the image control IC 76 to the image control microcomputer 72, and from the timing when the bank control instruction described later is sent from the image control microcomputer 72 to the image control IC 76 last time. Used to determine whether 1/30 seconds or more have elapsed.

  The image ROM 79 stores image data constituting an image displayed on the liquid crystal display device 5. In the present embodiment, in particular, a numerical image corresponding to the value of a loss counter that will be described later is stored. In this embodiment, as will be described later, the image control microcomputer 72 encodes the URL information to generate a two-dimensional code. However, in the present invention, the two-dimensional code in which the URL information is encoded is stored in the image ROM 79. You may leave it.

  The video RAM 80 is used as a temporary storage unit when the image control IC 76 generates a display image from the image data. The video RAM 80 is composed of two frame buffers, a write image data area for storing image data transferred from the image control IC 76 and a display image data area for storing image data displayed on the liquid crystal display device 5. Yes. These frame buffers are alternately switched by the image control IC 76 (that is, the banks are switched), whereby image data is sequentially supplied to the liquid crystal display device 5.

  The sound / lamp control circuit 90 includes a serial port 91, a sound / lamp control microcomputer 92, a work RAM 93, a program ROM 94, a sound source IC 95, a power amplifier 96, and a sound source ROM 97.

  The serial port 91 receives a command generated by the image control microcomputer 72 via the serial port 71.

  The sound / lamp control microcomputer 92 controls the lighting of the LED 101 and the lamp 102 and the output sound of the speakers 21L and 21R based on the program stored in the program ROM 94. Specifically, the sound / lamp control microcomputer 92 receives a command from the image control circuit 70 and stores it in the work RAM 93. The sound / lamp control microcomputer 92 executes the program (see FIG. 26) stored in the program ROM 94 based on the information stored in the work RAM 93, and controls the sound source IC 95 and the lighting of the LED 101 and the lamp 102. I do.

  The sound source IC 95 reads the sound data stored in the sound source ROM 97 and amplifies the read sound data using the power amplifier 96 in accordance with control by the sound / lamp control microcomputer 92.

  Next, with reference to FIG. 6, the display combination corresponding to the displayed symbol combination and its payout will be described. FIG. 6 is a diagram illustrating an example of the symbol combination table of the gaming machine 1 in the present embodiment.

  The symbol combination table defines the display combination corresponding to the combination of symbols displayed on the active line and the number of payouts for the display combination for each inserted number of medals. Cherry, bell, watermelon, replay, and BB (so-called “big bonus”) are set as the display combination of the gaming machine 1. Here, cherry, bell, and watermelon are collectively referred to as “small role”.

  As shown in FIG. 6, the cherry is established when the symbol of the cherry is on the effective line and displayed on the left symbol display window 4 </ b> L. As a result, the cherry is won and three medals are paid out.

  The bell is established by displaying three bell symbols side by side along the active line. As a result, Bell wins. When the number of inserted medals is 3, 10 medals are paid out.

  A watermelon is established by displaying three watermelon symbols along the active line. As a result, the watermelon is won and one medal is paid out.

  Replay is established when three replay symbols are displayed side by side along the active line. Thereby, the re-game is performed in the next unit game. That is, the same number of medals as the number of coins inserted in the unit game in which replay is established are automatically inserted in the next unit game without being based on the player's insertion operation. Thereby, the player can perform the next unit game without consuming medals. Here, the above-mentioned medal payout and re-game are examples of giving game value.

  BB is established by displaying three white 7 symbols side by side along the active line, and thereafter, the BB operation state is established. When the gaming machine 1 enters the BB operating state, the gaming machine 1 continuously operates the RB gaming state until the payout number of medals exceeds 350. In the RB gaming state, the probability that an internal winning combination (that is, a bell) having a larger number of payouts than other internal winning combinations is determined is increased. Further, the RB gaming state is ended when the number of unit games performed in the RB gaming state reaches 12 times or when the number of winnings reaches 8 times. However, even before the termination condition is satisfied, if the BB operation state is terminated because the number of paid-out medals exceeds 350, the RB gaming state is also terminated accordingly.

  Further, when a symbol combination other than the symbol combinations related to cherry, bell, watermelon, replay, and BB is displayed, a loss is established. When the display combination is lost, medals are not paid out.

  Next, a lottery count determination table used when determining an internal winning combination in an internal lottery process (see FIG. 16) described later will be described with reference to FIG. FIG. 7 is a diagram illustrating an example of a lottery count determination table of the gaming machine 1 in the present embodiment.

  The lottery count determination table defines the number of lotteries corresponding to each gaming state. Specifically, the lottery count determination table defines “5” as the number of lotteries when the gaming state is the general gaming state, and “5” as the number of lotteries even when the gaming state is the FT gaming state. ”Is specified, and“ 3 ”is specified as the number of lotteries when the gaming state is the RB gaming state. However, in the case of the BB carryover state described later, the number of lotteries is updated to “4” in the process of step S33 of the internal lottery process.

  Next, an internal lottery table used when determining an internal winning combination in an internal lottery process (see FIG. 16) described later will be described with reference to FIG. FIG. 8 (1) is a diagram showing an example of an internal lottery table for general gaming state of the gaming machine 1 in the present embodiment. FIG. 8 (2) is a diagram showing an example of an internal lottery table for FT gaming state of the gaming machine 1 in the present embodiment. FIG. 8 (3) is a diagram showing an example of an internal lottery table for RB gaming state of the gaming machine 1 in the present embodiment.

  The internal lottery table includes an internal lottery table for a general gaming state that is used when the gaming state is a general gaming state, an internal lottery table for an FT gaming state that is used when the gaming state is an FT gaming state, There is an RB gaming state internal lottery table used when the gaming state is the RB gaming state. The internal lottery table defines a lower limit value and an upper limit value that are determined based on the winning number and the number of inserted medals for each combination. For example, in the internal lottery table for the general gaming state, when the winning number “5” corresponding to BB is three medals, the lower limit value is set to “18001” and the upper limit value is “18250”. Is prescribed.

  That is, in the gaming machine 1, in an internal lottery process (see FIG. 16) described later, the random number value stored in the RAM 33 is within a range from a lower limit value to an upper limit value defined by the internal lottery table (hereinafter referred to as “winning range”). If it is within the winning range, the internal winning combination is determined based on the winning number corresponding to the winning range. Here, the winning number is a number that takes a value of “0 to 5”, and the value of “0 to 5” corresponds to lose, cherry, bell, watermelon, replay, and BB, respectively.

  Further, in the present embodiment, the internal lottery table is defined so that the winning range does not overlap with a plurality of roles, but by defining this so as to overlap, two roles are determined as internal winning combinations. It can also be made.

  In the present embodiment, the RB gaming state internal lottery table is set to have one medal inserted per unit game in the RB gaming state, so the number of inserted medals is two or three. It does not stipulate in some cases. In FIG. 8, the internal lottery table for the general gaming state and the internal lottery table for the FT gaming state show only the case where the number of inserted medals is one and three, and the case where the number of inserted medals is two. Is omitted.

  Next, an internal winning combination determination table used when determining an internal winning combination in an internal lottery process (see FIG. 16) described later will be described with reference to FIG. FIG. 9 is a diagram showing an example of the internal winning combination determination table of the gaming machine 1 in the present embodiment.

  The internal winning combination determination table defines an internal winning combination corresponding to the winning number and a bit pattern indicating the internal winning combination. For example, when the winning number is “5”, the internal winning combination determination table defines BB as the internal winning combination and “00010000” as the bit pattern of the internal winning combination.

  Next, referring to FIG. 10, in the BB operation process (see step S92 in FIG. 20) and the RB operation process (see step S53 in FIG. 15), which will be described later, conditions for ending the BB operation state and the RB gaming state The bonus operation time table used when setting the value will be described. FIG. 10 is a diagram showing an example of the bonus operation time table of the gaming machine 1 in the present embodiment.

  The bonus operation time table defines the value of the bonus end number counter that is a condition for ending the BB operation state, and also defines the value of the possible number of games and the number of possible winnings that are conditions for ending the RB gaming state. Specifically, in the bonus operation time table, “350” is defined as the value of the bonus end number counter which is a condition for ending the BB operation state, and the possible number of games and the number of possible winnings are the conditions for ending the RB gaming state. The values of “12” and “8” are respectively defined as the values of. That is, the BB operation state is ended when the number of paid-out medals exceeds 350, and the RB game state is ended when the number of games reaches 12 times or the number of wins reaches 8.

  Next, with reference to FIG. 11 (1), bonus check data used for determining whether or not the internal winning combination is BB in the internal lottery process (see FIG. 16) described later will be described. FIG. 11 (1) is a diagram showing an example of bonus check data of the gaming machine 1 in the present embodiment.

  The bonus check data is an 8-bit bit pattern, where “bit 0 to bit 3” and “bit 5 to bit 7” are composed of “0”, and “bit 4” is composed of “1”. In other words, the bonus check data has the same bit pattern as the BB bit pattern “00010000” defined in the internal winning combination determination table.

  Next, with reference to FIG. 11 (2), an internal winning combination storing area for storing internal winning combination information will be described. FIG. 11B is a diagram illustrating an example of the internal winning combination storing area of the gaming machine 1 in the present embodiment.

  The internal winning combination storing area is an 8-bit data area allocated on the RAM 33. The internal winning combination storage area indicates which combination is an internal winning combination by storing “0” or “1” data in the “bit 0 to bit 4” area. For example, when the bit pattern of the internal winning combination storing area is “00000010”, it indicates that the bell is an internal winning combination. Further, when the bit pattern of the internal winning combination storing area is “00000110”, it indicates that the watermelon and the bell are internal winning combinations.

  Next, a carryover combination storage area for storing carryover combination information will be described with reference to FIG. In addition, FIG. 11 (3) is a figure which shows the example of the carryover combination storage area | region of the gaming machine 1 in this embodiment.

  The carryover combination storage area is an 8-bit data area allocated on the RAM 33. The carryover combination storage area indicates whether it is in the BB carryover state by storing “0” or “1” data in the “bit 4” area. That is, when the bit pattern of the carryover combination storage area is “00010000”, it indicates that the BB carryover state is set. Here, the BB carryover state means that, during the general gaming state or the FT gaming state, when the internal winning combination is determined to be BB, three white 7 symbols are displayed along the active line. , The state where the internal winning state continues for BB.

  Next, with reference to FIG. 11 (4), a winning number storage area for storing winning number information will be described. FIG. 11 (4) is a diagram showing an example of the winning number storage area of the gaming machine 1 in the present embodiment.

  The winning number storage area is an 8-bit data area allocated on the RAM 33. The winning number storage area indicates which winning number is won by storing “0” or “1” data in the “bit 0 to bit 4” area. For example, when the winning number “5” is won, data “1” is stored in “bit 4”.

  When two winning numbers are won, “1” is set in the bits of the winning number storage area corresponding to these two winning numbers. That is, when the winning numbers “2” and “3” are internally won, the bit pattern of the winning number storage area is “00000110”.

  Next, with reference to FIG. 12 (1), the effect identifier determination table used when determining an effect identifier in the game start process (refer FIG. 30) mentioned later is demonstrated. In addition, FIG. 12 (1) is a figure which shows the example of the production identifier determination table of the gaming machine 1 in this embodiment.

  The effect identifier determination table is stored in the program ROM 73 in the sub-control circuit 61, and defines the effect identifier for determining the effect content to be performed by the gaming machine 1 and the conditions for determining the effect identifier. For example, in the effect identifier determination table, when the winning combination identifier indicates BB winning and the random value is “60000” or less, “A1” is defined as the effect identifier.

  Next, referring to FIG. 12 (2), it is used when effect data is determined in a game start process (see FIG. 30), a reel stop process (see FIG. 33) and a display process (see FIG. 34) which will be described later. The production data determination table to be performed will be described. FIG. 12 (2) is a diagram illustrating an example of the effect data determination table of the gaming machine 1 in the present embodiment.

  The effect data determination table is stored in the program ROM 73 in the sub-control circuit 61, and the effect data for determining the effect content to be performed when the start button is pressed, at the first stop, at the second stop, at the third stop, and at the time of display, It is defined for each production identifier. For example, when the effect identifier is “effect A1”, the effect data determination table defines “A1-1” as start effect data set in a game start process described later.

  Next, with reference to FIG. 13, a URL information setting table used when determining URL information to be encoded in an encoding process (see FIG. 30) described later will be described. FIG. 13 is a diagram showing an example of the URL information setting table of the gaming machine 1 in the present embodiment.

  The URL information setting table is stored in the program ROM 73 in the sub-control circuit 61. The URL information setting table defines the number of times of losing in the FT gaming state, which is a condition for determining URL information, and is stored in a predetermined server indicated by the URL information. The contents of the processed image data and moving image data are shown. For example, when the number of lost times is 2, “http: //***.***/002.htm” is determined as the URL information.

  Note that the player can acquire moving image data of “large 7 symbols” by connecting to a predetermined server indicated by the URL information via the Internet. Further, as will be described later, the URL information “http: //***.***/002.htm” is encoded to generate a two-dimensional code 202. The player obtains “http: //***.***/002.htm” as URL information by photographing and decoding the two-dimensional code 202 with the mobile phone 300 with a camera function. To do. A player can obtain a moving image 212 showing seven large symbols as shown in FIG. 2 by connecting to a predetermined server indicated by the URL information via the Internet.

  Next, the control operation of the main CPU 31 of the main control circuit 60 will be described with reference to the flowcharts shown in FIGS.

  First, with reference to FIG. 14, the reset interrupt process by the main CPU 31 of the main control circuit 60 will be described. FIG. 14 is a flowchart of the reset interrupt process performed by the main CPU 31 performed by the main control circuit 60 of the present embodiment. Further, the main CPU 31 generates a reset interrupt when power is turned on and a voltage is applied to the reset terminal, and the reset interrupt process stored in the ROM 32 is sequentially performed based on the occurrence of the interrupt. It is configured as follows.

  First, when the power is turned on, the main CPU 31 performs initialization (step S1).

  Next, the main CPU 31 clears the designated RAM area at the end of the game (step S2). Specifically, the main CPU 31 erases data in the writable area in the RAM 33 used for the previous unit game, writes parameters necessary for the current unit game in the writable area in the RAM 33, Specify the start address to the sequence program.

  Next, the main CPU 31 performs a bonus operation monitoring process which will be described later with reference to FIG. 15 (step S3). This bonus operation monitoring process is a process for generating an RB gaming state when the BB operating state is not the RB gaming state.

  Next, the main CPU 31 performs medal insertion / start check processing (step S4). First, in the medal insertion check process, the main CPU 31 determines whether the medal sensor 22S has detected passage of a medal, whether the BET switches 11S, 12S, 13S are turned on, or based on the replay operating flag. It is determined whether or not a replay has been established in the unit game, and the insertion number counter set in the RAM 33 is updated based on each determination result. Here, the replay operating flag is information for identifying whether or not replay is established. The inserted number counter is information for specifying the inserted number in the current unit game. Next, the main CPU 31 validates the winning line according to the value of the inserted number counter. For example, if the inserted number counter is “3”, the main CPU 31 performs a display combination search process, which will be described later, based on a combination of symbols displayed on all active lines. In the start check process, the main CPU 31 starts on the condition that a medal is inserted, for example, on the condition that the inserted number counter is “1” or more or the inserted number counter is the maximum value “3”. Processing for determining whether or not the start switch 6S is turned on by the operation is performed.

  Next, when determining that the start switch 6S is turned on, the main CPU 31 extracts a random number value for determining an internal winning combination (step S5). Specifically, the main CPU 31 extracts one random value from the range of “0 to 65535” by the random number generator 36 and the sampling circuit 37 and stores the extracted random value in the random value storage area of the RAM 33 described above. .

  Next, the main CPU 31 performs a gaming state monitoring process (step S6). In this gaming state monitoring process, the main CPU 31 sets a gaming state identifier for identifying the gaming state in the current unit game in the RAM 33 based on the RB operating flag and the FT game number counter. Specifically, the main CPU 31 sets the RB gaming state if the RB operating flag is on, and sets the FT gaming state if the FT game number counter is greater than “1”. Set the gaming state.

  Next, the main CPU 31 performs an internal lottery process which will be described later with reference to FIG. 16 (step S7). In this internal lottery process, the main CPU 31 determines the aforementioned lottery count determination table (see FIG. 7) and the internal lottery table (FIG. 8 (1), FIG. 8 (2), FIG. 8 (3)) based on the gaming state. And an internal winning combination determination table (see FIG. 9), and an internal winning combination is determined.

  Next, the main CPU 31 performs an FT control process which will be described later with reference to FIG. 17 (step S8). In this FT control process, the main CPU 31 subtracts “1” from the FT game number counter when the gaming state is the FT gaming state. Further, when the game state is the general game state, the main CPU 31 sets “100” to the FT game number counter in order to transition the game state to the FT game state when the watermelon is determined to be the internal winning combination. .

  Next, the main CPU 31 transmits a start command to the sub control circuit 61 (step S9). The start command includes, for example, information such as a gaming state, an internal winning combination, a random value, and an FT game number counter.

  Next, the main CPU 31 determines whether 4.1 seconds have elapsed since the start of the previous rotation of the reels 3L, 3C, 3R (step S10). When determining that 4.1 seconds have not elapsed, the main CPU 31 performs a wait process (step S11). In this wait process, the main CPU 31 performs a standby process without performing subsequent processes until 4.1 seconds have elapsed since the start of rotation of the reels 3L, 3C, and 3R.

  The main CPU 31 sets a game monitoring timer in the RAM 33 when it is determined that 4.1 seconds have elapsed in the process of step S10, or when a wait process is performed in the process of step S11 (step S11). S12). The main CPU 31 counts the above-mentioned 4.1 seconds by the set game monitoring timer, sets the automatic stop timer in order to perform the above-mentioned automatic stop, and sets a predetermined time (for example, 40 seconds). Start timing.

  Next, the main CPU 31 requests the start of rotation of all reels (step S13). For example, the main CPU 31 performs processing such as turning on a rotation start request flag set in the RAM 33. When the start of rotation of all reels is requested, rotation start processing and acceleration control processing of the reels 3L, 3C, and 3R are performed.

  Next, the main CPU 31 performs a reel stop control process which will be described later with reference to FIG. 18 (step S14). In the reel stop control process, the main CPU 31 stops the rotation of the reels 3L, 3C, and 3R based on a stop signal output from the stop switches 7LS, 7CS, and 7RS by the player's stop operation.

  Next, when all the rotations of the reels 3L, 3C, and 3R are stopped, the main CPU 31 performs a display combination search process based on the displayed symbol combination (step S15). In this display combination search process, the main CPU 31 identifies the display combination based on the code number of the symbols displayed side by side on the active line and the symbol combination table (see FIG. 6). Further, the main CPU 31 sets a display combination flag for identifying the display combination and information on the number of payouts corresponding to the display combination in the RAM 33. For example, when the watermelons are displayed side by side on the center line 8c, the main CPU 31 displays the display combination flag for identifying that the display combination is a watermelon and the payout number information for specifying that the payout number is 1 in the RAM 33. Set to.

  Next, the main CPU 31 transmits a display combination command to the sub control circuit 61 (step S16). The display combination command includes information on a display combination flag that identifies a display combination established on the active line, such as a replay display combination.

  Next, the main CPU 31 performs medal payout processing (step S17). In this medal payout process, the main CPU 31 updates the credit counter set in the RAM 33 based on the payout number information in the credit mode. When the credit counter is updated, the credit counter 19 displays the value of the credit counter. In the payout mode, the main CPU 31 drives and controls the hopper 40 by the hopper drive circuit 41 based on the payout number information to pay out medals. Further, if the display combination is replay, the main CPU 31 turns on the replay operating flag.

  Next, when the BB operating flag set in the RAM 33 is ON, the main CPU 31 subtracts the number of medals paid out in the process of step S17 from the bonus end number counter (step S18).

  Next, the main CPU 31 determines whether or not the BB operating flag or the RB operating flag set in the RAM 33 is on (step S19). At this time, when the main CPU 31 determines that the BB operating flag or the RB operating flag is not on, that is, when it is determined that both the BB operating flag and the RB operating flag are off, FIG. The process proceeds to a bonus operation check process (step S21) described with reference to FIG.

  On the other hand, when the main CPU 31 determines in the process of step S19 that the BB operating flag or the RB operating flag is on, it performs a bonus end check process (step S20) described later with reference to FIG. . In this bonus end check process, the main CPU 31 ends the RB when the RB end condition is satisfied, and when the BB operation state end condition is satisfied, the main CPU 31 determines the BB operation state and the RB game. End the state.

  Next, when the main CPU 31 determines in the process of step S19 that the BB operating flag or the RB operating flag is not on, or performs a bonus end check process in the process of step S20, the main CPU 31 checks the bonus operation check. Processing is performed (step S21). This bonus operation check process is a process for generating a BB operation state when the display combination is BB. When this process ends, the main CPU 31 proceeds to the process of step S2.

  As described above, the main CPU 31 executes the process from step S2 to step S21 as the process in the unit game, and when the process in step S21 ends, the main CPU 31 proceeds to the process in step S2 to execute the process in the next unit game. .

  Next, the bonus operation monitoring process will be described with reference to FIG. FIG. 15 is a view showing a flowchart of the bonus operation monitoring process performed in the main control circuit 60 of the present embodiment. The bonus operation monitoring process is a process for generating an RB gaming state when the BB operating state is not the RB gaming state.

  First, the main CPU 31 determines whether or not the BB operating flag is on (step S51). At this time, when the main CPU 31 determines that the BB operating flag is not on, the main CPU 31 ends the bonus operation monitoring process. On the other hand, in the process of step S51, when the main CPU 31 determines that the BB operating flag is on, it then determines whether or not the RB operating flag is on (step S52). At this time, when the main CPU 31 determines that the RB operating flag is on, the main CPU 31 ends the bonus operation monitoring process.

  On the other hand, when the main CPU 31 determines in the process of step S52 that the RB operating flag is not on, the main CPU 31 then refers to the bonus operating table (see FIG. 10) and performs the RB operating process (step S53). Specifically, the main CPU 31 refers to the bonus operating time table, sets “12” as the number of possible games, sets “8” as the number of possible winnings, and turns on the RB operating flag. After completing this process, the main CPU 31 ends the bonus operation monitoring process.

  That is, the main CPU 31 always generates the RB gaming state in the BB operating state by the bonus operation monitoring process. For example, in the previous unit game, either the number of possible games or the number of possible winnings is “0”, and even if the RB gaming state is finished, the main CPU 31 again performs the RB A game state is generated. When the main CPU 31 ends the bonus operation monitoring process, the main CPU 31 proceeds to the process of step S4 in FIG.

  Next, the internal lottery process will be described with reference to FIG. FIG. 16 is a diagram showing a flowchart of an internal lottery process performed by the main control circuit 60 of the present embodiment. The internal lottery process is a process that is executed when called in the process of step S7 of the reset interrupt process by the main CPU 31 described above.

  First, the main CPU 31 refers to the lottery count determination table (see FIG. 7) and determines the lottery count based on the gaming state (step S31). Specifically, when the main CPU 31 refers to the gaming state identifier for identifying the gaming state and determines that it is the general gaming state or the FT gaming state, the main CPU 31 determines “5” as the number of lotteries, When it is determined that the state is the state, “3” is determined as the number of lotteries.

  Next, the main CPU 31 determines whether or not the carryover combination storage area is “00000000” (step S32). Specifically, the main CPU 31 determines whether or not it is in the BB carryover state. When the main CPU 31 determines that the carryover combination storage area is “00000000”, that is, determines that the carryover combination storage area is not in the BB carryover state, the main CPU 31 proceeds to the processing of step S34.

  On the other hand, when the main CPU 31 determines in the process of step S32 that the carryover combination storage area is not “00000000”, that is, is in the BB carryover state, the main CPU 31 changes the number of lotteries to “4” (step S33). By changing the number of lotteries to “4”, the main CPU 31 avoids determining the BB as an internal winning combination again in the subsequent processing despite the BB carryover state. When this process ends, the main CPU 31 proceeds to the process of step S34.

  Next, the main CPU 31 sets the same value as the number of lotteries in the winning number (step S34). Next, the main CPU 31 refers to the internal lottery table (see FIG. 8) and determines whether or not the random number value stored in the RAM 33 is equal to or greater than the lower limit value determined based on the winning number and the inserted number counter (step S35). . At this time, when the main CPU 31 determines that the random number value is not equal to or lower than the lower limit value, the main CPU 31 proceeds to the process of step S41.

  On the other hand, when the main CPU 31 determines in the process of step S35 that the random number value is greater than or equal to the lower limit value, the main CPU 31 similarly refers to the internal lottery table (see FIG. 8), and the random number value stored in the RAM 33 is the winning number. Then, it is determined whether or not it is equal to or less than an upper limit value determined based on the insertion number counter (step S36). At this time, when the main CPU 31 determines that the random number value is not less than or equal to the upper limit value, the main CPU 31 proceeds to the process of step S41.

  On the other hand, when the main CPU 31 determines in the process of step S36 that the random number value is equal to or smaller than the upper limit value, the main CPU 31 then stores the winning number in the winning number storage area (step S37). Specifically, “1” is set to the bit corresponding to the winning number. For example, when the winning number is “5”, “1” is set in “bit 4” of the winning number storage area. Depending on the setting of the winning range of the internal lottery table, the process may be executed a plurality of times in the unit game. In this case, the main CPU 31 sets “1” to the corresponding bit as needed.

  Next, the main CPU 31 refers to the internal winning combination determination table (see FIG. 9) and determines an internal winning combination based on the gaming state and the winning number (step S38). For example, the main CPU 31 determines BB as an internal winning combination when the gaming state is the general gaming state and the winning number is “5”.

  Next, the main CPU 31 calculates the logical product of the 8-bit bit pattern corresponding to the internal winning combination determined in the process of step S38 and the bonus check data (see FIG. 11 (1)), and this bit pattern and carryover The logical sum with the combination storage area is stored in the carryover combination storage area (step S39). For example, when the internal winning combination is BB and the carryover combination storing area is “00000000”, the main CPU 31 sets a bit pattern “00010000” corresponding to the internal winning combination BB and bonus check data “00010000”. And “00010000”, which is the logical sum of this and the carryover combination storage area “00000000”, is stored in the carryover combination storage area.

  Next, the main CPU 31 stores the logical sum of the 8-bit bit pattern corresponding to the internal winning combination and the carryover combination storing area in the internal winning combination storing area (step S40). For example, when the internal winning combination is a watermelon and the carryover combination storing area is “00010000”, the main CPU 31 sets the bit pattern “00000100” corresponding to the watermelon that is the internal winning combination and the carryover combination storing area “00010000”. Is stored in the internal winning combination storing area. When this process ends, the main CPU 31 proceeds to the process of step S41.

  Next, the main CPU 31 determines in the process of step S35 that the random number value is not greater than or equal to the lower limit value, determines in the process of step S36 that the random number value is not less than or equal to the upper limit value, or in step S40. When the process is finished, “1” is subtracted from the number of lotteries (step S41).

  Next, the main CPU 31 determines whether or not the number of lotteries is “0” (step S42). When the main CPU 31 determines that the number of lotteries is “0”, the main CPU 31 proceeds to the process of step S43.

  On the other hand, when the main CPU 31 determines in the process of step S42 that the number of lotteries is not “0”, the main CPU 31 proceeds to the process of step S34. Thereafter, the main CPU 31 repeats the processing from step S34 to step S42 (hereinafter referred to as “repetition processing”) until the number of lotteries becomes “0”.

  Next, the main CPU 31 refers to the internal winning combination determination table and determines an internal winning combination based on the gaming state and the winning number stored in the winning number storage area (step S43). For example, when the bit pattern of the winning number storage area is “00000000”, the main CPU 31 determines a loss (bit pattern is “00000000”) as an internal winning combination. Further, when the bit pattern of the winning number storage area is “00000010”, the main CPU 31 determines a bell (bit pattern is “00000010”) as an internal winning combination.

  Next, the main CPU 31 stores the logical sum of the internal winning combination and the internal winning combination storing area in the internal winning combination storing area (step S44). For example, when the internal winning combination is lost (bit pattern “00000000”) and the bit pattern of the internal winning combination storage area is “00000000”, the main CPU 31 sets the bit pattern “00000000” in the internal winning combination storage area. Is stored. When the internal winning combination is Bell (bit pattern “00000010”) and the bit pattern of the internal winning combination storage area is “00000010”, the main CPU 31 stores the bit pattern “00000010” in the internal winning combination storage area. Is stored.

  Next, the main CPU 31 stores the logical sum of the internal symbol combination storage area and the carryover combination storage area in the internal symbol combination storage area (step S45). For example, if the bit pattern “00000000” of the internal winning combination storage area and the value of the carryover combination storing area is “00010000”, the main CPU 31 stores the bit pattern “00010000” in the internal winning combination storage area. To do. Further, the main CPU 31 stores the bit pattern “00010010” in the internal winning combination storing area when the bit pattern “00000010” in the internal winning combination storing area and the value of the carryover combination storing area is “00010000”. To do. When this process ends, the main CPU 31 ends the internal lottery process and proceeds to the process of step S8 in FIG.

  Here, the main CPU 31 performs a lottery of an internal winning combination by executing the above-described repetitive processing. Specifically, the main CPU 31 determines the winning number by sequentially determining whether the random number value in the RAM 33 is in any winning range of the internal lottery table, and determines the winning combination corresponding to the winning number. A role. Further, the main CPU 31 edits the winning number storage area, the internal winning combination storage area, and the carryover storage area based on the winning number and the internal winning combination in the repetition process.

  On the other hand, if the main CPU 31 determines that the random number value in the RAM 33 does not fall within any winning range of the internal lottery table, the main CPU 31 ends the repetitive processing without executing the processing from step S37 to step S40. Become. In this case, since the internal winning combination is not determined in the repetitive processing, and the winning number storage area, the internal winning combination storage area and the carryover combination storing area are not edited, the winning number storage area is “00000000” The internal winning combination storage area is in a state of “00000000”. However, the carryover combination storage area is “00010000” in the BB carryover state.

  Accordingly, in this case, the main CPU 31 determines a loss as an internal winning combination based on the fact that the winning number storage area is “00000000” in the process of step S43. Further, if the internal winning combination is lost even if the internal winning combination is lost, the main CPU 31 must set the bit pattern of the internal winning combination storing area to “00010000” at the end of the internal lottery process. The process of step S45 is performed.

  As described above, the processing from step S43 to step S45 is processing that is provided in the case where the internal winning combination is lost. However, even if one of the winning combinations is determined as an internal winning combination by this repeated processing and the internal winning combination storing area is edited, the processing from step S43 to step S45 is executed, so that the internal winning combination is achieved. The consistency of the role storage area is not hindered. That is, the main CPU 31 determines the internal winning combination based on the winning number stocked in the winning number storage area in the process of step 43.

  Next, the FT control process will be described with reference to FIG. FIG. 17 is a diagram illustrating a flowchart of the FT control process performed by the main control circuit 60 of the present embodiment. The FT control process is a process that is executed when triggered by being called in the process of step S8 of the reset interrupt process by the main CPU 31 described above.

  First, the main CPU 31 determines whether or not the value of the FT game number counter is “1” or more (step S61). At this time, when the main CPU 31 determines that the value of the FT game number counter is “1” or more, it subtracts “1” from the value of the FT game number counter (step S62). When the main CPU 31 finishes this process, it ends the FT control process.

  On the other hand, when the main CPU 31 determines that the value of the FT game number counter is not “1” or more in the process of step S61, it next determines whether or not the gaming state is a general gaming state (step S63). . At this time, when the main CPU 31 determines that the gaming state is not the general gaming state, the main CPU 31 ends the FT control process.

  On the other hand, in the process of step S63, when the main CPU 31 determines that the gaming state is the general gaming state, the main CPU 31 then determines whether or not the internal winning combination is a watermelon (step S64). When it is determined that the internal winning combination is not a watermelon, the FT control process is terminated.

  On the other hand, in the process of step S64, when the main CPU 31 determines that the internal winning combination is a watermelon, it sets “100” in the FT game number counter (step S65). Thereby, the gaming state is updated to the FT gaming state in the process of step S6 in the next unit game. Note that the FT game state continues until the 100 unit game ends or the BB operation state operates. When the main CPU 31 finishes this process, it ends the FT control process.

  When the main CPU 31 ends the FT control process, the main CPU 31 proceeds to the process of step S9 in FIG.

  Next, the reel stop control process will be described with reference to FIG. FIG. 18 is a flowchart of the reel stop control process performed by the main control circuit 60 of this embodiment. The reel stop control process is a process for stopping the symbols of the reels 3L, 3C, and 3R based on a stop signal output from the stop switches 7LS, 7CS, and 7RS based on the stop operation of the player. is there.

  First, the main CPU 31 determines whether or not a valid stop switch is turned on (step S101). Specifically, the main CPU 31 determines whether stop switches 7LS, 7CS, and 7RS corresponding to the rotating reels 3L, 3C, and 3R are turned on based on a stop operation by the player. At this time, when the main CPU 31 determines that the effective stop switch is not turned on, the main CPU 31 repeats the process of step S101 until it is determined that the effective stop switch is turned on.

  On the other hand, when the main CPU 31 determines in the process of step S101 that the effective stop switch has been turned on, the main CPU 31 performs the sliding top based on the internal winning combination determined in the process of step S41 of the internal lottery process (see FIG. 16). The number is determined (step S102).

  Next, the main CPU 31 determines the planned stop positions of the reels 3L, 3C, 3R based on the number of sliding symbols determined in the process of step S102 and the current symbol position (step S103).

  Next, the main CPU 31 transmits a reel stop command to the sub control circuit 61 (step S104).

  Next, the main CPU 31 determines whether or not all reels have been stopped (step S105). At this time, when determining that all the reels are not stopped, the main CPU 31 repeats the processing from step S101 to step S104 until it is determined that all the reels are stopped.

  On the other hand, when the main CPU 31 determines in the process of step S105 that all the reels have stopped, the main CPU 31 ends the reel stop control process, and proceeds to the process of step S15 in FIG.

  Next, the bonus end check process will be described with reference to FIG. FIG. 19 is a flowchart of the bonus end check process performed in the main control circuit 60 of the present embodiment. Further, this bonus end check process is a process of updating the RB game possible number and the winning possible number, BB end time process, and RB end time process.

  First, the main CPU 31 determines whether or not a winning is achieved (step S81). At this time, when the main CPU 31 determines that no winning has been established, the main CPU 31 proceeds to the processing of step S87. Here, winning means that a medal is paid out by displaying a combination of symbols related to small roles such as cherry, bell, and watermelon.

  On the other hand, when the main CPU 31 determines in the process of step S81 that a winning has been established, the main CPU 31 determines whether or not the bonus end number counter is “0” (step S82). At this time, when the main CPU 31 determines that the bonus end number counter is not “0”, the main CPU 31 proceeds to the process of step S85.

  On the other hand, when the main CPU 31 determines in the process of step S82 that the bonus end number counter is “0”, the main CPU 31 performs the RB end process (step S83). Specifically, the main CPU 31 turns off the RB operating flag and performs processing such as setting a command indicating the end of the RB gaming state.

  Next, the main CPU 31 performs processing at the end of BB (step S84). Specifically, the main CPU 31 performs processing such as turning off the BB operating flag. When this process ends, the main CPU 31 ends the bonus end check process and proceeds to the process of step S21 in FIG.

  On the other hand, when the main CPU 31 determines in the process of step S82 that the bonus end number counter is not “0”, the main CPU 31 subtracts “1” from the winning possible number counter (step S85).

  Next, the main CPU 31 determines whether or not the winning possible number counter obtained by subtracting “1” in the process of step S85 is “0” (step S86). At this time, when the main CPU 31 determines that the winning possible number counter is “0”, the main CPU 31 proceeds to the process of step S89. On the other hand, when the main CPU 31 determines that the winning possible number counter is not “0”, the main CPU 31 proceeds to the process of step S87.

  Next, when the main CPU 31 determines that a winning is not established in the process of step S81, or when it is determined that the winning possible number counter is not “0” in the process of step S86, the possible game number counter Then, “1” is subtracted from (Step S87).

  Next, the main CPU 31 determines whether or not the possible game number counter obtained by subtracting “1” in the process of step S87 is “0” (step S88). At this time, when the main CPU 31 determines that the possible game number counter is not “0”, the main CPU 31 ends the bonus end check process and proceeds to the process of step S21 in FIG. On the other hand, when the main CPU 31 determines that the possible game number counter is “0”, the main CPU 31 proceeds to the process of step S89.

  Next, when the main CPU 31 determines in the process of step S86 that the possible winning number counter is “0”, or in the process of step S88, determines that the possible game number counter is “0”. , RB end processing is performed (step S89). Specifically, the main CPU 31 turns off the RB operating flag and performs a predetermined process such as setting a command indicating the end of the RB gaming state. When this process ends, the main CPU 31 ends the bonus end check process and proceeds to the process of step S21 in FIG.

  Next, the bonus operation check process will be described with reference to FIG. FIG. 20 is a flowchart of the bonus operation check process performed by the main control circuit 60 of the present embodiment. The bonus operation check process is a process for generating a BB operation state when the display combination is BB.

  First, the main CPU 31 determines whether or not the display combination is BB (step S91). At this time, when the main CPU 31 determines that the display combination is not BB, the main CPU 31 ends the bonus operation check process and proceeds to the process of step S2 in FIG.

  On the other hand, when the main CPU 31 determines in step S91 that the display combination is BB, the main CPU 31 performs BB operation processing based on the BB operation table (step S92). Specifically, the main CPU 31 refers to the bonus operating time table, sets “350” in the bonus end number counter, and turns on the BB operating flag. Further, when the FT game number counter is larger than “1”, the main CPU 31 clears this.

  Next, the main CPU 31 clears the carryover combination storage area (step S93). When this process ends, the main CPU 31 ends the bonus operation check process and proceeds to the process of step S2 in FIG.

  Next, with reference to FIG. 21, an interrupt process under the control of the main CPU will be described. FIG. 21 is a diagram showing a flowchart of the interrupt process under the control of the main CPU performed by the main control circuit 60 of the present embodiment. Further, the interrupt process under the control of the main CPU is an interrupt process that occurs every predetermined period (for example, 1.1173 milliseconds).

  First, the main CPU 31 interrupts the program being executed before calling the interrupt process under the control of the main CPU, and saves the address indicating the interrupted position and the values of various registers in a predetermined area of the RAM 33. (Step S401). This is because when the interrupt process under the control of the main CPU is completed, the address indicating the interrupted position of the saved program and the values of various registers are restored, and the program is continuously executed from the point of interruption. It is.

  Next, the main CPU 31 performs input port check processing for checking the I / O port 38 (step S402), and then adds “1” to the interrupt counter (step S403).

  Next, the main CPU 31 determines whether or not the value of the interrupt counter is an even number (step S404). At this time, when the main CPU 31 determines that the value of the interrupt counter is an even number, the main CPU 31 proceeds to the processing of step S411.

  On the other hand, when the main CPU 31 determines in step S404 that the value of the interrupt counter is not an even number, the main CPU 31 sets an identifier indicating the left reel to the rotation control reel identifier for determining the target reel for rotation control (step S404). S405). The main CPU 31 performs reel rotation control based on the rotation control reel identifier in a reel control process described later.

  Next, the main CPU 31 performs a reel control process described later with reference to FIG. 22 based on the rotation control reel identifier set in the process of step S405 (step S406).

  Next, the main CPU 31 sets an identifier indicating a middle reel as a rotation control reel identifier for determining a target reel for rotation control (step S407).

  Next, the main CPU 31 performs a reel control process described later with reference to FIG. 22 based on the rotation control reel identifier set in the process of step S407 (step S408).

  Next, the main CPU 31 sets an identifier indicating the right reel as a rotation control reel identifier for determining a target reel for rotation control (step S409).

  Next, the main CPU 31 performs a reel control process described later with reference to FIG. 22 based on the rotation control reel identifier set in the process of step S409 (step S410).

  Next, when the main CPU 31 determines that the value of the interrupt counter is an even number in the process of step S404, or when the reel control process is performed in step S410, the main CPU 31 performs a lamp / 7SEG drive control process ( Step S411). Specifically, the main CPU 31 drives and controls the BET lamps 9 a, 9 b, 9 c and the WIN lamp 17 via the lamp driving circuit 45. Thereby, the BET lamps 9a, 9b, 9c and the WIN lamp 17 are turned on and off. Further, the main CPU 31 drives and controls the payout number display unit 18 and the credit display unit 19 via the display unit drive circuit 48. As a result, various information (such as the number of credits) is displayed on the payout number display unit 18 and the credit display unit 19.

  Next, the main CPU 31 refers to the value saved in the RAM 33 in the process of step S401 and restores the register (step S412). When this process ends, the interrupt process under the control of the main CPU is ended, and the program interrupted by the occurrence of the interrupt process under the control of the main CPU is continuously executed.

  Next, the reel control processing will be described with reference to FIG. FIG. 22 is a diagram illustrating a flowchart of the reel control process performed by the main control circuit 60 of the present embodiment.

  First, the main CPU 31 refers to the rotation control reel identifier set in step S405, step S407, and step S409 of the interrupt process (see FIG. 21) under the control of the main CPU described above, and the corresponding reel is in rotation control. It is determined whether or not (step S421). At this time, when the main CPU 31 determines that the corresponding reel is not under rotation control, the main CPU 31 ends the reel control process.

  On the other hand, when the main CPU 31 determines in the process of step S421 that the corresponding reel is under rotation control, the main CPU 31 determines whether or not the reel is in a waiting state for a planned stop position (step S422). Here, the waiting state for the planned stop position refers to a state of waiting for the corresponding rotating reel to reach the planned position for stopping the rotation. In this state, the rotation of the reel is maintained at a constant speed. When the main CPU 31 determines that the corresponding reel is not waiting for the scheduled stop position, the main CPU 31 proceeds to the process of step S425.

  Next, when the main CPU 31 determines in the process of step S422 that the corresponding reel is waiting for the planned stop position, the main CPU 31 determines whether or not the reel has reached the planned stop position (step S423). When the main CPU 31 determines that the corresponding reel has not reached the scheduled stop position, the main CPU 31 proceeds to the process of step S425.

  On the other hand, when the main CPU 31 determines in step S423 that the corresponding reel has reached the scheduled stop position, the main CPU 31 shifts the control state of the reel to the deceleration control state (step S424).

  Next, when the main CPU 31 determines in the process of step S422 that the corresponding reel is not waiting for the planned stop position, the main CPU 31 determines in the process of step S423 that the corresponding reel has not reached the planned stop position. Alternatively, when the control state of the corresponding reel is shifted to the deceleration control state in the process of step S424, the reel rotation acceleration control, constant speed control, deceleration control, or stop is performed according to the reel control state. Control is performed (step S425). The main CPU 31 ends the reel control process after completing the process of step S425.

  Next, control operations of the image control microcomputer 72 and the sound / lamp control microcomputer 92 of the sub-control circuit 61 will be described with reference to flowcharts shown in FIGS.

  First, with reference to FIG. 23, the reset interruption process by the image control microcomputer 72 will be described. FIG. 23 is a diagram showing a flowchart of reset interrupt processing by the image control microcomputer 72 of this embodiment. Further, the image control microcomputer 72 generates a reset interrupt when the power is turned on and a voltage is applied to the reset terminal, and the reset interrupt process stored in the program ROM 73 based on the occurrence of the interrupt. Are sequentially performed.

  First, the image control microcomputer 72 performs initialization when power is turned on (step S201). Specifically, the image control microcomputer 72 performs initial setting of a storage area such as a work RAM 74 provided in the image control circuit.

  Next, the image control microcomputer 72 performs input monitoring processing for the command transmitted from the main control circuit 60 (step S202). Specifically, in the input monitoring process, the image control microcomputer 72 determines whether various commands such as a start command and a display combination command are received.

  Next, the image control microcomputer 72 performs a command input process which will be described later with reference to FIG. 27 (step S203). Specifically, in the command input process, when various commands are received, the image control microcomputer 72 performs a predetermined process based on the received commands.

  Next, the image control microcomputer 72 performs image drawing processing (step S204). Specifically, the image control microcomputer 72 reads image data from the work RAM 74 and transmits the read image data and information related to the display position and size of the image data to the image control IC 76. Further, the image control IC 76 stores the received image data in one frame buffer area provided in the video RAM 80.

  Next, the image control microcomputer 72 determines whether or not the VDP counter is “2” (step S205). At this time, if the image control microcomputer 72 determines that the VDP counter is “2”, the process proceeds to step S206. On the other hand, when the image control microcomputer 72 determines that the VDP counter is not “2”, it proceeds to the process of step S205 again, and repeats the process of step S205 until the VDP counter becomes “2”. The VDP counter is counted up when a periodic signal reception process from the image control IC 76 described later occurs at a predetermined cycle (every 1/60 seconds). Thereby, in this embodiment, a display image will be switched every 1/30 second.

  Next, when the image control microcomputer 72 determines that the VDP counter has reached “2” in the process of step S205, the image control microcomputer 72 sets “0” to the VDP counter (step S206). A bank switching command is transmitted, and the display image data area and the writing image data area are switched (step S207). That is, the bank switching process is performed. In addition, the image control IC 97 receives the bank switching command to output the image data written in the write image data area to the liquid crystal display device 5 and replace the display image data area with the write image data area. Then, image data to be displayed next is written. When this process ends, the image control microcomputer 72 proceeds to the process of step S202.

  Next, with reference to FIG. 24, the periodic signal reception process from the image control IC 76 will be described. FIG. 24 is a diagram illustrating a flowchart of a regular signal reception process from the image control IC 76 according to the present embodiment. The regular signal reception process from the image control IC 76 is an interrupt process that occurs every predetermined period (for example, 1/60 seconds).

  In this periodic signal reception process, the image control microcomputer 72 interrupts the program being executed before calling the periodic signal reception process, and stores the address indicating the interrupted position and the values of various registers in a predetermined area of the work RAM 74. Evacuate to. In addition, when the periodic signal reception process is completed, the image control microcomputer 72 restores the address indicating the position where the saved program is interrupted and the values of various registers, and continues to execute the program from the point of interruption. To do.

  In the regular signal reception process, the image control microcomputer 72 adds “1” to the VDP counter (step S321). When this process ends, the image control microcomputer 72 ends the regular signal reception process and continues the reset interrupt process interrupted by the occurrence of the regular signal reception process.

  Next, a command signal reception interrupt process performed by the image control microcomputer 72 when a command transmitted from the main control circuit 60 is received will be described with reference to FIG. FIG. 25 is a diagram showing a flowchart of command signal reception interrupt processing from the main control circuit 60 of this embodiment. The command signal reception interrupt process by the image control microcomputer 72 is an interrupt process that is called when a command transmitted from the main control circuit 60 is received.

  Similar to the periodic signal reception processing from the image control IC 76, the image control microcomputer 72 interrupts the program being executed before calling the command signal reception interrupt processing, and addresses indicating the interrupted position and various registers The value is saved in a predetermined area of the work RAM 74. Further, when the command signal reception interrupt process is completed, the image control microcomputer 72 restores the address indicating the interrupted position of the saved program and the values of various registers, and continues the program from the point of interruption. And execute.

  When receiving the command signal from the main control circuit 60, the image control microcomputer 72 interrupts the reset interrupt process, and then stores the data corresponding to the received command in the work RAM 74 as an unprocessed command (step S331). The command reception interrupt process is terminated, and the reset interrupt process interrupted by the occurrence of the command signal reception interrupt process is continued.

  Next, the periodic interruption process by the sound / lamp control microcomputer 92 will be described with reference to FIG. FIG. 26 is a diagram showing a flowchart of periodic interruption processing by the sound / lamp control microcomputer 92 of the present embodiment. In addition, this periodic interrupt process is an interrupt process that occurs every predetermined period (for example, 2 milliseconds).

  Similar to the periodic signal reception process from the image control IC 76, the sound / lamp control microcomputer 92 interrupts the program being executed before the periodic interrupt process is executed, The register value is saved in a predetermined area of the work RAM 93. In addition, when the periodic interrupt process ends, the sound / lamp control microcomputer 92 restores the address indicating the interrupted position of the saved program and the values of various registers, and continues the program from the point of interruption. And execute.

  First, the sound / lamp control microcomputer 92 performs a sound output control process based on the effect data (step S341). Specifically, in the sound output control process, the sound / lamp control microcomputer 92 causes the sound source IC 95 to generate a sound signal corresponding to the effect data, and outputs the sound signal from the speakers 21L and 21R at a predetermined timing.

  Next, the sound / lamp control microcomputer 92 performs lamp lighting control processing based on the effect data (step S342). Specifically, in the lamp lighting control process, the sound / lamp control microcomputer 92 controls the lighting of the LED 101 and the lamp 102 so as to perform a lighting mode corresponding to the effect data. When this process ends, the sound / lamp control microcomputer 92 ends the periodic interrupt process and continues to execute the program interrupted by the occurrence of the periodic interrupt process.

  Next, command input processing by the image control microcomputer 72 will be described with reference to FIG. FIG. 27 is a diagram showing a flowchart of command input processing by the image control microcomputer 72 of this embodiment. The command input process is a process for determining whether or not a command has been received and performing predetermined control based on the command.

  First, the image control microcomputer 72 determines whether or not the command transmitted from the main control circuit 60 has been received (step S211). If the image control microcomputer 72 determines that the command transmitted from the main control circuit 60 has not been received, the image control microcomputer 72 ends the command input process and proceeds to the process of step S204 in FIG.

  On the other hand, when determining that the command transmitted from the main control circuit 60 has been received in the process of step S211, the image control microcomputer 72 performs a command corresponding execution process described later with reference to FIG. 28 (step S212). Specifically, the image control microcomputer 72 performs medal insertion processing, game start processing, reel stop processing, and display processing based on the received command type.

  Next, the image control microcomputer 72 sets the unprocessed command for which the command corresponding execution process has been performed to be processed (step S213). Specifically, the image control microcomputer 72 clears an unprocessed command stored in the work RAM 74 in the command signal reception interrupt process. When this process ends, the image control microcomputer 72 ends the command input process and proceeds to the process of step S204 in FIG.

  Next, with reference to FIG. 28, a command response execution process by the image control microcomputer 72 will be described. FIG. 28 is a diagram showing a flowchart of command response execution processing by the image control microcomputer 72 of this embodiment. In the command corresponding execution process, a predetermined process is performed based on the type of the received command.

  First, the image control microcomputer 72 determines whether or not the received command is a medal insertion command (step S221). When the image control microcomputer 72 determines that the received command is a medal insertion command, the image control microcomputer 72 performs medal insertion processing described later with reference to FIG. 29 (step S222). Specifically, in the medal insertion process, the image control microcomputer 72 sets an in-game identifier. When this process ends, the image control microcomputer 72 ends the command corresponding execution process, sets the unprocessed command to “processed” in the command input process (see FIG. 27) (step S213), and performs the process of step S204 in FIG. Migrate to

  Next, when the image control microcomputer 72 determines in step S221 that the received command is not a medal insertion command, it determines whether or not the received command is a start command (step S223). When determining that the received command is a start command, the image control microcomputer 72 performs a game start process which will be described later with reference to FIG. 30 (step S224). Specifically, in the game start process, the image control microcomputer 72 determines an effect identifier and sets start effect data. When this process ends, the image control microcomputer 72 ends the command corresponding execution process, sets the unprocessed command to “processed” in the command input process (see FIG. 27) (step S213), and performs the process of step S204 in FIG. Migrate to

  Next, when determining in step S223 that the received command is not a start command, the image control microcomputer 72 determines whether or not the received command is a reel stop command (step S225). When determining that the received command is a reel stop command, the image control microcomputer 72 performs a reel stop process which will be described later with reference to FIG. 33 (step S226). Specifically, in the reel stop process, the image control microcomputer 72 sets the first stop effect data, the second stop effect data, the third stop effect data, and the like. When this process ends, the image control microcomputer 72 ends the command corresponding execution process, sets the unprocessed command to “processed” in the command input process (see FIG. 27) (step S213), and performs the process of step S204 in FIG. Migrate to

  Next, when the image control microcomputer 72 determines in step S225 that the received command is not a reel stop command, whether the received command is a display combination command having information of a display combination flag for specifying a display combination. It is determined whether or not (step S227). When determining that the received command is a display combination command, the image control microcomputer 72 performs a display process described later with reference to FIG. 34 (step S228). Specifically, in the display process, display effect data is set. When this process ends, the image control microcomputer 72 ends the command corresponding execution process, sets the unprocessed command as processed in the command input process (see FIG. 27) (step S213), and performs step S204 in FIG. Move on to processing.

  Next, when the image control microcomputer 72 determines in step S227 that the received command is not a display combination command, the image control microcomputer 72 determines effect data corresponding to the received command (step S229). When this process ends, the image control microcomputer 72 ends the command corresponding execution process, sets the unprocessed command to “processed” in the command input process (see FIG. 27) (step S213), and performs the process of step S204 in FIG. Migrate to

  Next, with reference to FIG. 29, a medal insertion process by the image control microcomputer 72 will be described. FIG. 29 is a diagram showing a flowchart of medal insertion processing by the image control microcomputer 72 of the present embodiment. The medal insertion process is a process that is executed when a medal insertion command is received.

  First, the image control microcomputer 72 extracts a medal insertion command stored in the work RAM 74 as an unprocessed command (step S251).

  Next, the image control microcomputer 72 determines whether or not the in-game identifier of the work RAM 74 is “0” (step S252). When determining that the in-game identifier is not “0”, the image control microcomputer 72 ends the medal insertion process.

  On the other hand, when the image control microcomputer 72 determines that the in-game identifier is “0” in the process of step S252, it sets “1” in the in-game identifier (step S253). The image control microcomputer 72 ends the medal insertion process when this process ends.

  When the medal insertion process is completed, the image control microcomputer 72 returns to the command input process of FIG. 27 through the command corresponding execution process of FIG. 28, sets the unprocessed command to processed (step S213), The process proceeds to step S204.

  Next, a game start process by the image control microcomputer 72 will be described with reference to FIG. FIG. 30 is a diagram showing a flowchart of the game start process by the image control microcomputer 72 of this embodiment. The game start process is a process that is executed when a start command is received.

  First, the image control microcomputer 72 extracts a start command stored in the work RAM 74 as an unprocessed command, and stores a game state identifier, a winning combination identifier, a carryover combination identifier, an FT game number counter, etc. included in the start command. The work RAM 74 is set (step S261).

  Next, the image control microcomputer 72 performs FT count processing described later with reference to FIG. 31 (step S262). In this FT counting process, the image control microcomputer 72 counts the number of lost internal winnings during the FT gaming state. Further, in the final unit game in the FT game state, the URL information is encoded based on the number of internal winnings of the lost game.

  Next, the image control microcomputer 72 refers to the effect identifier determination table (FIG. 12 (1)) and determines the effect identifier based on the winning combination identifier (step S263).

  Next, the image control microcomputer 72 refers to the effect data determination table (see FIG. 12 (2)), and determines start effect data based on the effect identifier determined in the process of step S263 (step S264). For example, when the effect identifier is “A1”, the image control microcomputer 72 determines “A1-1” as the start effect data. The gaming machine 1 performs an effect at the start of the game using the liquid crystal display device 5, the LED 101, the lamp, the speakers 21L, 21R, and the like based on the start effect data.

  Next, the image control microcomputer 72 clears the stop reel number counter (step S265). When this process ends, the image control microcomputer 72 ends the game start process, returns to the command input process of FIG. 27 via the command corresponding execution process of FIG. 28, and sets the unprocessed command as processed (step S213), the process proceeds to step S204 in FIG.

  Next, the FT counting process by the image control microcomputer 72 will be described with reference to FIG. FIG. 31 is a view showing a flowchart of the FT counting process by the image control microcomputer 72 of the present embodiment. The FT counting process is a process that is executed when called in the process of step S262 of the game start process described above.

  First, the image control microcomputer 72 determines whether or not the FT gaming state is set (step S291). Specifically, the image control microcomputer 72 refers to the gaming state identifier to determine whether or not the FT gaming state. At this time, if the image control microcomputer 72 determines that it is not in the FT gaming state, it ends the FT counting process, and proceeds to the process of step S263 of the game start process (see FIG. 30).

  On the other hand, when the image control microcomputer 72 determines in the process of step S291 that the game is in the FT gaming state, the image control microcomputer 72 then determines whether or not the internal winning combination is lost (step S292). At this time, when the image control microcomputer 72 determines that the internal winning combination is not lost, the process proceeds to step S294.

  On the other hand, if the image control microcomputer 72 determines that the internal winning combination is a loss in the process of step S292, then the image control microcomputer 72 adds “1” to the loss count counter (step S293).

  Next, the image control microcomputer 72 determines whether or not the FT game number counter is “0” when the internal winning combination is determined not to be lost in the process of step S292 or after the process of step S293. Is determined (step S294). At this time, when the image control microcomputer 72 determines that the FT game number counter is not “0”, the image control microcomputer 72 ends the FT counting process and proceeds to the process of step S263 of the game start process (see FIG. 30).

  On the other hand, if the image control microcomputer 72 determines that the FT game number counter is “0” in the process of step S294, the image control microcomputer 72 performs an encoding process (see FIG. 32) described later (step S295). In the encoding process, the image control microcomputer 72 acquires URL information from the URL setting information table (see FIG. 13) based on the value of the number-of-loss counter, and generates a two-dimensional code indicating the URL information.

  Next, the image control microcomputer 72 resets the loss count counter (step S296). When this process ends, the image control microcomputer 72 ends the FT counting process and proceeds to the process of step S263 of the game start process (see FIG. 30).

  Note that the lost count counter is a counter for counting the number of times the lose is internally won in the FT gaming state. Further, the image control microcomputer 72, in the final unit game in the FT gaming state, stores the two-dimensional code and the number of lost times in the two-dimensional code display area 200 and the number display area 210, respectively, based on the value of the number of lost times counter at that time. Display.

  Next, an encoding process performed by the image control microcomputer 72 will be described with reference to FIG. FIG. 32 is a diagram showing a flowchart of encoding processing by the image control microcomputer 72 of this embodiment. The encoding process is a process that is executed when called in the process of step S295 of the FT counting process described above.

  First, the image control microcomputer 72 refers to the URL information setting table (see FIG. 13), acquires URL information based on the value of the number of lost times counter, and stores it in the work RAM 74 (step S301). For example, when the value of the loss counter is “0”, the image control microcomputer 72 refers to the URL information setting table and sets “http: //***.***/001. htm ”is acquired and stored in the work RAM 74.

  Next, the image control microcomputer 72 creates a mode identifier in the work RAM 74 according to the character type such as numerals and alphanumeric characters of the acquired URL information (step S302).

  Next, the image control microcomputer 72 creates a character number identifier corresponding to the number of characters in the acquired URL information in the work RAM 74 (step S303).

  Next, the image control microcomputer 72 performs a process of binarizing the acquired URL information (step S304).

  Next, the image control microcomputer 72 adds a termination pattern to the data obtained by the processing from step S301 to step S304 described above (step S305).

  Next, the image control microcomputer 72 performs code word conversion of the data obtained by the process of step S305 described above (step S306).

  Next, the image control microcomputer 72 creates an error correction code word based on the data obtained by the process of step S306 described above, and adds it to the data obtained by the process of step S306 (step S307).

  Next, the image control microcomputer 72 binarizes the data obtained by the process of step S307 described above, and performs a process of arranging in a matrix (step S308).

  Next, the image control microcomputer 72 performs a process of masking a predetermined pattern on the data obtained by the process of step S308 described above (step S309).

  Next, the image control microcomputer 72 performs a process of adding format information including an error correction level and a mask identifier to the data obtained by the process of step S309 described above (step S310), and generates a two-dimensional code. (Step S311). The image control microcomputer 72 stores the generated two-dimensional code in the work RAM 74. When this process ends, the image control microcomputer 72 ends the encoding process, and proceeds to the process of step S296 of the FT count process (see FIG. 31).

  Next, the reel stop process by the image control microcomputer 72 will be described with reference to FIG. FIG. 33 is a diagram showing a flowchart of reel stop processing by the image control microcomputer 72 of this embodiment. The reel stop process is a process that is executed when a reel stop command is received.

  First, the image control microcomputer 72 extracts a reel stop command stored in the work RAM 74 as an unprocessed command, and sets a stop reel identifier and a stop symbol identification number included in the reel stop command in the work RAM 74 (steps). S271).

  Next, the image control microcomputer 72 determines whether or not the reel 3 to be stopped is the first stop based on the stop reel identifier (step S272). When the image control microcomputer 72 determines that the reel 3 to be stopped is the first stop, the image control microcomputer 72 refers to the effect data determination table (see FIG. 12 (2)), and based on the effect identifier, the first stop effect data Is set (step S273). For example, when the effect identifier is “A1”, the image control microcomputer 72 determines “A1-2” as the first stop effect data. The gaming machine 1 performs an effect at the time of the first stop using the liquid crystal display device 5, the LED 101, the lamp, the speakers 21L, 21R, and the like based on the first stop effect data. When this process ends, the image control microcomputer 72 ends the reel stop process.

  On the other hand, when the image control microcomputer 72 determines in the process of step S272 that the reel 3 to be stopped is not the first stop, it determines whether or not the reel 3 to be stopped is the second stop based on the stop reel identifier. (Step S274). When it is determined that the reel 3 to be stopped is the second stop, the image control microcomputer 72 refers to the effect data determination table and sets the second stop effect data based on the effect identifier (step S275). For example, when the effect identifier is “A1”, the image control microcomputer 72 determines “A1-3” as the second stop effect data. Based on the second stop effect data, the gaming machine 1 uses the liquid crystal display device 5, the LED 101, the lamp, the speakers 21L, 21R, etc. to perform the effect at the second stop time. When this process ends, the image control microcomputer 72 ends the reel stop process.

  On the other hand, when determining that the reel 3 to be stopped is not the second stop in the process of step S274, the image control microcomputer 72 refers to the effect data determination table and determines the third stop effect data based on the effect identifier. Set (step S276). For example, when the effect identifier is “A1”, the image control microcomputer 72 determines “A1-4” as the third stop effect data. The gaming machine 1 performs an effect at the time of the third stop using the liquid crystal display device 5, the LED 101, the lamp, the speakers 21L, 21R, etc. based on the third stop effect data. Next, the image control microcomputer 72 adds “1” to the stop reel number counter (step S277), and ends the reel stop process.

  When finishing the reel stop process, the image control microcomputer 72 returns to the command input process of FIG. 27 through the command corresponding execution process of FIG. 28, sets the unprocessed command as processed (step S213), and FIG. The process proceeds to step S204.

  Next, display processing by the image control microcomputer 72 will be described with reference to FIG. FIG. 34 is a diagram showing a flowchart of display processing by the image control microcomputer 72 of this embodiment. The display process is a process that is executed when a display combination command is received.

  First, the image control microcomputer 72 extracts the display combination command stored in the work RAM 74 as an unprocessed command, and sets the display combination identifier included in the display combination command in the work RAM 74 (step S281).

  Next, the image control microcomputer 72 refers to the effect data determination table (see FIG. 12 (2)), and sets display effect data based on the effect identifier (step S282). For example, when the effect identifier is “A1”, the image control microcomputer 72 determines “A1-5” as the display effect data. Based on the display effect data, the gaming machine 1 uses the liquid crystal display device 5, the LED 101, the lamp, the speakers 21 </ b> L, 21 </ b> R, etc. to perform an effect at the time of symbol stop display on the reel 3.

  Next, the image control microcomputer 72 sets “0” in the in-game identifier (step S283). When this process ends, the image control microcomputer 72 ends the display process, returns to the command input process of FIG. 27 via the command corresponding execution process of FIG. 28, and sets the unprocessed command as processed (step S213). ), The process proceeds to step S204 in FIG.

  As described above, the gaming machine 1 is based on the number of times that losing is determined as an internal winning combination during the FT gaming state even if the player's game becomes monotonous because the gaming state is the FT gaming state. Since the two-dimensional codes 211 and 212 generated by encoding information advantageous to the player are displayed, the interest of the player can be improved.

  Further, the player can acquire information advantageous to himself / herself by photographing and decoding the two-dimensional code with the mobile phone 300 with a camera function, and can improve the interest in the game.

  Furthermore, since the gaming machine 1 displays the number of times that the loss is determined as an internal winning combination when the gaming state is the FT gaming state in the number display area 210, the gaming machine 1 visually notifies the player of the number of times. And the interest of the player can be improved.

  In the present embodiment, the number of times that the losing has been determined as the internal winning combination is displayed in the number of times display area 210, but this is not limiting, and the number of times that the losing has been stopped may be displayed. In this case, the same effect as the gaming machine described above is obtained.

  Further, in this embodiment, the pachislot gaming machine is exemplified, but the present invention is not limited to this, and the present invention can be applied to other gaming machines.

  Furthermore, the game can be executed by applying the present invention to a game program in which the operation of the gaming machine 1 is executed in a pseudo manner for a home game machine. In this case, the same effect as the gaming machine 1 described above can be obtained.

It is a perspective view which shows the game machine in one Embodiment which concerns on this invention. It is a figure which shows the example after acquiring a predetermined | prescribed image or a moving image, after image | photographing a two-dimensional code with the mobile telephone in one Embodiment. It is a figure which shows the example of the arrangement | positioning table of the symbol on the reel of the game machine in one Embodiment. It is a figure which shows the structure of the internal circuit of the game machine in one Embodiment. It is a figure which shows the structure of the sub control circuit of the game machine in one Embodiment. It is a figure which shows the example of the symbol combination table of the game machine of one Embodiment. It is a figure which shows the example of the lottery frequency determination table of the game machine of one Embodiment. It is a figure which shows the example of the internal lottery table of the game machine of one Embodiment. It is a figure which shows the example of the internal winning combination determination table of the gaming machine of one embodiment. It is a figure which shows the example of the table at the time of the bonus action | operation of the gaming machine of one Embodiment. It is a figure which shows the example of the bonus check data of the gaming machine of one Embodiment, an internal winning combination storing area, a carryover combination storing area, and a winning number storing area. It is a figure which shows the example of the effect identifier determination table and effect data determination table of the game machine of one Embodiment. It is a figure which shows the example of the URL information setting table of the game machine of one Embodiment. It is a figure which shows the flowchart of the reset interruption process by the main CPU performed by the main control circuit of one Embodiment. It is a figure which shows the flowchart of the bonus operation | movement monitoring process performed with the main control circuit of one Embodiment. It is a figure which shows the flowchart of the internal lottery process performed with the main control circuit of one Embodiment. It is a figure which shows the flowchart of the FT control process performed with the main control circuit of one Embodiment. It is a figure which shows the flowchart of the reel stop control process performed with the main control circuit of one Embodiment. It is a figure which shows the flowchart of the bonus completion | finish check process performed in the main control circuit of one Embodiment. It is a figure which shows the flowchart of the bonus operation | movement check process performed with the main control circuit of one Embodiment. It is a figure which shows the flowchart of the interruption process by control of the main CPU performed by the main control circuit of one Embodiment. It is a figure which shows the flowchart of the reel control process performed with the main control circuit of one Embodiment. It is a figure which shows the flowchart of the reset interruption process by the image control microcomputer performed by the sub control circuit of one Embodiment. It is a figure which shows the flowchart of the regular signal reception process from the image control IC performed with the sub control circuit of one Embodiment. It is a figure which shows the flowchart of the command signal reception interruption process performed with the sub control circuit of one Embodiment. It is a figure which shows the flowchart of the regular interruption process performed with the sub control circuit of one Embodiment. It is a figure which shows the flowchart of the command input process performed with the sub-control circuit of one Embodiment. It is a figure which shows the flowchart of the command corresponding | compatible execution process performed with the sub control circuit of one Embodiment. It is a figure which shows the flowchart of the medal insertion process performed with the sub control circuit of one Embodiment. It is a figure which shows the flowchart of the game start process performed with the sub-control circuit of one Embodiment. It is a figure which shows the flowchart of the FT count process performed with the sub control circuit of one Embodiment. It is a figure which shows the flowchart of the encoding process performed with the sub control circuit of one Embodiment. It is a figure which shows the flowchart of the reel stop process performed with the sub control circuit of one Embodiment. It is a figure which shows the flowchart of the display process performed in the sub control circuit of one Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Game machine 3L, 3C, 3R ... Reel 4L, 4C, 4R ... Symbol display window 6S ... Start switch 7LS, 7CS, 7CR ... Stop switch 21L, 21R ... Speaker 101 ... Lamp 102 ... LED
30 ... Microcomputer 31 ... Main CPU
32 ... ROM
33 ... RAM
49L, 49C, 49R ... Stepping motor 60 ... Main control circuit 61 ... Sub control circuit 200 ... Two-dimensional code display area 210 ... Number display area 300 ... Mobile phone

Claims (3)

Variable display means having a plurality of variable display parts for variably displaying a plurality of symbols;
Stop operation means used when stopping the variable display of the variable display section;
A winning combination determination means for determining an internal winning combination by lottery from a predetermined group including a loser;
Stop control means for stopping the variable display of each variable display unit based on the operation timing for the stop operation means and the internal winning combination determined by the winning combination determining means;
The winning combination determining means when the gaming state is a special gaming state in which the lottery is performed according to a condition that a combination that can be replayed without a new gaming value being input compared to the normal gaming state is won with high probability. Is a counting means for counting the number of times the lose is determined as an internal winning combination,
Privilege granting means for granting a privilege based on the number of times counted by the counting means;
A gaming machine comprising: In the gaming machine according to claim 1,
The privilege granting means
Code generating means for generating a two-dimensional code by encoding information advantageous to the player;
Code display means for displaying the two-dimensional code generated by the code generation means;
A gaming machine characterized by including: In the gaming machine according to claim 1 or 2,
A gaming machine comprising a number display means for displaying the number of times counted by the counting means.

Images