JP2007165355A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device wherein reliability can be improved and microfabrication can be ensured by suppressing an influence of a plasma charging. <P>SOLUTION: The semiconductor device is provided with a first conductivity type semiconductor layer 10, a first area 10A and a second area 10B which are specified by an isolation insulating layer 20 provided in the semiconductor layer 10, a gate insulating layer 32 provided in the second area 10B, a consecutive gate electrode 34 which is provided above the first and second areas 10A and 10B, and an impurity area 36 which is provided in the second area 10B to pinch the gate electrode 34. At least the gate electrode 34 located above the first area 10A is a second conductivity type semiconductor. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device.

In a manufacturing process of a semiconductor device for forming a MOS transistor, a multilayer wiring layer, and the like, processing using plasma is performed in various film forming processes and patterning processes. This plasma treatment may cause a phenomenon in which electric charges due to plasma are charged in the surrounding insulating layers such as the gate electrode, the wiring layer, and the plug of the MOS transistor. When the negative charge due to plasma is charged to the insulating layer around the wiring layer and the plug (hereinafter referred to as “plasma charge”), a potential difference corresponding to the amount of charge charged to the gate electrode connected thereto is applied. It will be done. This overuses the gate insulating layer and may cause deterioration of the insulating properties of the gate insulating layer. In addition, the charged charge may accumulate on the channel portion and affect the characteristics of the MOS transistor, such as fluctuation in threshold value. In order to suppress the deterioration of the reliability of the MOS transistor due to such plasma charging, a technique described in Japanese Patent Application Laid-Open No. 2004-363254 is disclosed. In Japanese Patent Application Laid-Open No. 2004-363254, a dummy contact and wiring are used to connect a diode to a MOS transistor to release plasma charge.
JP 2004-363254 A

  However, in the technique described in Japanese Patent Application Laid-Open No. 2004-363254, the dummy contact and the wiring are portions that do not function after the device is manufactured. Therefore, it becomes a semiconductor device with poor area efficiency.

  An object of the present invention is to provide a semiconductor device that is improved in reliability and miniaturized by suppressing the influence of plasma charging.

(1) A semiconductor device according to the present invention includes:
A first conductivity type semiconductor layer;
A first region and a second region specified by an isolation insulating layer provided in the semiconductor layer;
A gate insulating layer provided in the second region;
A continuous gate electrode provided above the first region and the second region;
An impurity region sandwiching the gate electrode provided in the second region,
The gate electrode located at least above the first region is a second conductivity type semiconductor portion.

  According to the present invention, a diode composed of a first conductivity type semiconductor layer and a second conductivity type semiconductor portion is provided in the first region, and a MIS transistor is provided in the second region. The diode and the MIS transistor are electrically connected by using a common gate electrode. Therefore, the charge charged by the plasma process can be released to the grounded semiconductor layer (substrate) through the diode. As a result, a potential difference is generated in the gate electrode, deterioration of the film quality of the gate insulating layer, dielectric breakdown, and the like are suppressed, and a highly reliable semiconductor device can be provided.

  In the present invention, when a specific B layer (hereinafter referred to as “B layer”) provided above a specific A layer (hereinafter referred to as “A layer”) is referred to as “B” directly on the A layer. This includes the case where the layer is provided and the case where the B layer is provided on the A layer via another layer.

  Further, the semiconductor device according to the present invention can further take the following aspects.

(2) In the semiconductor device according to the present invention,
The gate electrode may be a polycrystalline silicon layer doped with impurities.

(3) In the semiconductor device according to the present invention,
The first region and the second region may be included in a second conductivity type well provided in the semiconductor layer.

(4) In the semiconductor device according to the present invention,
The polycrystalline silicon layer located in the first region is of a second conductivity type;
The polycrystalline silicon layer located in the second region may be of a first conductivity type.

(5) In the semiconductor device according to the present invention,
A silicide layer may be provided on the polycrystalline silicon layer.

  According to this aspect, even when a polycrystalline silicon layer having different conductivity types is formed in the first region and the second region, electrical connection can be reliably achieved.

(6) A semiconductor device according to the present invention includes:
A MIS, a transistor, and a diode connected to the MIS transistor;
The MIS transistor is
A gate insulating layer provided in the semiconductor layer;
A gate electrode provided above the gate insulating layer;
A source region and a drain region provided in the semiconductor layer,
The diode is
A first semiconductor portion of a first conductivity type that is part of the semiconductor layer;
A second conductive type second semiconductor part provided on the semiconductor layer, wherein the second semiconductor part may be a layer continuous with the gate electrode.

  The semiconductor device according to the present invention includes a MIS transistor to which a diode is connected. The MIS transistor and the diode are electrically connected in a layer continuous with the gate electrode of the MIS transistor. For this reason, it is possible to release electric charges due to plasma charge through the diode. As a result, deterioration of the gate insulating layer due to plasma charge can be suppressed, and a highly reliable semiconductor device can be provided.

(7) A semiconductor device according to the present invention includes:
A plurality of elements including a MIS transistor and a diode connected to the MIS transistor are arranged,
The element is
A first region and a second region specified by an isolation insulating layer provided in the semiconductor layer;
A diode comprising a first conductivity type semiconductor part that is provided in the first region and is part of the semiconductor layer; and a second conductivity type semiconductor part provided on the semiconductor layer;
A MIS transistor provided in the second region and having a gate electrode made of a layer continuous with the second conductivity type semiconductor part,
A P-type impurity region provided between the adjacent first regions between the plurality of the elements;
A plug provided above the P-type impurity region;
A wiring layer provided above the plurality of plugs,
The wiring layer may be a continuous layer.

  According to the semiconductor device of the present invention, a plurality of MIS transistors connected with diodes are arranged. A P-type impurity region is provided between the diodes, and a wiring layer connected to the ground potential is connected between the P-type impurity regions. Therefore, it is possible to further increase the number of paths for releasing the charge due to the plasma charge. As a result, a semiconductor device with improved reliability can be provided. In the stage where the semiconductor device is used, the wiring layer can be used as wiring for fixing the potential of the well. For this reason, it is not necessary to separately provide wiring for fixing the potential of the well. As a result, a miniaturized semiconductor device can be provided.

(8) A semiconductor device according to the present invention includes:
A semiconductor layer;
A first region, a second region, and a third region provided in the semiconductor layer;
A diode provided in the first region;
A first MIS transistor of a first conductivity type channel provided in the second region;
A second MIS transistor of a second conductivity type channel provided in the third region,
The diode is
A first conductivity type semiconductor part which is a part of the semiconductor layer;
A second conductive semiconductor portion provided on the semiconductor layer, wherein the first gate electrode of the first MIS transistor, the second gate electrode of the second MIS transistor, and the second conductive semiconductor portion are continuous. It is a layer to do.

  The semiconductor device according to the present invention includes a CMOS transistor to which a diode is connected. For this reason, the charge due to the plasma charge can be released through the diode. As a result, it is possible to provide a semiconductor device in which deterioration of the gate insulating layer, threshold value fluctuation, and the like are suppressed and reliability is improved.

  The semiconductor device according to the present invention can further take the following aspects.

(9) In the semiconductor device according to the present invention,
The first gate electrode, the second gate electrode, and the second conductivity type semiconductor part may be a polycrystalline silicon layer into which impurities are introduced.

(10) In the semiconductor device according to the present invention,
In the first gate electrode, the second gate electrode, and the second conductivity type semiconductor part, impurities of different conductivity types are introduced,
A silicide layer may be provided above the first gate electrode, the second gate electrode, and the second semiconductor part.

  Hereinafter, an example of an embodiment of the present invention will be described with reference to the drawings.

1. 1. First embodiment 1.1. Semiconductor Device A semiconductor device according to the first embodiment will be described with reference to FIG. FIG. 1A is a plan view schematically showing the semiconductor device according to the present embodiment. FIG. 1B is a cross-sectional view taken along line I-I in FIG. FIG. 1C is a cross-sectional view taken along the line II-II in FIG.

  As shown in FIG. 1, the semiconductor device 100 according to the first embodiment first has a first conductivity type (P type) semiconductor layer 10. In the present embodiment, a case of a P-type semiconductor substrate will be described as an example. In the semiconductor device according to the present embodiment, the P-type well 12 is provided, but the P-type well 12 is not necessarily provided. An isolation insulating layer 20 is provided in the semiconductor layer 10. The isolation region 20 separates the first region 10A and the second region 10B. An N-channel MIS transistor 30 is provided in the second region 10B. A diode 40 is provided in the first region 10A.

  As shown in FIG. 1B, the N-channel MIS transistor 30 includes a gate insulating layer 32, a gate electrode 34, and an impurity region 36 provided above the second region 10B. The gate insulating layer 32 is provided above the channel region. The gate electrode 34 is provided on the gate insulating layer 32. As gate electrode 34, for example, an N-type polycrystalline silicon layer can be used. The impurity region 36 becomes a source region or a drain region. The impurity region 36 is an N-type impurity region. In the semiconductor device according to the present embodiment, the sidewall insulating layer, the LDD region, and the like are not shown, but it goes without saying that these may be provided.

  As shown in FIG. 1C, the diode 40 includes a P-type semiconductor layer 10 and an N-type semiconductor portion. The N-type semiconductor portion is one conductive layer continuous with the gate electrode 34. That is, the gate electrode 34 is provided continuously in the first region 10A and the second region 10B. In this embodiment, the gate electrode 34 is made of a polycrystalline silicon layer into which an N-type impurity is introduced. Further, in the semiconductor device according to the present embodiment, the case where the N-type impurity region 42 is provided in the first region 10A with the gate electrode 34 interposed therebetween is shown. The N-type impurity region 42 is not necessarily required as long as the diode 40 is formed by the junction of the P-type well 12 and the gate electrode 34 made of the N-type polycrystalline silicon layer.

  According to the semiconductor device according to the present embodiment, the first region 10A is provided with the diode 40 including the P-type semiconductor layer 10 and the N-type polycrystalline silicon layer 34 (a part of the gate electrode 34). A MIS transistor 30 is provided in the second region 10B. The diode 40 and the MIS transistor 30 are electrically connected by making the gate electrode 34 common. Therefore, the electric charge charged by the plasma process can be released to the P-type semiconductor layer 10 that is grounded via the diode 40. As a result, a potential difference is generated in the gate electrode 34 and deterioration of the film quality or dielectric breakdown of the gate insulating layer 32 is suppressed, so that a highly reliable semiconductor device can be provided.

1.2. Semiconductor Device Manufacturing Method Next, a semiconductor device manufacturing method according to the present embodiment will be described with reference to FIGS. 2 to 4 are diagrams schematically showing a manufacturing process of the semiconductor device according to the present embodiment, and (A), (B), and (C) in each figure are shown in FIG. It is a figure corresponding to 1 (B) and FIG.1 (C).

  (1) First, as shown in FIGS. 2B and 2C, a P-type well 12 is formed in the semiconductor layer 10. In forming the well 12, a mask layer (not shown) having a predetermined pattern is formed and a P-type impurity is introduced. The mask layer has an opening in a region where the well 12 is to be formed. The introduction of the P-type impurity can be performed by, for example, an ion implantation method. If necessary, heat treatment for diffusing impurities may be performed.

  Next, the isolation insulating layer 20 is formed. The isolation insulating layer 20 can be formed by a LOCOS (Local Oxidation of Silicon) method, a semi-recessed LOCOS method, or an STI (Shallow Trench Isolation) method. Through the above steps, the first region 10A and the second region 10B are formed as shown in FIG. Note that the order in which the well 12 and the isolation insulating layer 20 are formed is not particularly limited, and may be the reverse order of the above-described manufacturing method.

  (2) Next, as shown in FIG. 3, an insulating layer 32a to be the gate insulating layer 32 is formed. A silicon oxide layer can be formed as the insulating layer 32a. The insulating layer 32a can be formed by, for example, a thermal oxidation method. Next, as shown in FIG. 3, the insulating layer 32a in the first region 10A is removed. By removing the insulating layer 32a in this way, a diode composed of the P-type well 12 and the N-type polycrystalline silicon layer can be formed. In this step, after forming a mask layer (not shown) having an opening above the first region 10A, for example, wet etching using dilute hydrofluoric acid or the like can be performed. Thereby, the insulating layer 32a is removed from at least a region where a gate electrode (described later) is formed in the first region 10A.

  (3) Next, a conductive layer (not shown) to be the gate electrode 34 is formed. A polycrystalline silicon layer can be used as the conductive layer. Thereafter, by patterning the conductive layer, the gate electrode 34 made of a continuous polycrystalline silicon layer can be formed on the first region 10A and the second region 10B. A gate electrode 34 is formed in the second region 10B. In the step of forming the gate electrode 34, the insulating layer 32a provided under the conductive layer to be removed is also removed. In this way, the gate insulating layer 32 is also patterned.

  (4) Next, as shown in FIG. 1, an impurity region 36 is formed. In the formation of the impurity region 36, a mask layer M1 having an opening in a predetermined region is formed. The opening region 120 in the mask layer M1 is indicated by a dotted line in FIG. The mask layer M1 has an opening above the impurity region 36 and the gate electrode 34 in the second region 10B, and at least above the gate electrode 34 in the first region 10A. FIG. 4A illustrates a mask layer M1 that includes the above-described region and has one continuous opening. Thereafter, N-type impurities are introduced into the semiconductor layer by, for example, ion implantation. At this time, N-type impurities are simultaneously introduced into the polycrystalline silicon layer. Therefore, the diode 40 composed of N-type polycrystalline silicon and a P-type well is formed in the second region 10B.

2. Second Embodiment 2.1. Semiconductor Device A semiconductor device according to the second embodiment will be described with reference to FIG. FIG. 5A is a plan view schematically showing the semiconductor device according to the present embodiment. FIG. 5B is a cross-sectional view taken along the line I-I in FIG. FIG. 5C is a cross-sectional view taken along line II-II in FIG.

  The semiconductor device 110 according to the second embodiment includes a P-channel MIS transistor 50 and a diode 60 provided in a P-type semiconductor layer. Note that detailed descriptions of configurations and members common to those of the semiconductor device according to the first embodiment are omitted.

  As shown in FIGS. 5B and 5C, in the semiconductor device according to the second embodiment, an N-type well 14 is provided in a P-type semiconductor layer 10. The first region 10 </ b> A and the second region 10 </ b> B are defined by the isolation insulating layer 20 provided in the semiconductor layer 10.

  As shown in FIG. 5B, a P-channel MIS transistor 50 is provided in the second region 10B. P channel MIS transistor 50 includes a gate insulating layer 52, a gate electrode 54, and an impurity region 56. The configuration of each member is the same as that of the N-channel type MIS transistor described in the first embodiment.

  As shown in FIG. 5C, a diode 60 is provided in the first region 10A. The diode 60 includes a P-type semiconductor layer 10 and an N-type semiconductor unit 62. The N-type semiconductor unit 62 includes an N-type well 14 and an N-type semiconductor layer 64. As the N-type semiconductor layer 64, a polycrystalline silicon layer can be used, which is one layer continuous with the gate electrode 54. The gate electrode 54 is continuously provided in the first region 10A and the second region 10B. That is, a continuous polysilicon layer is provided in the first region 10A and the second region 10B, and impurities of different conductivity types are introduced into the first region 10A and the second region 10B. A silicide layer 66 is formed on the gate electrode 54 and the N-type semiconductor layer 64. The gate electrode 54 and the N-type semiconductor layer 64 are electrically connected by the silicide layer 66. In the present embodiment, a case where an N-type impurity region 61 is provided in the first region 10A at a position sandwiching the N-type semiconductor layer 64 is illustrated. N-type impurity region 61 is a region including a polycrystalline silicon layer in consideration of mask misalignment in the step of introducing N-type impurities into the polycrystalline silicon layer (part of the step of forming N-type semiconductor layer 64). This is a region formed when a mask layer having an opening is formed, and is not necessarily required.

  In the semiconductor device according to the present embodiment, the MIS transistor 50 and the diode 60 are connected. Therefore, it is possible to provide a highly reliable semiconductor device having the same advantages as those of the first embodiment.

2.2. Semiconductor Device Manufacturing Method Next, a semiconductor device manufacturing method according to the second embodiment will be described with reference to FIGS. 6 or 7 is a cross-sectional view schematically showing the manufacturing process of the semiconductor device according to this embodiment. 6 and 7, (A), (B), and (C) correspond to FIGS. 5 (A), 5 (B), and 5 (C). In the following description, description and illustration of steps common to the first embodiment are omitted.

  (1) First, steps (1) to (3) according to the first embodiment are performed to form a patterned polycrystalline silicon layer 64. Next, as shown in FIG. 6, an impurity region 56 is formed. In this step, a mask layer M1 that covers at least the first region 10A and has an opening above at least the second region 10B is formed. Note that a region surrounded by a dotted line illustrated in FIG. 6A indicates the opening region 120 of the mask layer M1. As mask layer M1, for example, a resist layer can be used. Next, a P-type impurity is introduced by, for example, an ion implantation method. You may heat-process as needed.

  (2) Next, as shown in FIG. 7, a mask layer M2 having an opening above at least the first region 10A and covering the second region is formed. A region surrounded by a dotted line in FIG. 7A indicates the opening region 122 of the mask layer M2. Next, an N-type impurity is introduced into the semiconductor layer 10. By this step, the N-type semiconductor layer 64 that is a part of the N-type semiconductor portion 62 of the diode 60 can be formed in the first region 10A.

  (3) Next, a silicide layer is formed on the conductive layer. Since the conductive layer has a different conductivity type between the first region 10A and the second region 10B, electrical connection can be achieved by forming a silicide layer. In forming the silicide layer, first, a silicide metal is formed on the entire surface. Thereafter, a heat treatment for causing a silicidation reaction is performed. Subsequently, the silicide layer 66 can be formed by removing the unreacted metal. Through the above steps, the semiconductor device according to the second embodiment can be manufactured.

3. Third embodiment 3.1. Semiconductor Device Next, a semiconductor device according to a third embodiment will be described with reference to FIG. FIG. 8A is a plan view showing the semiconductor device according to this embodiment. FIG. 8B is a cross-sectional view taken along the line II of FIG. Note that the semiconductor device according to this embodiment is a diagram illustrating a case where a plurality of semiconductor devices described in the first embodiment are provided. A detailed description of the configuration and members common to the description of the first embodiment will be omitted.

  As shown in FIG. 8, in the semiconductor device according to the present embodiment, a plurality of MIS transistors 30 described in the first embodiment and a plurality of elements 110 including diodes connected to the MIS transistors 30 are arranged. The MIS transistors 30 are arranged so that the width directions of the gate electrodes 34 are parallel so that the impurity regions 36 are adjacent to each other. Each MIS transistor 30 is provided with a diode 40 electrically connected by a gate electrode 34.

  As shown in FIGS. 8A and 8B, a P-type impurity region 68 is provided between the diodes 40. That is, in the first region 10A, the P-type impurity region 68 is provided in the semiconductor layer 10 located between the adjacent conductive layers.

  An interlayer insulating layer 112 is provided above the MIS transistor 30 and the diode 40 as shown in FIG. As the interlayer insulating layer 112, a silicon oxide film, a silicon nitride film, a PSG film, a BSG film, a BPSG film, a TEOS film, an ozone-TEOS film, a USG film, or a stacked film thereof can be used. A wiring layer 114 is provided on the interlayer insulating layer 112. Needless to say, another wiring layer connected to the gate electrode at the same level of the wiring layer 114 (on the interlayer insulating layer) is provided. As the wiring layer 114, for example, an aluminum alloy layer can be used. A plug 116 is provided in the interlayer insulating layer 112. The plug 116 electrically connects the wiring layer 114 and the P-type impurity region 68 between the diodes. The wiring layer 114 is connected to the ground line.

  In the semiconductor device according to the third embodiment, the P-type impurity region 68 is provided in the region between the plurality of diodes 40, and the P-type impurity region 68 is connected to the ground layer 114. Connected with. Therefore, charges can be released to the wiring layer 114 via the diode 40. Thereby, in addition to the path for escaping to the P-type semiconductor layer 10 side, the path for escaping charges can be increased. The wiring layer 114 can also serve as a wiring for fixing the potential of the P-type well 12. Therefore, it is not necessary to newly form a wiring for fixing the well potential, and a semiconductor device in which miniaturization is realized can be provided.

  Note that the manufacturing method of the semiconductor device according to the third embodiment can be the same as the manufacturing method of the semiconductor device according to the first embodiment.

4). Fourth Embodiment Next, a fourth embodiment will be described with reference to FIG. FIG. 9A is a plan view for explaining a semiconductor device according to the fourth embodiment. FIG. 9B is a cross-sectional view taken along the line II of FIG. The semiconductor device according to the fourth embodiment is a case where a plurality of MIS transistors 50 disclosed in the second embodiment are arranged. The position of the arrangement of the MIS and the transistor 50 is the same as that of the semiconductor device according to the third embodiment.

  As shown in FIG. 9, a P-type impurity region 68 is provided between adjacent diodes 60. The P-type impurity region 68 is connected to the wiring layer 114 formed thereabove. The diode 60 is formed by joining the P-type impurity region 68 and the N-type well 14 together. The wiring layer 114 is connected to the ground line.

  The manufacturing method of the semiconductor device according to the fourth embodiment can be performed in the same manner as the method described in the second embodiment, although the pattern of the mask layer when implanting various impurities is different. .

  According to the semiconductor device of the fourth embodiment, when the wiring layer 114 is connected to the ground line, the charge caused by the plasma is passed through the diode 60 composed of the N-type well 14 and the P-type impurity region 68. Can escape. Thereby, in addition to the diode 60, the path | route which releases an electric charge can be increased. Therefore, the deterioration of the gate insulating layer 52 of the MIS transistor 50 can be further suppressed. As a result, a highly reliable semiconductor device can be provided.

5. Fifth Embodiment Next, a semiconductor device according to a fifth embodiment will be described with reference to FIG. FIG. 10 is a plan view schematically showing the fifth semiconductor device. The semiconductor device according to the fifth embodiment is a CMOS transistor to which a diode for releasing charges due to the influence of plasma is connected.

  In the semiconductor device according to the present embodiment, as shown in FIG. 10, the first region 10A, the second region 10B, and the third region 10C are specified. A P-channel transistor 70 is provided in the first region 10A, an N-channel transistor 80 is provided in the second region 10B, and a diode 90 is provided in the third region 10C. The P-channel transistor 70 and the N-channel transistor 80 are electrically connected to form a CMOS transistor 130. In the semiconductor device according to the present embodiment, a plurality of CMOS transistors 130 are arranged. The CMOS transistor 130 is arranged so that the width direction of the gate electrode is parallel. CMOS transistor 130 includes a P-channel transistor 70 and an N-channel transistor 80.

  P-channel transistor 70 includes at least a gate insulating layer, a gate electrode, and an impurity region serving as a source region or a drain region. Similarly, the N-channel transistor 80 includes at least a gate insulating layer, a gate electrode, and an impurity region serving as a source region or a drain region. Note that FIG. 1B and FIG. 5B are referred to for each cross-sectional structure. FIG. 10 shows the positional relationship between the polycrystalline silicon layer 72 serving as the respective gate electrodes and the impurity regions 76 and 86 serving as the source region or the drain region.

  As shown in FIG. 10, in the semiconductor device according to the present embodiment, the gate electrodes of the P-channel transistor 70 and the N-channel transistor 80 have the same continuous polysilicon layer 72.

  A diode 90 is connected to the CMOS transistor 130. The diode 90 can have the same structure as the diode 40 described in the first embodiment. The diode 90 includes an N-type semiconductor portion and a P-type semiconductor portion. An example in which the N-type semiconductor portion is an N-type polycrystalline silicon layer 72 and the P-type semiconductor portion is a P-type well (P-type semiconductor layer) is illustrated. A silicide layer is formed on the polycrystalline silicon layer 72. Thereby, the P-channel transistor 70 and the N-channel transistor 80 and the diode 90 are electrically connected.

  The semiconductor device according to the fifth embodiment can be manufactured by combining the manufacturing steps of the semiconductor device according to the above-described embodiment. First, a P-type semiconductor layer 10 is prepared, and a well 12 and a well 14 are formed. Next, by forming the isolation insulating layer 20, the first region 10A and the second region 10B are defined. An insulating layer to be a gate insulating layer is formed on the semiconductor layer 10. Thereafter, only the insulating layer in the second region 10B is removed. Thereafter, a conductive layer is formed on the entire surface of the semiconductor layer 10, and the conductive layer is patterned to form a gate electrode. A polycrystalline silicon layer is used as the conductive layer. Thereafter, impurity regions are formed and impurities are introduced into the polycrystalline silicon layer. Next, by forming a silicide layer, the semiconductor device according to this embodiment can be manufactured.

  The semiconductor device according to the present embodiment has the CMOS transistor 130 to which the diode 90 is connected. Therefore, a semiconductor device having advantages similar to those of the above embodiment and improved reliability can be provided.

  In addition, this invention is not limited to embodiment mentioned above, A various deformation | transformation is possible. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same purposes and results). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

1A and 1B illustrate a semiconductor device according to a first embodiment. FIG. 6 is a diagram for explaining a manufacturing process for the semiconductor device according to the first embodiment; FIG. 6 is a diagram for explaining a manufacturing process for the semiconductor device according to the first embodiment; FIG. 6 is a diagram for explaining a manufacturing process for the semiconductor device according to the first embodiment; 6A and 6B illustrate a semiconductor device according to a second embodiment. 8A and 8B illustrate a manufacturing process of a semiconductor device according to a second embodiment. 8A and 8B illustrate a manufacturing process of a semiconductor device according to a second embodiment. FIG. 6 is a diagram illustrating a semiconductor device according to a third embodiment. FIG. 10 is a diagram illustrating a semiconductor device according to a fourth embodiment. FIG. 10 is a diagram illustrating a semiconductor device according to a fifth embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Semiconductor layer, 10A ... 1st area | region, 10B ... 2nd area | region, 10C ... 3rd area | region, 12 ... P-type well, 14 ... N-type well, 20 ... Isolation insulation layer, 30 ... MIS transistor, 32 ... Gate insulation Layer 32a ... insulating layer 34 ... gate electrode 36 ... impurity region 40 ... diode 42 ... N-type impurity region 50 ... MIS transistor 52 ... gate insulating layer 54 ... gate electrode 56 ... impurity region 60 DESCRIPTION OF SYMBOLS 61 ... N-type impurity region 62 ... N-type semiconductor part 64 ... N-type semiconductor layer 66 ... Silicide layer 68 ... P-type impurity region 70 ... MIS transistor 72 ... Polycrystalline silicon layer 76 ... Impurity region, 80 ... MIS transistor, 86 ... impurity region, 90 ... diode, 100, 110 ... semiconductor device, 30 ... CMOS transistor ,, 110 ... device, 112 ... interlayer insulating layer, 114 ... wiring layer, 116 ... Plug, M1 ... mask layer, M2 ... mask layer

Claims (10)

A first conductivity type semiconductor layer;
A first region and a second region specified by an isolation insulating layer provided in the semiconductor layer;
A gate insulating layer provided in the second region;
A continuous gate electrode provided above the first region and the second region;
An impurity region sandwiching the gate electrode provided in the second region,
The semiconductor device, wherein at least the gate electrode located above the first region is a second conductivity type semiconductor portion. In claim 1,
The semiconductor device, wherein the gate electrode is a polycrystalline silicon layer into which impurities are introduced. In claim 1 or 2,
The semiconductor device, wherein the first region and the second region are included in a second conductivity type well provided in the semiconductor layer. In any of claims 1 to 3,
The polycrystalline silicon layer located in the first region is of a second conductivity type;
The semiconductor device, wherein the polycrystalline silicon layer located in the second region is of a first conductivity type. In any of claims 1 to 4,
A semiconductor device, wherein a silicide layer is provided on the polycrystalline silicon layer. A MIS, a transistor, and a diode connected to the MIS transistor;
The MIS transistor is
A gate insulating layer provided in the semiconductor layer;
A gate electrode provided above the gate insulating layer;
A source region and a drain region provided in the semiconductor layer,
The diode is
A first semiconductor portion of a first conductivity type that is part of the semiconductor layer;
A second semiconductor portion of a second conductivity type provided on the semiconductor layer, wherein the second semiconductor portion is a layer continuous with the gate electrode. A plurality of elements including a MIS transistor and a diode connected to the MIS transistor are arranged,
The element is
A first region and a second region specified by an isolation insulating layer provided in the semiconductor layer;
A diode comprising a first conductivity type semiconductor part that is provided in the first region and is part of the semiconductor layer; and a second conductivity type semiconductor part provided on the semiconductor layer;
A MIS transistor provided in the second region and having a gate electrode made of a layer continuous with the second conductivity type semiconductor part,
A P-type impurity region provided between the adjacent first regions between the plurality of the elements;
A plug provided above the P-type impurity region;
A wiring layer provided above the plurality of plugs,
The semiconductor device, wherein the wiring layer is a continuous layer. A semiconductor layer;
A first region, a second region, and a third region provided in the semiconductor layer;
A diode provided in the first region;
A first MIS transistor of a first conductivity type channel provided in the second region;
A second MIS transistor of a second conductivity type channel provided in the third region,
The diode is
A first conductivity type semiconductor part which is a part of the semiconductor layer;
A second conductive semiconductor portion provided on the semiconductor layer, wherein the first gate electrode of the first MIS transistor, the second gate electrode of the second MIS transistor, and the second conductive semiconductor portion are continuous. A semiconductor device which is a layer to be In claim 8,
The semiconductor device, wherein the first gate electrode, the second gate electrode, and the second conductivity type semiconductor portion are polycrystalline silicon layers into which impurities are introduced. In claim 8 or 9,
In the first gate electrode, the second gate electrode, and the second conductivity type semiconductor part, impurities of different conductivity types are introduced,
A semiconductor device, wherein a silicide layer is provided above the first gate electrode, the second gate electrode, and the second semiconductor portion.

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