JP2013089652A - Solid state image sensor and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce random noise.SOLUTION: The solid state image sensor comprises: a pixel array formed on a substrate where pixels, each consisting of a photoelectric conversion part (PD) and a plurality of transistors in a pixel, are arranged two-dimensionally. The electrodes of predetermined transistors in a pixel out of the plurality of transistors in a pixel, more specifically the contacts being connected only with the gate electrode of an amplification transistor, have a substantially rectangular or elliptic shape in the plane parallel with the substrate. The present technique can be applied to a CMOS image sensor.

Description

  The present technology relates to a solid-state imaging device and a manufacturing method thereof, and more particularly, to a solid-state imaging device and a manufacturing method thereof capable of reducing random noise.

  In recent years, it has become difficult to reduce random noise in a solid-state imaging device as the pixel size is reduced.

  In order to reduce random noise, as much hydrogen as possible is supplied to the amplification transistor to reduce electron traps at the gate oxide film interface.

  For example, in some semiconductor devices, hydrogen supply is promoted by providing a dummy contact on a gate in order to extend the life of hot carriers (see, for example, Patent Document 1).

  On the other hand, for the purpose of improving the incident efficiency of light without lowering the degree of freedom of wiring, photoelectric conversion that uses a shared contact that connects the diffusion layer and the gate electrode of the pixel transistor in the pixel transistor portion An apparatus has been proposed (see, for example, Patent Document 2).

  In addition, a method for manufacturing a solid-state imaging device has been proposed in which a nitride film is formed as a stopper for contact etching and the nitride film other than the contact region is removed to promote hydrogen supply (for example, Patent Documents). 3).

JP 2002-343812 A JP 2008-210870 A JP 2004-165236 A

  However, in the photoelectric conversion device of Patent Document 2, although the contact layout of the shared contact becomes large, the side wall is formed under the shared contact, so that the hydrogen supply cannot be sufficiently promoted.

  In the case of using a shared contact, a nitride film is generally used as an insulating film in a part under the contact hole. For example, as disclosed in Patent Document 3, the nitride film does not allow hydrogen to pass through. Therefore, the diffusion coefficient of hydrogen in the nitride film becomes low.

  On the other hand, according to the manufacturing method of Patent Document 3, hydrogen supply can be promoted, but it is necessary to remove the nitride film other than the contact region, which increases the number of steps.

  Thus, in the solid-state imaging device, a configuration that efficiently promotes hydrogen supply has not been known.

  This technique is made in view of such a situation, and makes it possible to reduce random noise.

  A solid-state imaging device according to a first aspect of the present technology includes a pixel array that is formed on a substrate and in which pixels including a photoelectric conversion unit and a plurality of in-pixel transistors are two-dimensionally arranged. Of the contacts connected only to the electrodes of the predetermined intra-pixel transistor, the shape of the surface parallel to the substrate is substantially rectangular or elliptical.

  The predetermined intra-pixel transistor may be an amplification transistor.

  The contact may be connected only to the gate electrode of the predetermined intra-pixel transistor.

  At least a part of the contact on the substrate side may be in contact with a sidewall formed on a sidewall of the gate electrode of the predetermined intra-pixel transistor.

  At least a part of the contact on the substrate side may be in contact with a region that electrically isolates the predetermined in-pixel transistor.

  In the shape of the surface of the contact parallel to the substrate, the longitudinal direction of the substantially rectangular or substantially elliptical shape is the same as the extending direction of the element region formed between the photoelectric conversion portions of the plurality of pixels. can do.

  Of the plurality of in-pixel transistors, a contact connected to the electrode of another in-pixel transistor has a substantially square shape in a plane parallel to the substrate, and is a contact connected only to the electrode of the predetermined in-pixel transistor. The shape of the surface parallel to the substrate is a substantially rectangular shape having a short side length equal to the length of one side of the square, or a short axis length substantially equal to the length of one side of the square. It can be elliptical.

  In addition to the contacts connected to the electrodes of the plurality of in-pixel transistors, dummy contacts that are not electrically connected can be formed.

  The dummy contact may be provided on the gate electrode of the in-pixel transistor.

  The dummy contact may be connected to a metal wiring.

  A zero or negative bias can be applied to the metal wiring.

  The shape of the surface of the dummy contact parallel to the substrate may be formed in a substantially rectangular shape or a substantially elliptical shape.

  A manufacturing method of a solid-state imaging device according to a first aspect of the present technology is a manufacturing method of a solid-state imaging device including a pixel array formed on a substrate and in which pixels including a photoelectric conversion unit and a plurality of in-pixel transistors are two-dimensionally arranged. A method of forming a shape of a surface parallel to the substrate of a contact connected to only an electrode of a predetermined intra-pixel transistor of the plurality of intra-pixel transistors in a substantially rectangular shape or an elliptical shape. Including.

  A solid-state imaging device according to a second aspect of the present technology includes a pixel array formed on a substrate, in which pixels including a photoelectric conversion unit and a plurality of in-pixel transistors are two-dimensionally arranged. In addition to the contacts connected to the electrodes, dummy contacts that are not electrically connected are formed.

  The dummy contact may be provided on the gate electrode of the in-pixel transistor.

  The dummy contact may be connected to a metal wiring.

  A zero or negative bias can be applied to the metal wiring.

  The shape of the surface of the dummy contact parallel to the substrate may be formed in a substantially rectangular shape or a substantially elliptical shape.

  A method for manufacturing a solid-state imaging device according to a second aspect of the present technology is a method for manufacturing a solid-state imaging device including a pixel array formed on a substrate and in which pixels including a photoelectric conversion unit and a plurality of in-pixel transistors are two-dimensionally arranged. A method includes forming a dummy contact that is not electrically connected, in addition to contacts that are connected to the electrodes of the plurality of in-pixel transistors.

  In the first aspect of the present technology, the shape of the surface parallel to the substrate of the contact connected to only the electrode of the predetermined intra-pixel transistor among the plurality of intra-pixel transistors is formed in a substantially rectangular shape or a substantially elliptical shape. The

  In the second aspect of the present technology, dummy contacts that are not electrically connected are formed in addition to contacts that are connected to the electrodes of the plurality of in-pixel transistors.

  According to the first and second aspects of the present technology, random noise can be reduced.

It is a top view which shows the structural example of the CMOS image sensor to which this technique is applied. It is a figure which shows the structural example of 1st Embodiment of a CMOS image sensor. It is a figure which shows the structural example of 1st Embodiment of a CMOS image sensor. It is a figure explaining the shape of a contact. It is a figure which shows the structural example of 2nd Embodiment of a CMOS image sensor. It is a figure which shows the structural example of 3rd Embodiment of a CMOS image sensor. It is a figure which shows the structural example of 4th Embodiment of a CMOS image sensor. It is a top view which shows the structural example of 5th Embodiment of a CMOS image sensor. It is a flowchart explaining the manufacturing process of a CMOS image sensor. It is a flowchart explaining the manufacturing process of a CMOS image sensor. It is a flowchart explaining the manufacturing process of a CMOS image sensor. It is a figure which shows the manufacturing process of a CMOS image sensor. It is a figure which shows the manufacturing process of a CMOS image sensor. It is a figure which shows the manufacturing process of a CMOS image sensor. It is a figure which shows the manufacturing process of a CMOS image sensor. It is a figure which shows the manufacturing process of a CMOS image sensor. It is a figure which shows the manufacturing process of a CMOS image sensor. It is a figure which shows the manufacturing process of a CMOS image sensor. It is a figure which shows the manufacturing process of a CMOS image sensor. It is a figure which shows the manufacturing process of a CMOS image sensor. It is a figure which shows the manufacturing process of a CMOS image sensor. It is a figure which shows the manufacturing process of a CMOS image sensor. It is a figure which shows the manufacturing process of a CMOS image sensor. It is a figure which shows the manufacturing process of a CMOS image sensor. It is a figure which shows the manufacturing process of a CMOS image sensor. It is a figure which shows the manufacturing process of a CMOS image sensor. It is a figure which shows the manufacturing process of a CMOS image sensor. It is a figure which shows the manufacturing process of a CMOS image sensor. It is a figure which shows the manufacturing process of a CMOS image sensor. It is a figure which shows the manufacturing process of a CMOS image sensor. It is a figure which shows the manufacturing process of a CMOS image sensor. It is a figure which shows the manufacturing process of a CMOS image sensor.

Hereinafter, embodiments of the present technology will be described with reference to the drawings. The description will be given in the following order.
1. 1. Configuration example of CMOS image sensor 1. First embodiment 2. Second embodiment 3. Third embodiment 4. Fourth embodiment Fifth embodiment Manufacturing process of CMOS image sensor

<1. Configuration example of CMOS image sensor>
FIG. 1 is a plan view illustrating a configuration example of a CMOS (Complementary Metal Oxide Semiconductor) image sensor as a solid-state imaging device to which the present technology is applied.

  The CMOS image sensor of FIG. 1 has a photoelectric conversion element (photoelectric conversion unit) that generates and accumulates photoelectric charges having a charge amount corresponding to the amount of incident light and unit pixels having a plurality of in-pixel transistors in a two-dimensional matrix. An arranged pixel array is provided.

  In the CMOS image sensor of FIG. 1, a unit pixel (hereinafter also simply referred to as a pixel) includes a PD (Photo Diode) 21, a transfer transistor 22, an FD (Floating Diffusion) 23, a reset transistor 24, an amplification transistor 25, and a selection transistor 26. And a vertical signal line 27.

  Here, the unit pixel is configured to include four transistors (hereinafter also referred to as an in-pixel transistor), ie, a transfer transistor 22, a reset transistor 24, an amplifying transistor 25, and a selection transistor 26, but includes three in-pixel transistors. Alternatively, the FD 23 and the in-pixel transistor may be shared by a plurality of PDs 21.

  The transfer transistor 22, the reset transistor 24, the amplification transistor 25, and the selection transistor 26 (intra-pixel transistor) in FIG. 1 are actually gate electrodes of the respective intra-pixel transistors made of polysilicon. The in-pixel transistor itself is shown as necessary.

  The PD 21 receives light from the subject and accumulates electric charges. When the transfer pulse (voltage) is applied to the transfer transistor 22 connected to the PD 21, the charge accumulated in the PD 21 is transferred to the FD 23 via the transfer transistor 22 and converted into a voltage.

  When a selection pulse (voltage) is applied to the selection transistor 26 connected to the vertical signal line 27, the voltage of the FD 23 becomes a signal level via the amplification transistor 25, the selection transistor 26, and the vertical signal line 27. Read out.

  Further, when a reset pulse (voltage) is applied to the reset transistor 24 while the selection pulse is still applied, the voltage of the FD 23 is reset to a predetermined voltage. Then, the reset voltage of the FD 23 is read as a reset level from the amplification transistor 25 through the vertical signal line.

  1 is provided with contacts C1 to C6 for applying a voltage to the electrodes of the in-pixel transistors. Specifically, the contact C1 is connected to the gate electrode of the transfer transistor 21, and the contact C2 is connected to the gate electrode of the reset transistor 24. The contact C3 is connected to the drain electrode of the amplification transistor 25, and the contact C4 is connected to the gate electrode of the amplification transistor 25. The contact C3 connects the drain electrode of the amplification transistor 25 and the power supply VDD. The contact C5 is connected to the gate electrode of the selection transistor 26, and the contact C6 is connected to the source electrode of the selection transistor 26. The contact C6 connects the source electrode of the selection transistor 26 and the vertical signal line 27.

  Here, in the unit pixel of FIG. 1, the cross section (surface parallel to the substrate) of the contact connected to the in-pixel transistor (transfer transistor 22, reset transistor 24, amplification transistor 25, and selection transistor 26). The shape is assumed to be substantially rectangular or elliptical. In FIG. 1, the cross-sectional shapes of the contact C3 and the contact C4 are substantially rectangular or elliptical. The cross-sectional shape of the other contacts (contacts C1, C2, C4, C5) is a square. Note that the contacts C1 to C6 are all connected only to the electrode of the in-pixel transistor, and are not connected to both the electrode and the diffusion layer (for example, the FD 23) as in the so-called shared contact.

  Thus, by forming the cross-sectional shape of the contact into a substantially rectangular shape or a substantially elliptical shape, the cross-sectional area can be increased, so that the contact resistance can be reduced.

  In the CMOS image sensor, in particular, since the amplification transistor 25 greatly affects random noise, the shape of the cross section of the contact connected to the electrode of the amplification transistor 25 is substantially rectangular or substantially elliptic as shown in FIG. By forming, hydrogen supply can be promoted and random noise can be reduced.

  Further, the salicide technique is not used for the gate electrode portion and the diffusion layer of the in-pixel transistor in order to suppress white scratches caused by metal.

  When the salicide technology is used for a normal contact, the contact resistance can be almost ignored, but when there is no silicide, the on-current is affected and the contact resistance increases. For example, at the 90 nm node, the contact resistance when there is no silicide is about 500 Ω / piece. On the other hand, in FIG. 1, for example, when the amplification transistor 25 has a gate length of 0.5 μm, a gate width of 0.3 μm, and an operating voltage of 2.7 V, the on-resistance is about 12 kΩ. Thus, the contact resistance may affect the on-resistance by about 4 to 5% with respect to the on-resistance.

  Therefore, even if salicide technology is not used, the cross-sectional area of the contact can be increased by forming the cross-sectional shape of the contact to be approximately rectangular or approximately elliptical, and the influence of contact resistance on the transistor characteristics can be reduced. It becomes possible.

  In addition, while it is necessary to allow light to sufficiently enter the PD 21, the in-pixel transistor needs to be shielded from light. However, the contact cross section is formed in a substantially rectangular shape or a substantially elliptical shape, and is provided on the channel. Thus, the light shielding of the in-pixel transistor can be enhanced.

  Furthermore, by forming the cross-sectional shape of the contact into a substantially rectangular or substantially elliptical shape, the cross-sectional area can be increased, thereby reducing defects in which the contact is not electrically connected to the gate electrode, so-called open defects. It is possible to increase the yield.

<2. First Embodiment>
[Cross Section 1]
FIG. 2 is a first diagram illustrating a configuration example of the first embodiment of the CMOS image sensor. 2 is an enlarged view of the amplifying transistor 25 portion of FIG. 1, and a lower portion of FIG. 2 is a cross-sectional view of the amplifying transistor 25 portion along the straight line L1 in the upper portion of FIG. Yes.

  As shown in the lower part of FIG. 2, in the amplification transistor 25 portion, polysilicon 53 as an electrode (gate electrode) of the amplification transistor 25 is formed on the P-type layer 51 and the N-type layer 52 constituting the substrate. Has been. A nitride film (SiN) 54 is formed on the surface of the substrate and the polysilicon 53, but only a portion where a contact is formed is opened. A sidewall oxide film (sidewall) 55 is formed on the surface of the nitride film 54 and on the sidewall of the polysilicon 53 as the gate electrode.

  In the cross-sectional view of FIG. 2, the contacts (contacts C3 and C4) are constituted by a barrier metal film 56 and tungsten (W) 57, and a wiring 58 made of Cu or Al is provided on the upper side thereof.

[Cross sectional view 2]
FIG. 3 is a second diagram illustrating a configuration example of the first embodiment of the CMOS image sensor. 3 shows an enlarged view of the amplifying transistor 25 portion of FIG. 1, and the lower portion of FIG. 3 shows the amplifying transistor 25 portion (specifically, the contact in the straight line L2 in the upper portion of FIG. A cross-sectional view of C3) is shown.

  In the lower cross-sectional view of FIG. 3, the same components as those in the lower cross-sectional view of FIG. 2 are denoted by the same names and the same reference numerals, and description thereof will be omitted as appropriate.

  The oxide film isolation region 61 electrically isolates the in-pixel transistor.

[Shape of surface parallel to contact substrate]
Here, with reference to FIG. 4, the details of the shape of the plane parallel to the substrate of the contacts C3 and C4 described with reference to FIGS.

  As described above, the shapes of the contacts C3 and C4 in the plane parallel to the substrate are substantially rectangular with four vertices rounded as shown in FIG. 4A, or as shown in FIG. 4B. It is formed in a substantially oval shape. Here, the ratio of the length of the long side of the rectangle to the length of the short side, and the ratio of the length of the elliptical long axis to the length of the short axis (hereinafter also simply referred to as aspect ratio) are other than 1: 1. Any ratio of Note that the layout pattern of the contact holes formed on the substrate is actually a rectangle having four vertices.

  Further, when the shape of the surface parallel to the contact substrate other than the contacts C3 and C4 is a square, the shape of the surface parallel to the contact substrate of the contacts C3 and C4 is set to have a short side length of square. A rectangle equal to the length of one side or an ellipse whose minor axis length is equal to the length of one side of a square may be used.

  Thereby, when forming the contacts C3 and C4, even if the conditions for depositing the tungsten 57 are the same as those of the other contacts, the tungsten is easily embedded, and an increase in the number of manufacturing steps can be avoided.

<3. Second Embodiment>
FIG. 5 is a diagram illustrating a configuration example of the CMOS image sensor according to the second embodiment. 5 is an enlarged view of the amplifying transistor 25 portion of FIG. 1, and a lower portion of FIG. 5 is a cross-sectional view of the amplifying transistor 25 portion along the straight line L3 in the upper portion of FIG. Yes.

  In the cross-sectional view in the lower part of FIG. 5, the same components as those in the cross-sectional view in the lower part of FIG. 2 are denoted by the same names and the same reference numerals, and description thereof will be omitted as appropriate.

  However, the configuration of FIG. 5 differs from the configuration of FIG. 2 in that a part of the contact C4 on the substrate side (barrier metal film 56 and tungsten 57 on the lower right side in FIG. 5) is in contact with a part of the sidewall 55. It is a point. Specifically, in the configuration of FIG. 5, the nitride film 54 is opened over the entire surface of the polysilicon 53, and alignment between the polysilicon 53 (gate electrode) and the contacts (the barrier metal film 56 and the tungsten 57) is performed. In consideration of the variation of the line width, the contact is applied to the sidewall 55.

  Thereby, compared with the structure of FIG. 2, hydrogen supply can be further promoted and random noise can be reduced more efficiently. In addition, on the channel, light shielding of the in-pixel transistor can be further enhanced, so that variation in transistor characteristics due to light can be suppressed.

<4. Third Embodiment>
FIG. 6 is a diagram illustrating a configuration example of the CMOS image sensor according to the third embodiment. 6 is an enlarged view of the amplification transistor 25 portion of FIG. 1, and the lower portion of FIG. 6 shows the amplification transistor 25 portion (specifically, the contact in the straight line L4 in the upper portion of FIG. A cross-sectional view of C3) is shown.

  In the lower cross-sectional view of FIG. 6, the same components as those in the lower cross-sectional view of FIG. 3 are denoted by the same names and the same reference numerals, and the description thereof will be omitted as appropriate.

  However, the configuration of FIG. 6 differs from the configuration of FIG. 3 in that a part of the contact C3 on the substrate side (barrier metal film 56 and tungsten 57 in the lower stage of FIG. 6) is in contact with a part of the oxide film isolation region 61. It is a point.

  Thereby, compared with the structure of FIG. 3, hydrogen supply can be further promoted and random noise can be reduced more efficiently. In addition, the contact resistance can be lowered and the light shielding of the in-pixel transistor can be further enhanced on the channel, so that variations in transistor characteristics due to light can be suppressed. In addition, by combining the contact C4 of the second embodiment and the contact C3 of the present embodiment, it is possible to further enhance the hydrogen supply and further enhance the light shielding characteristics of the in-pixel transistor. Is clear.

<5. Fourth Embodiment>
FIG. 7 is a diagram illustrating a configuration example of the fourth embodiment of the CMOS image sensor. FIG. 7A shows an enlarged view of the amplification transistor 25 portion of FIG.

  In the present embodiment, as shown in FIG. 7A, in the shape of the surface parallel to the substrate of the contact C4, the longitudinal direction of the substantially rectangular or substantially elliptical shape is the plurality of pixels constituting the pixel array in the CMOS image sensor. This is the same as the extending direction (vertical direction in the figure) of the element region (also referred to as active) formed between the PDs 21.

  Hydrogen supply does not necessarily have a positive effect on the PD 21. When many crystal defects exist, white scratches can be suppressed by terminating dangling bonds with hydrogen. However, when there are few crystal defects, as shown in FIG. There is a possibility that the boron of the P-type layer (+ P) forming the surface is inactivated, and conversely, white scratches are increased.

  Therefore, by adopting the configuration shown in FIG. 7A, it is possible to supply hydrogen sufficiently to the amplifying transistor 25 and to supply as little hydrogen as possible to the PD 21. Thereby, it becomes possible to suppress the deterioration of white scratches caused by hydrogen supply.

<6. Fifth embodiment>
FIG. 8 is a plan view showing a configuration example of the fifth embodiment of the CMOS image sensor.

  In the plan view of FIG. 8, the same components as those in the plan view of FIG. 1 are denoted by the same names and the same reference numerals, and the description thereof will be omitted as appropriate.

  That is, the plan view of FIG. 8 differs from the plan view of FIG. 1 in that dummy contacts C11 to C14 and polysilicon 81 are provided.

  The dummy contacts C11 to C14 are contacts not intended for electrical connection. In particular, the dummy contact C14 is connected to polysilicon 81 as an electrode not intended for electrical connection.

  Thus, by providing the dummy contacts C11 to C14, hydrogen supply can be further promoted, and random noise can be reduced more efficiently. In particular, by providing the dummy contacts C11 to C14 in the vicinity of the amplification transistor 25, the hydrogen supply to the amplification transistor 25 can be more reliably promoted.

  Further, like the dummy contact C14, it may be provided on the gate electrode of the in-pixel transistor. Thereby, it is possible to prevent the substrate and the dummy contact C14 from being short-circuited when the thickness of the oxide film isolation region is thin.

  Further, a metal wiring may be connected to the dummy contacts C11 to C14, and 0 or a negative bias may be applied to the metal wiring. Thereby, it is possible to avoid causing an electrically unstable state with respect to the substrate. In addition, when a positive bias is applied, electrons may be induced under the dummy contacts C11 to C14 and white scratches may occur. However, by applying 0 or a negative bias, the occurrence of white scratches can be suppressed. Can do.

  The dummy contacts C11 to C14 described above may be provided in the configurations of the first to fourth embodiments described with reference to FIGS. 2 to 8, and the cross sections of the dummy contacts C11 to C14. You may make it form the shape of (a surface parallel to a board | substrate) in a substantially rectangular shape or a substantially elliptical shape. Thereby, hydrogen supply can be further promoted, and random noise can be reduced more efficiently.

<7. Manufacturing process of CMOS image sensor>
Next, the manufacturing process of the above-described CMOS image sensor will be described with reference to the flowcharts of FIGS.

  In step S11, a pad oxide film for protecting the Si substrate surface is formed by thermal oxidation, and a nitride film is deposited.

  Specifically, first, as shown in FIG. 12A, for example, a pad oxide film 112 having a thickness of about 15 nm is formed on the surface of the Si substrate 111. Next, a nitride film 113 having a thickness of, for example, 160 nm is deposited by LPCVD (Low Pressure Chemical Vapor Deposition). In this example, the structure of the nitride film and the pad oxide film is formed. However, the structure of the nitride film and polysilicon, or the structure of a silicon (amorphous silicon) and the pad oxide film may be formed. Good.

  In step S12, lithography is performed to process the nitride film 113 and the pad oxide film 112 as shown in FIG. 12B. Here, as the etching apparatus, an RIE (Reactive Ion Etching) apparatus, an ECR (Electron Cyclotron Resonance) apparatus, or the like is used. After the processing, the resist is removed by an ashing device or the like.

  In step S13, trench etching is performed using a nitride film mask. As the etching apparatus, the above-described RIE apparatus or ECR apparatus is used. As a result, a trench 114 is formed as shown in FIG. 12C. The depth of the trench 114 is about 0.3 μm. Thereafter, thermal oxidation (liner oxidation) for the liner oxide film is performed at about 800 to 900 ° C. The liner oxide film may be an oxide film containing nitrogen or a CVD oxide film. The film thickness is about 4 to 10 nm.

In step S14, lithography is performed to suppress dark current, and boron is implanted into the pixel portion (PD portion). Specifically, boron (B) implantation of 1e ^{12 to} 1e ¹⁴ cm ⁻² is performed with an acceleration energy of about 10 keV. As the boron concentration around the element isolation region in the pixel is higher, the generation of dark current and parasitic transistors can be suppressed. However, if the boron concentration is too high, the area of the PD becomes small and the saturation charge Qs becomes small.

  In step S15, as shown in FIG. 13A, an HDP (High Density Plasma) oxide film 116 is deposited in the trench 114 (FIG. 12C). The HDP oxide film 116 may be an inorganic or organic oxide film such as SOG (Spin On Glass). Thereafter, CMP (Chemical Mechanical Polishing) is performed. CMP is stopped by a nitride film.

  In step S16, wet etching is performed on the oxide film in order to adjust the level difference of the trench oxide film from the Si substrate surface. The film thickness of the oxide film etch is about 40 nm to 100 nm. Thereafter, the nitride film 113 is removed by hot phosphoric acid as shown in FIG. 13B.

In step S17, lithography is performed, and p-well implantation and channel implantation are performed. As p-well implantation, boron (B) of about 1e ¹³ cm ⁻² is implanted with an acceleration energy of about 200 keV. As channel implantation, boron (B) of about 1e ^{11 to} 1e ¹³ cm ⁻² is implanted with an acceleration energy of 10 keV to 20 keV. After removing the resist, lithography is performed, and n-well implantation and channel implantation are performed. As n-well implantation, about 1e ¹³ cm ^-2 of phosphorus (P) is implanted with an acceleration energy of about 200 keV. As channel implantation, arsenic (As) of about 1e ^{11 to} 1e ¹³ cm ⁻² is implanted with an acceleration energy of 10 keV to 20 keV. Thereafter, the resist is removed. In this way, as shown in FIG. 14A, a P-type well layer and an N-type well layer are formed.

  In step S18, lithography is performed and ions are implanted into the PD region. Specifically, boron implantation is performed on the surface of the PD region, and an N-type layer (N−) is formed in the deep region of the PD region using As or P. Thereafter, the resist is removed.

  In step S19, the pad oxide film is removed by wet etching to form a high-voltage thick film oxide film 121 shown in FIG. 14B. The thickness of the high-voltage thick oxide film 121 is about 7.5 nm for the power supply voltage 3.3V transistor and about 5.5 nm for the 2.5V transistor.

  In step S20, lithography is performed to remove the thick oxide film 121 formed in the low voltage transistor region. Thereafter, the resist is removed, and a thin film oxide film 122 shown in FIG. 14B is formed. The film thickness of the thin oxide film 122 is about 1.2 to 1.8 nm for a 1.0 V transistor.

  The material of the gate oxide film may be a thermal oxide film or an oxynitride film using RTO (Rapid Thermal Oxidation). In addition, in order to reduce gate leakage, the material of the gate oxide film may be a high dielectric film using an oxide film such as Hf (hafnium) or Zr (zirconium).

  In step S21, polysilicon is deposited by LPCVD.

  FIG. 15 is a cross-sectional view of a pixel region and a peripheral (logic circuit) region in a CMOS image sensor manufacturing process.

  In the cross-sectional view of the pixel region of FIG. 15, a P-type layer 213-1 is formed on the substrate surface side of the P-type well layer 212 formed on the N-type substrate 211, and an N-type buried layer 213- PD is formed by embedding 2. An oxide film 214 is formed on the surface, and an element isolation region 215 is provided.

  In the cross-sectional view of the peripheral region in FIG. 15, the N-type well layer 313-1 and the P-type well layer 313-2 are formed on the surface of the P-type well layer 312 formed on the N-type substrate 311. On the surface, an oxide film 314 is formed, and an element isolation region 315 is provided.

  In step S21, polysilicon 216 shown in the sectional view of the pixel region in FIG. 15 and polysilicon 316 shown in the sectional view of the peripheral region in FIG. 15 are deposited.

  The film thicknesses of the polysilicon 216 and the polysilicon 316 are, for example, about 150 to 200 nm at the 90 nm node. In addition, this film thickness tends to become thinner at each node because the gate aspect ratio is generally not increased because of controllability of processing. In addition, the gate depletion (with the thinning of the gate oxide film, not only the physical gate oxide film thickness but also the influence of the depletion layer thickness in the gate polysilicon can not be ignored, the effective gate film As a countermeasure against the reduction in the thickness and the transistor performance, a polysilicon containing SiGe may be used instead of the polysilicon.

In step S22, lithography is performed, and as a gate depletion countermeasure, as shown in FIG. 16, P or As is implanted into the NMOS region, and B, BF2, or In is implanted into the PMOS region, although not shown. To do. The injection amount is about 1e ^{15 to} 1e ¹⁶ cm ⁻² , respectively. In order to prevent impurities from penetrating directly under the gate oxide film, N2 may be implanted together. After the implantation, the resist RG is removed.

  In step S23, as shown in FIG. 17A, an insulating film 401 serving as a mask during gate processing is deposited. As the mask material, an oxide film, a nitride film, or the like is used, and the film thickness is about 10 to 100 nm. Next, lithography is performed, and the mask insulating film is processed using an RIE apparatus or the like. Thereafter, the resist RG is removed. Further, gate processing is performed using an RIE apparatus or the like. After processing, for example, when the mask material is a nitride film, the mask material is removed by wet etching. As a result, a polysilicon gate 411 is formed as shown in FIG. 17B.

In step S24, as shown in FIG. 18, LDD ion implantation is performed on the PMOS region in the peripheral region. Specifically, lithography is performed, and pocket implantation and LDD ion implantation are performed. Pocket implantation into the PMOS region is performed with As or P at an implantation concentration of about 1e ^{12 to} 1e ¹⁴ cm ⁻² . The extension implantation is performed with B, BF2, or In at an implantation concentration of about 1e ^{13 to} 1e ¹⁵ cm ⁻² . After the implantation, the resist RG is removed.

In step S25, as shown in FIG. 19, LDD ion implantation is performed on the NMOS region in the peripheral region. Specifically, lithography is performed, and pocket implantation and LDD ion implantation are performed. Pocket implantation into the NMOS region is performed with B, BF 2, or In at an implantation concentration of about 1e ^{12 to} 1e ¹⁴ cm ⁻² . LDD ion implantation is performed with As or P at an implantation concentration of about 1e ^{13 to} 1e ¹⁵ cm ⁻² . After the implantation, the resist RG is removed.

  Note that, before pocket injection in step S24 and step S25, preamorphization may be performed by implanting Ge or the like in order to suppress channeling of implantation. Further, after the extension region is formed, an RTA (Rapid Thermal Annealing) process at about 800 to 900 ° C. may be performed in order to reduce implantation defects that cause TED (Transient Enhanced Diffusion) or the like.

  In step S26, a sidewall is formed. Specifically, by CVD, an oxide film 421 is deposited by about 10 nm as shown in FIG. 20A, and a nitride film 422 is deposited by about 50 nm as shown in FIG. 20B. Then, sidewalls are formed using an RIE apparatus or the like. The sidewall structure may be a three-layer structure of SiO2, Si3N4, and SiO2 instead of a two-layer structure of SiO2 and Si3N4.

  In step S27, lithography is performed to process the sidewalls in the peripheral region as shown in FIG. From the viewpoint of reducing man-hours, the sidewalls of the pixel region may be processed without performing lithography.

  In step S28, a third-layer film 423 such as an oxide film is deposited as a sidewall film (SW film) as shown in FIG.

  In step S29, as shown in FIG. 23, the third layer film 423 (SW film) is etched back. Here, in the pixel region, the etch back is stopped by the nitride film 422 in order to prevent damage due to the etch back. Thereby, dark current can be suppressed.

In step S30, as shown in FIG. 24, SD implantation is performed in the PMOS region with respect to the peripheral region. SD implantation is performed with B or BF 2 at an implantation concentration of about 1e ^{15 to} 1e ¹⁶ cm ⁻² . Thereby, the SD diffusion layer 431 is formed.

In step S31, as shown in FIG. 25, SD implantation is performed in the NMOS region with respect to the peripheral region. SD implantation is performed with As or P at an implantation concentration of about 1e ^{15 to} 1e ¹⁶ cm ^-2 . Thereby, the SD diffusion layer 432 is formed.

In step S32, as shown in FIG. 26, B or BF2 is implanted into the pixel region through the nitride film 422 and the oxide film 421. The implantation concentration is about 1e ^{15 to} 1e ¹⁶ cm ⁻² . Thereby, the diffusion layer 433 is formed.

In step S33, As or P is implanted into the pixel region as shown in FIG. The implantation concentration is about 1e ^{15 to} 1e ¹⁶ cm ⁻² . After the implantation, the resist is removed. Thereafter, activation annealing is performed at about 800 to 1100 ° C. using an apparatus for performing RTA processing or Spike-RTA processing. Thereby, the diffusion layer 434 is formed.

  In step S34, silicide 441 is formed in the peripheral region as shown in FIG. As the silicide 441, CoSi2, NiSi, TiSi2, PtSi, WSi2 or the like is used. Here, a case where NiSi is used will be described. First, about 10 nm of Ni is deposited using a sputtering apparatus. Next, after annealing at about 300 to 400 ° C., Ni is wet etched. Thereby, only the surface of silicon or polysilicon other than the insulating film is silicided in a self-aligning manner. Thereafter, annealing is performed at about 500 to 600 ° C. The pixel region is blocked by silicide with SiN so that no silicide is formed.

  In step S35, SiN (interlayer insulating film 442) is deposited as shown in FIG. As SiN, LP-SiN or plasma SiN is used. The interlayer insulating film 442 has an effect of minimizing contact etch overetching, and can suppress an increase in junction leakage due to etching damage. In the contact etching, first, the interlayer insulating film 442 is stopped, and the variation of the oxide film on SiN is absorbed. Next, the upper side of the gate 411 and the diffusion layers 431 to 434 is opened by etching the interlayer insulating film 442. The film thickness of the interlayer insulating film 442 is 10 to 100 nm.

  In step S36, as shown in FIG. 30, an oxide film 451 is deposited by CVD. As the oxide film 451, a film such as TEOS, PSG, BPSG, and SOG is used, and the film thickness is about 100 to 1000 nm. Then, CMP is performed to flatten the surface.

  In step S37, lithography is performed and a contact portion (contact hole) is processed using an RIE apparatus or the like. Thereafter, the resist is removed.

  In step S38, TiN or Ti is deposited by sputtering or CVD as a tungsten (W) barrier metal film. Since the tungsten film is highly stressed and may be peeled off when directly deposited on the silicon oxide film, a barrier metal film 452 is deposited as shown in FIG. Thereafter, annealing is performed at about 600 ° C.

  In step S39, as shown in FIG. 31, tungsten 453 is deposited by CVD. For the deposition of tungsten 453, WF6 is used as the source gas and H2 or SiH4 is used as the reducing agent. At this time, the supply of hydrogen is facilitated by the absence of SiN in the contact hole and the use of H2 during the deposition of tungsten 453.

  The film thickness of tungsten 453 is about 100 to 500 nm. Here, by forming the contact layout pattern, in other words, the shape of the surface parallel to the substrate of the contact in a substantially rectangular shape or a substantially elliptical shape, the film thickness of the tungsten 453 can be reduced and the cost can be reduced. Can do. Specifically, when the aspect ratio of the contact layout pattern is 1: 1, increasing the layout pattern increases the film thickness for embedding the layout pattern. However, the layout pattern is substantially rectangular or elliptical. Thus, tungsten 453 can be embedded with a film thickness corresponding to the side (or axis) having the smaller aspect ratio.

  In step S40, CMP of W (tungsten) is performed so that tungsten is embedded only in the contact hole. Here, etch back may be performed instead of CMP.

  In step S41, a wiring layer is formed. Specifically, Al is deposited by sputtering. As a material, Cu having a lower resistance than Al may be used. Next, lithography is performed, and wiring is processed using an RIE apparatus or the like. In this way, the wiring 454 shown in FIG. 32 is formed. Note that the wiring layer is not limited to one layer, and may have a multilayer structure such as two layers, three layers,.

  In step S42, a plasma nitride film is deposited and hydrogen is supplied to supply hydrogen. Thereafter, the pad portion (electrode) is opened by lithography or etching. Further, a lens or a waveguide for condensing light may be formed on the PD, or a color filter for dispersing light may be provided.

  According to the above processing, the shape of the surface parallel to the substrate of the contact connected to the electrode of the in-pixel transistor can be formed into a substantially rectangular shape or a substantially elliptical shape. Therefore, in the CMOS image sensor, hydrogen supply can be promoted and random noise can be reduced.

  The dummy contact described with reference to FIG. 8 may be formed in steps S37 to S40 in the above-described CMOS image sensor manufacturing process.

  The embodiments of the present technology are not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present technology.

Furthermore, this technique can take the following structures.
(1) A pixel array formed on a substrate and having a two-dimensional array of pixels including a photoelectric conversion unit and a plurality of in-pixel transistors,
A shape of a surface parallel to the substrate of a contact connected only to an electrode of a predetermined intra-pixel transistor among the plurality of intra-pixel transistors is formed in a substantially rectangular shape or a substantially elliptical shape.
(2) The solid-state imaging device according to (1), wherein the predetermined in-pixel transistor is an amplification transistor.
(3) The solid-state imaging device according to (1) or (2), wherein the contact is connected to a gate electrode of the predetermined intra-pixel transistor.
(4) The solid-state imaging device according to (3), wherein at least a part of the contact on the substrate side is in contact with a sidewall formed on a sidewall of the gate electrode of the predetermined in-pixel transistor.
(5) The solid-state imaging device according to (1) or (2), wherein at least a part of the contact on the substrate side is in contact with a region that electrically isolates the predetermined in-pixel transistor.
(6) In the shape of the surface of the contact parallel to the substrate, the longitudinal direction of the substantially rectangular or substantially elliptical shape is the same as the extending direction of the element region formed between the photoelectric conversion portions of the plurality of pixels. The solid-state imaging device according to any one of (1) to (3).
(7) The shape of the surface parallel to the substrate of the contact connected to the electrode of the other in-pixel transistor among the plurality of in-pixel transistors is substantially square,
The shape of the surface parallel to the substrate of the contact connected only to the electrode of the predetermined intra-pixel transistor is a substantially rectangular shape having a short side length equal to the length of one side of the square, or a short axis The solid-state imaging device according to any one of (1) to (3), wherein the length is a substantially oval shape equal to the length of one side of the square.
(8) The solid-state imaging device according to any one of (1) to (7), wherein a dummy contact that is not electrically connected is formed in addition to contacts that are connected to the electrodes of the plurality of in-pixel transistors.
(9) The solid-state imaging device according to (8), wherein the dummy contact is provided on a gate electrode of the in-pixel transistor.
(10) The solid-state imaging device according to (8) or (9), wherein the dummy contact is connected to a metal wiring.
(11) The solid-state imaging device according to (10), wherein 0 or a negative bias is applied to the metal wiring.
(12) The solid-state imaging device according to any one of (8) to (10), wherein a shape of a surface of the dummy contact parallel to the substrate is substantially rectangular or elliptical.
(13) A method of manufacturing a solid-state imaging device including a pixel array formed on a substrate and having a two-dimensional array of pixels including a photoelectric conversion unit and a plurality of in-pixel transistors,
A solid-state imaging device comprising: a step of forming a shape of a surface parallel to the substrate of a contact connected only to an electrode of a predetermined intra-pixel transistor among the plurality of intra-pixel transistors into a substantially rectangular shape or a substantially elliptical shape. Production method.
(14) A pixel array formed on a substrate and having a two-dimensional array of pixels each including a photoelectric conversion unit and a plurality of in-pixel transistors,
A solid-state imaging device in which dummy contacts that are not electrically connected are formed in addition to contacts that are connected to electrodes of the plurality of transistors in the pixel.
(15) The solid-state imaging device according to (14), wherein the dummy contact is provided on a gate electrode of the in-pixel transistor.
(16) The solid-state imaging device according to (14) or (15), wherein the dummy contact is connected to a metal wiring.
(17) The solid-state imaging device according to (16), wherein 0 or a negative bias is applied to the metal wiring.
(18) The solid-state imaging device according to any one of (14) to (17), wherein a shape of a surface of the dummy contact parallel to the substrate is substantially rectangular or elliptical.
(19) A method of manufacturing a solid-state imaging device including a pixel array formed on a substrate and having a two-dimensional array of pixels including a photoelectric conversion unit and a plurality of in-pixel transistors,
A method for manufacturing a solid-state imaging device, comprising: forming a dummy contact that is not electrically connected, in addition to contacts that are connected to the electrodes of the plurality of transistors in the pixel.

  21 PD, 22 transfer transistor, 24 reset transistor, 25 amplification transistor, 26 selection transistor, C1 to C5 contact, C11 to C14 dummy contact

Claims (19)

A pixel array formed on a substrate and having a two-dimensional array of pixels including a photoelectric conversion unit and a plurality of in-pixel transistors;
A shape of a surface parallel to the substrate of a contact connected only to an electrode of a predetermined intra-pixel transistor among the plurality of intra-pixel transistors is formed in a substantially rectangular shape or a substantially elliptical shape. The solid-state imaging device according to claim 1, wherein the predetermined intra-pixel transistor is an amplification transistor. The solid-state imaging device according to claim 1, wherein the contact is connected only to a gate electrode of the predetermined intra-pixel transistor. The solid-state imaging device according to claim 3, wherein at least a part of the contact on the substrate side is in contact with a sidewall formed on a sidewall of the gate electrode of the predetermined in-pixel transistor. The solid-state imaging device according to claim 1, wherein at least a part of the contact on the substrate side is in contact with a region that electrically isolates the predetermined in-pixel transistor. The shape of a surface parallel to the substrate of the contact has a substantially rectangular or substantially elliptical longitudinal direction that is the same as an extending direction of an element region formed between the photoelectric conversion portions of the plurality of pixels. The solid-state imaging device according to 1. The shape of the surface parallel to the substrate of the contact connected only to the electrode of the other in-pixel transistor among the plurality of in-pixel transistors is substantially square,
The shape of the surface parallel to the substrate of the contact connected only to the electrode of the predetermined intra-pixel transistor is a substantially rectangular shape having a short side length equal to the length of one side of the square, or a short axis The solid-state imaging device according to claim 1, wherein the length is a substantially elliptical shape equal to a length of one side of the square. The solid-state imaging device according to claim 1, wherein a dummy contact that is not electrically connected is formed in addition to contacts that are connected to electrodes of the plurality of pixels in the pixel. The solid-state imaging device according to claim 8, wherein the dummy contact is provided on a gate electrode of the in-pixel transistor. The solid-state imaging device according to claim 8, wherein the dummy contact is connected to a metal wiring. The solid-state imaging device according to claim 10, wherein 0 or a negative bias is applied to the metal wiring. The solid-state imaging device according to claim 8, wherein a shape of a surface of the dummy contact parallel to the substrate is formed in a substantially rectangular shape or a substantially elliptical shape. A method of manufacturing a solid-state imaging device including a pixel array formed on a substrate and having a two-dimensional array of pixels including a photoelectric conversion unit and a plurality of in-pixel transistors,
A solid-state imaging device comprising: a step of forming a shape of a surface parallel to the substrate of a contact connected only to an electrode of a predetermined intra-pixel transistor among the plurality of intra-pixel transistors into a substantially rectangular shape or a substantially elliptical shape. Production method. A pixel array formed on a substrate and having a two-dimensional array of pixels including a photoelectric conversion unit and a plurality of in-pixel transistors;
A solid-state imaging device in which dummy contacts that are not electrically connected are formed in addition to contacts that are connected to electrodes of the plurality of transistors in the pixel. The solid-state imaging device according to claim 14, wherein the dummy contact is provided on a gate electrode of the in-pixel transistor. The solid-state imaging device according to claim 14, wherein the dummy contact is connected to a metal wiring. The solid-state imaging device according to claim 16, wherein zero or a negative bias is applied to the metal wiring. The solid-state imaging device according to claim 14, wherein a shape of a surface of the dummy contact parallel to the substrate is formed in a substantially rectangular shape or a substantially elliptical shape. A method of manufacturing a solid-state imaging device including a pixel array formed on a substrate and having a two-dimensional array of pixels including a photoelectric conversion unit and a plurality of in-pixel transistors,
A method for manufacturing a solid-state imaging device, comprising: forming a dummy contact that is not electrically connected, in addition to contacts that are connected to the electrodes of the plurality of transistors in the pixel.

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