JP7009529B2 - A photoelectric conversion device, a device equipped with a photoelectric conversion device, and a method for manufacturing a photoelectric conversion device. - Google Patents

Description

The present invention relates to a photoelectric conversion device.

In the photoelectric conversion device, a photoelectric conversion unit and an element other than the photoelectric conversion unit are provided on the same semiconductor substrate. An antireflection structure and a waveguide structure are provided on the photoelectric conversion unit, and a contact plug or the like is connected to the element. Therefore, it is necessary to design the photoelectric conversion device in consideration of the characteristics of both the photoelectric conversion unit and other elements.

According to Patent Document 1, a film having the same layer as the sidewall forming film (137) having a laminated structure of a silicon oxide film (134), a silicon nitride film and (135) on the photoelectric conversion unit (21). Discloses the formation of the silicide block film (71). Further, it is disclosed that an etching stopper film (74) of a silicon nitride film is formed on the entire surface of the pixel portion (12) and the peripheral circuit portion (13). Further, it is disclosed that a waveguide (23) is formed on the photoelectric conversion unit (21).

Patent Document 2 describes a control film (410) that serves as an etching stopper when forming an opening (421) for a light guide member (420) and a protective film that serves as an etching stop for forming a contact hole in a peripheral circuit region. 250) and are disclosed. Then, it is described that the control film (410) and the protective film (250) are formed from the same silicon nitride film.

In Patent Document 3, a waveguide is formed that penetrates the interlayer insulating film (IF1) and the contact etch stress liner film (CESL) that is a silicon nitride film and reaches the sidewall insulating film (SWI) that is a silicon nitride film. Is disclosed.

Japanese Unexamined Patent Publication No. 2010-56516 Japanese Unexamined Patent Publication No. 2013-84740 Japanese Unexamined Patent Publication No. 2014-56878

In the conventional technique, noise is generated due to contamination or damage to the photoelectric conversion unit, and the quality of the photoelectric conversion may be deteriorated. Further, the reliability of the electrical connection to the element other than the photoelectric conversion unit is important for ensuring the reliability of the photoelectric conversion device. The conventional technology does not sufficiently improve the performance and reliability of the photoelectric conversion device.

Therefore, an object of the present invention is to provide a photoelectric conversion device having improved performance and reliability.

The first aspect of the means for solving the problem is a photoelectric conversion device, which is provided on the semiconductor substrate having the photoelectric conversion unit and the semiconductor substrate so as not to overlap at least a part of the photoelectric conversion unit. The photoelectric has a metal-containing portion, an interlayer insulating film arranged on the semiconductor substrate so as to cover the metal-containing portion, and a portion located between the interlayer insulating film and the semiconductor substrate. The first silicon nitride layer arranged on the conversion portion, the portion arranged between the first silicon nitride layer and the photoelectric conversion portion, and between the interlayer insulating film and the metal-containing portion. A silicon oxide film having an arranged portion, a second silicon nitride layer arranged between the silicon oxide film and the metal-containing portion, an interlayer insulating film, the silicon oxide film, and the second silicon nitride layer. It is characterized by comprising a contact plug penetrating the metal-containing portion and contacting the semiconductor substrate, and a contact plug penetrating the interlayer insulating film and the silicon oxide film and contacting the semiconductor substrate.

The second aspect of the means to solve the problem is
A photoelectric conversion device, on a semiconductor substrate having a photoelectric conversion unit, a metal-containing portion provided on the semiconductor substrate so as not to overlap at least a part of the photoelectric conversion unit, and on the photoelectric conversion unit. In the arranged first silicon nitride layer, the distance between the photoelectric conversion unit and the first silicon nitride layer is smaller than the distance between the wiring layer and the semiconductor substrate. A silicon oxide film having a layer, a portion arranged between the first silicon nitride layer and the photoelectric conversion portion, and a portion arranged on the metal-containing portion, the silicon oxide film, and the metal. It is provided with a second silicon nitride layer arranged between the containing portion and a contact plug that penetrates the silicon oxide film and the second silicon nitride layer and comes into contact with the wiring layer and the metal containing portion. It is a feature.

The third aspect of the means for solving problems is
A photoelectric conversion device that covers a semiconductor substrate having a photoelectric conversion unit, an electrode arranged on the semiconductor substrate, a sidewall spacer that covers the side surface of the electrode, and the electrode and the sidewall spacer. An interlayer insulating film arranged on the semiconductor substrate, a first silicon nitride layer arranged on the photoelectric conversion unit, and a portion arranged between the first silicon nitride layer and the photoelectric conversion unit. A second silicon nitride layer having a silicon oxide film located between the interlayer insulating film and the sidewall spacer, and a portion arranged between the silicon oxide film and the sidewall spacer, and the said. A contact plug that penetrates the interlayer insulating film, the silicon oxide film, and the silicon nitride layer and is connected to an element including the electrode, and the distance between the photoelectric conversion unit and the first silicon nitride layer is determined. It is characterized by comprising the contact plug, which is smaller than the length of the contact plug.

The fourth aspect of the means for solving the problem is a method for manufacturing a photoelectric conversion device, which is a step of forming a first silicon nitride film so as to cover a metal-containing portion on a semiconductor substrate, and a first nitride. A step of forming a silicon oxide film on the silicon film so as to cover the photoelectric conversion portion provided on the semiconductor substrate, a step of forming a second silicon nitride film so as to cover the photoelectric conversion portion, and the first step. An interlayer insulating film is formed so as to cover a portion of the silicon nitride film located above the metal-containing portion and a portion of the second silicon nitride film located above the photoelectric conversion portion. It is characterized by having a step of forming a hole located above the metal-containing portion in the interlayer insulating film and the first silicon nitride film, and a step of arranging a conductor in the hole. And.

The fifth aspect of the means for solving the problem is a method for manufacturing a photoelectric conversion device, which is a step of forming a first silicon nitride film so as to cover a metal-containing portion on a semiconductor substrate, and the semiconductor substrate. A step of forming a second silicon nitride film so as to cover the photoelectric conversion portion and the metal-containing portion provided in the first silicon nitride film, a portion of the first silicon nitride film located above the metal-containing portion, and the first. A step of forming an interlayer insulating film so as to cover a portion of the silicon nitride film located above the photoelectric conversion portion, and a metal-containing portion on the interlayer insulating film and the first silicon nitride film. It comprises a step of forming a hole located in the hole and a step of arranging a conductor in the hole, and the second silicon nitride film is characterized in that it is thicker than the first silicon nitride film.

INDUSTRIAL APPLICABILITY According to the present invention, a photoelectric conversion device having improved performance and reliability is provided.

The schematic diagram explaining the photoelectric conversion apparatus. The schematic diagram explaining the structure of a photoelectric conversion apparatus. The schematic diagram explaining the structure of a photoelectric conversion apparatus. The schematic diagram explaining the manufacturing method of a photoelectric conversion apparatus. The schematic diagram explaining the manufacturing method of a photoelectric conversion apparatus. The schematic diagram explaining the manufacturing method of a photoelectric conversion apparatus. The schematic diagram explaining the manufacturing method of a photoelectric conversion apparatus. The schematic diagram explaining the manufacturing method of a photoelectric conversion apparatus. The schematic diagram explaining the structure of a photoelectric conversion apparatus. The schematic diagram explaining the structure of a photoelectric conversion apparatus.

Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. In the following description and drawings, common reference numerals are given to common configurations across a plurality of drawings. Therefore, a common configuration will be described with reference to each other with reference to a plurality of drawings, and the description of the configuration with a common reference numeral will be omitted as appropriate. Further, the configurations having the same name but different reference numerals can be distinguished as the first configuration, the second configuration, the third configuration, and the like.

FIG. 1A is a schematic diagram of an apparatus EQP including a photoelectric conversion device APR according to an embodiment of the present invention. The photoelectric conversion device APR includes a semiconductor device IC. The semiconductor device IC is a semiconductor chip provided with a semiconductor integrated circuit. In addition to the semiconductor device IC, the photoelectric conversion device APR can include a package PKG for storing these. The photoelectric conversion device APR can be used as an image sensor, an AF (Auto Focus) sensor, a photometric sensor, and a distance measuring sensor.

The equipment EQP may further include at least one of an optical system OPT, a control device CTRL, a processing device PRCS, a display device DSPL, a storage device MMRY, and a mechanical device MCNH. The details of the device EQP will be described later.

The semiconductor device IC has a pixel area PX in which a pixel circuit PXC including a photoelectric conversion unit is arranged two-dimensionally. The semiconductor device IC can have a peripheral area PR around the pixel area PX. Further, in the peripheral area PR, a drive circuit for driving the pixel circuit PXC, a signal processing circuit for processing the signal from the pixel circuit PXC, and a control circuit for controlling the drive circuit and the signal processing circuit shall be arranged. Can be done. The signal processing circuit can perform signal processing such as correlated double sampling (CDS: Correlated Double Sampling) processing, amplification processing, and AD (Analog-Digital) conversion processing. As another example of the semiconductor device IC, at least a part of the peripheral circuit arranged in the peripheral area PR is arranged in a semiconductor chip different from the semiconductor chip in which the pixel area PX is arranged, and both semiconductor chips are arranged. It can also be stacked.

FIG. 1B shows an example of the pixel circuit PXC. The pixel circuit unit PXC includes a photoelectric conversion element PD1, a photoelectric conversion element PD2, a transfer gate TX1, a transfer gate TX2, and a capacitive element FD. including. Further, the pixel circuit PXC can include an amplification transistor SF, a reset transistor RS, and a selection transistor SL. The photoelectric conversion elements PD1 and PD2 are photodiodes or photogates, respectively. The transfer gates TX1 and TX2 are MIS (Metal-Insulator-Semiconductor) gates, the amplification transistor SF, the reset transistor RS, and the selection transistor SL is a MIS transistor. The amplification transistor SF may be a junction field effect transistor. In this example, two photoelectric conversion elements PD1 and PD2 share one amplification transistor SF, but three or more photoelectric conversion elements may share one amplification transistor SF, or the photoelectric conversion element PD1 may be shared. , The amplification transistor SF may be provided for each PD2. The structures of the amplification transistor SF, the reset transistor RS, and the selection transistor SL may be the same, and the reset transistor RS, the selection transistor SL, and the amplification transistor SF are collectively referred to as a pixel transistor. The transfer gates TX1 and TX2, pixel transistors, and peripheral transistors are semiconductor elements including gate electrodes. In addition, the photoelectric conversion device APR can include semiconductor elements such as diodes, resistance elements, and capacitive elements.

The signal charges generated by the photoelectric conversion elements PD1 and PD2 are transferred to the floating node FN of the capacitive element FD via the transfer gates TX1 and TX2. The gate of the amplification transistor SF constituting the source follower circuit together with the current source CS is connected to the floating node FN, and a pixel signal as a voltage signal is output to the signal output line OUT. The reset transistor RS resets the charge and potential of the floating node FN, and the selection transistor SL switches the connection between the amplification transistor SF and the signal output line OUT. The reset transistor RS and the amplification transistor SF are connected to the power supply line VDD. The signal output line OUT and the power supply line VDD are provided for each row of the pixel circuit PXC. Focus detection and distance measurement by the phase difference detection method are possible based on the difference in signals between the photoelectric conversion elements PD1 and PD2. Further, imaging is possible by the signals of one or both of the photoelectric conversion elements PD1 and PD2.

FIG. 2A is a schematic plan view of the vicinity of the surface of the pixel area PX of the semiconductor substrate 10 included in the photoelectric conversion device APR, and FIG. 2B is a cross-sectional view taken along the line AB of FIG. 2A. It is a schematic sectional view of the photoelectric conversion apparatus APR including. Hereinafter, the structure of the photoelectric conversion device APR will be described without distinguishing between the plan view and the cross-sectional view. The column direction, which is the direction in which the pixels are arranged in the pixel column of the pixel area PX, is the X direction, and the row direction, which is the direction in which the pixels of the pixel row of the pixel area PX are arranged, is the Y direction, indicating the thickness of the layer or film. The thickness direction is the Z direction. The X, Y and Z directions are orthogonal to each other.

This embodiment is characterized by the positional relationship between a member (layer or film) made of silicon oxide and a member (layer or film) made of silicon nitride. The members made of silicon oxide, which will be described as separate members, have members made of different materials between them, or members having different compositions even if they are similar materials. The same applies to the member made of silicon nitride. Membranes are plane-continuous, but layers may be plane-discontinuous. Silicon oxide in the following description is a compound of oxygen (O) and silicon (Si), and is a light element (hydrogen (H) and helium (hydrogen (H)), which occupy the top two composition ratios of the constituent elements of the compound. It means a compound in which elements other than He)) are oxygen (O) and silicon (Si). Silicon oxide can contain light elements such as hydrogen (H), and the amount (atomic%) thereof may be higher or lower than that of oxygen (O) and silicon (Si). Silicon oxide can contain elements other than oxygen (O), silicon (Si), hydrogen (H) and helium (He) at lower concentrations than oxygen (O) and silicon (Si). Typical elements that can be contained in silicon oxide include hydrogen (H), boron (B), carbon (C), nitrogen (N), fluorine (F), phosphorus (P), chlorine (Cl), and Ar ( Argon). When the element other than the light element, which is the third most abundant element of silicon oxide, is nitrogen, this silicon oxide can be referred to as silicon nitride oxide or nitrogen-containing silicon oxide.

Similarly, silicon nitride is a compound of nitrogen (N) and silicon (Si), and elements other than light elements that occupy the top two composition ratios of the constituent elements of the compound are nitrogen (N) and silicon. It means a compound which is (Si). When the element other than the light element, which is the third most abundant element of silicon nitride, is oxygen, this silicon nitride can be referred to as silicon oxide or oxygen-containing silicon nitride. Silicon nitride can contain nitrogen (N), silicon (Si) and above, and non-light element elements at lower concentrations than nitrogen (N) and silicon (Si). Typical elements that can be contained in silicon nitride are boron (B), carbon (C), oxygen (O), fluorine (F), phosphorus (P), chlorine (Cl), and Ar (argon). When the element other than the light element, which is the third most abundant element of silicon nitride, is oxygen, this silicon nitride can be referred to as silicon oxide or oxygen-containing silicon nitride. The elements contained in the constituent members of the photoelectric conversion device APR can be analyzed by energy dispersive X-ray analysis (EDX: Energy dispersive X-ray spectroscopy). The hydrogen content can be analyzed by the elastic recoil detection analysis (ERDA: Elastic Recoil Detection Analysis :) method.

In the pixel area PX of the semiconductor substrate 10, a photoelectric conversion unit 11, a charge detection unit 12, a pixel transistor drain 13, and a pixel transistor source 14 are provided in the element region defined by the element separation region 9. Further, in the peripheral area PR of the semiconductor substrate 10, the source 16 and the drain 17 of the peripheral transistor are provided in the element region defined by the element separation region 9.

A transfer gate TX1, a gate electrode 42 of TX2, and a gate electrode 43 of a pixel transistor are arranged on the semiconductor substrate 10. A dielectric region 61 is arranged on the photoelectric conversion unit 11 via a silicon nitride layer 31. FIG. 2A shows the contours of the silicon nitride layer 31 and the dielectric region 61. Further, a gate electrode 47 of a peripheral transistor is arranged on the semiconductor substrate 10. The peripheral transistor is arranged in the peripheral area PR, and is, for example, an IGMP transistor or a polyclonal transistor constituting a CMOS circuit, and is referred to as a polyclonal transistor in this example.

Contact plugs 501, 502, 503, and 504 are arranged on the semiconductor substrate 10 so as to penetrate the interlayer insulating film 40. The contact plugs 501, 502, 503, and 504 are conductive members containing a barrier metal such as titanium or titanium nitride and a conductor such as tungsten. Typically, the barrier metal of the contact plugs 501, 502, 503, 504 comes into contact with the interlayer insulating film 40. The contact plugs 501, 502, 503, and 504 are provided in holes (contact holes) formed in the membrane or layer through which the contact plugs 501, 502, 503, and 504 penetrate. The contact plug 501 is connected to the charge detection unit 12 and the drain 13, and the contact plug 502 is connected to the gate electrodes 42 and 43. The contact plug 503 is connected to the source 16 and the drain 17, and the contact plug 504 is connected to the gate electrode 47.

Interlayer insulating films 50 and 70 are arranged on the semiconductor substrate 10. The interlayer insulating film 50 is a laminated film of an interlayer insulating layer 56 and a diffusion prevention layer 57, and wiring layers 51, 52, and 53 covered with a diffusion prevention layer 57 are provided between the plurality of interlayer insulating layers 56. .. The wiring layer 51 is in contact with the contact plugs 501, 502, 503, 504. The number of layers of the silicon carbide layer including the diffusion prevention layer 57 may be 1 times or more and less than 2 times the number of layers of the copper wiring layer. In this example, the number of layers of the silicon carbide layer is three, and the number of layers of the copper wiring layer is also three. The interlayer insulating layer 56 is a silicon oxide layer, and the silicon oxide layer preferably contains 5 to 30 atomic% of hydrogen. The diffusion prevention layer 57 is a silicon carbide layer, and the silicon carbide layer can contain 20 to 60 atomic% of hydrogen.

A dielectric member 60 is provided on the semiconductor substrate 10. The dielectric member 60 is a member in which a dielectric region 61 surrounded by the interlayer insulating films 40 and 50 and a dielectric film 62 located on the interlayer insulating film 50 are integrated. As shown in FIG. 2A, the dielectric region 61 of this example can be arranged over a plurality of photoelectric conversion units 11 to improve the sensitivity, but the dielectric region 61 of each of the plurality of photoelectric conversion units 11 is dielectric. By arranging the body region 61, the light separation accuracy can be improved. The material of the dielectric member 60 is silicon oxide, silicon nitride and / or resin. The refractive index of the dielectric member 60 is preferably higher than the refractive index of the interlayer insulating layer 56, but may be equal to the refractive index of the interlayer insulating layer 56 or lower than the refractive index of the interlayer insulating layer 56. good. The refractive index of the dielectric member 60 may be lower than that of the diffusion prevention layer 57. The boundary between the dielectric region 61 and the dielectric film 62 is defined by a virtual plane (dotted line in FIG. 2B) including the upper surface of the interlayer insulating film 50. The interlayer insulating film 70 covers the dielectric member 60, and the wiring layer 55 on the interlayer insulating film 70 is connected to the wiring layer 53 via a via plug 54 penetrating the interlayer insulating film 70. The interlayer insulating film 70 is a silicon oxide film, and the silicon oxide film can contain 5 to 30 atomic% of hydrogen. An inorganic material film 80 having an in-layer lens is provided on the interlayer insulating film 70. The inorganic material film 80 can function as a passage film or an antireflection film. The inorganic material film 80 may be a multi-layer film including at least two layers of a silicon nitride layer, a silicon oxynitride layer, a silicon nitride layer, and a silicon oxide layer. An organic material film 90 composed of a flattening layer 91, a color filter layer 92, a flattening layer 93, and a microlens layer 94 is provided on the silicon nitride film. The color filter layer 92 constitutes a multi-color filter array, and the microlens layer 94 constitutes a microlens array.

FIG. 3 is a schematic cross-sectional view showing a detailed configuration between the semiconductor substrate 10, the interlayer insulating film 40, and the dielectric region 61 in the photoelectric conversion device APR described with reference to FIG. 2.

The photoelectric conversion unit 11 constitutes the photoelectric conversion elements PD1 and PD2 as photodiodes. The photoelectric conversion unit 11 has an n-type semiconductor region 111 as a charge storage region (cathode) and a p-type semiconductor region 112 as a well region (anode) provided deeper than the semiconductor region 111 in the semiconductor substrate 10. include. The photoelectric conversion unit 11 includes a p-type semiconductor region 113 as a surface separation region provided between the semiconductor region 111 and the surface of the semiconductor substrate 10. Due to the semiconductor region 113, the photoelectric conversion unit 11 is an embedded photodiode.

The gate electrodes 42 and 43 are, for example, n-type polysilicon electrodes. The thickness T42 of the gate electrode 42 is, for example, 50 to 300 nm, and typically 100 to 200 nm. The thickness of the gate electrode 42 is equivalent to the thickness T42. The gate electrode 47 has a polyside structure including a p-type polysilicon portion 471 and a metal-containing portion 473. The thickness of the gate electrode 47 may be larger than or equivalent to the thickness T42. Semiconductor elements such as resistance elements and capacitive elements arranged in the peripheral area PR can also be configured by the polysilicon electrodes, and can have the same configuration as the gate electrodes 42, 43, 47. The contact plug 504 makes contact with the metal-containing portion 473. The sidewall spacer 48 is a multi-layer member including a silicon nitride layer 483 and a silicon oxide layer 482. The silicon oxide layer 482 is located between the silicon nitride layer 483 and the side surface of the gate electrode 47, and between the silicon nitride layer 483 and the semiconductor substrate 10 (semiconductor regions 151, 161).

A gate insulating film 24 is arranged between the gate electrodes 42 and 43 and the semiconductor substrate 10. A gate insulating film 26 is arranged between the gate electrode 47 and the semiconductor substrate 10. The gate insulating film 24 can be made thinner than the gate insulating film 26, for example, the thickness of the gate insulating film 24 is 5 to 10 nm, and the thickness of the gate insulating film 26 is 1 to 5 nm. The gate insulating film 24 and the gate insulating film 26 can be a silicon oxide film containing nitrogen.

A sidewall spacer 48 of the gate electrode 47 is provided so as to cover the side surface of the gate electrode 47.

The charge detection unit 12 constituting the capacitive element FD includes a low-concentration n-type semiconductor region 121 and a high-concentration n-type semiconductor region 122. The semiconductor region 121 functions as a floating diffusion region. The semiconductor region 121 is located below the contact plug 501 and functions as a contact region with which the contact plug 501 contacts. A metal compound (silicide) between the metal component of the contact plug 501 and the semiconductor component of the semiconductor substrate 10 may be formed between the contact plug 501 and the semiconductor substrate 10 (semiconductor regions 122 and 132). In this case as well, it can be said that the contact plug 501 contacts the semiconductor substrate 10 (semiconductor regions 122 and 132). The metal component of the contact plug 501 forming the compound with the semiconductor substrate 10 may be a metal (for example, titanium) contained in the barrier metal of the contact plug 501. The drain 13 includes a low-concentration n-type semiconductor region 131 and a high-concentration n-type semiconductor region 132. The semiconductor region 131 is located below the contact plug 501 and functions as a contact region with which the contact plug 501 contacts. The source 16 includes a low-concentration p-type semiconductor region 161 as an LDD region, a medium-concentration p-type semiconductor region 162, and a metal-containing portion 163. Similarly, the drain 17 includes a low-concentration p-type semiconductor region 171, a medium-concentration p-type semiconductor region 172, and a metal-containing portion 173. The semiconductor regions 161 and 171 are located below the sidewall spacer 48, and the semiconductor regions 162 and 172 are located below the metal-containing portion 173. The contact plug 503 contacts (contacts) the metal-containing portions 163 and 173. The metal-containing portions 163, 173, and 473 are provided in the source 16, drain 17, and gate electrode 47 of the peripheral transistor, but any one of them may be used. Further, the metal-containing portion may be provided in the pixel transistor, but since the generation of noise increases, when the metal-containing portion is provided in the pixel transistor, it is preferable to arrange the metal-containing portion only under the contact plugs 501 and 502.

The metal-containing portions 163, 173, and 473 are regions containing a metal and are made of a metal or a metal compound. The metals contained in the metal-containing portions 163, 173, and 473 are, for example, cobalt (Co), nickel (Ni), titanium (Ti), tantalum (Ta), and tungsten (W). Typically, the metal-containing portions 163, 173, and 473 are portions made of a semiconductor metal compound, and more typically, a silicon metal compound, that is, a portion made of a silicide (silicide portion). As the silicide, cobalt silicside, nickel silicide, tungsten silicide, titanium silicide and the like are suitable. The metal-containing portions 163, 173, and 473 may be a compound of a metal and germanium. The metal-containing portion 473 may be a metal nitride such as tantalum nitride, titanium nitride, or aluminum nitride, or may be a metal carbide. The metal-containing portions 163, 173, and 473 are provided for the purpose of reducing the resistance between the transistor and the contact plugs 503 and 504. The metal-containing portion may be provided for another purpose, for example, to make the gate electrode a metal gate, or may be provided as a light-shielding member for the semiconductor substrate 10. The metal-containing portion is provided so as not to overlap at least the photoelectric conversion unit 11 so that the photoelectric conversion unit 11 can receive light. In this example, since the metal-containing portions 163, 173, and 473 are arranged in the peripheral area PR, the metal-containing portions 163, 173, and 473 do not overlap with the photoelectric conversion unit 11. Even when the metal-containing portion is provided in the pixel area PX, it is preferable that the metal-containing portion is provided so as not to overlap the photoelectric conversion unit 11.

The photoelectric conversion device APR includes a silicon nitride layer 31, a silicon oxide film 21, and a silicon nitride layer 32 arranged on the semiconductor substrate 10. The contact plugs 501 and 502 penetrate the silicon oxide film 21 in addition to the interlayer insulating film 40. The contact plugs 501 and 502 are in contact with the silicon oxide film 21 in addition to the interlayer insulating film 40. Typically, the barrier metal of the contact plugs 501 and 502 is in contact with the interlayer insulating film 40 and the silicon oxide film 21. The contact plugs 503 and 504 penetrate the silicon oxide film 21 and the silicon nitride layer 32 in addition to the interlayer insulating film 40. The contact plugs 503 and 504 are in contact with the silicon oxide film 21 and the silicon nitride layer 32. Typically, the barrier metal of the contact plugs 503 and 504 is in contact with the silicon oxide film 21 and the silicon nitride layer 32.

The silicon nitride layer 31 is arranged on the photoelectric conversion unit 11 so as to have a portion 311 located between the interlayer insulating film 40 and the semiconductor substrate 10. The silicon nitride layer 31 also has a portion 312 arranged between the dielectric region 61 and the photoelectric conversion unit 11. The thickness T312 of the portion 312 of the silicon nitride layer 31 may be smaller than the thickness T311 of the portion 311 of the silicon nitride layer 31 (T312 <T311). The thickness T312 may be 25 to 75% of the thickness T311. The thickness T311 is, for example, 30 to 120 nm, and the thickness T312 is, for example, 10 to 60 nm. When the dielectric region 61 is not provided, the entire silicon nitride layer 31 is located between the interlayer insulating film 40 and the semiconductor substrate 10, and the entire silicon nitride layer 31 has a substantially uniform thickness (thickness). Distribution can have ± 10% or less). In the silicon nitride layer 31 on the photoelectric conversion unit 11, the silicon nitride layer 31 itself functions as a protective layer, and damage and contamination to the photoelectric conversion unit 11 during manufacturing and use of the photoelectric conversion device APR can be reduced.

In order for the silicon nitride layer 31 to improve the optical characteristics with respect to the photoelectric conversion unit 11, it is preferable that the silicon nitride layer 31 is close to the photoelectric conversion unit 11 to some extent. The distance D1 between the silicon nitride layer 31 and the photoelectric conversion unit 11 is preferably smaller than the distance D5 between the semiconductor substrate 10 and the wiring layer 51 (D1 <D5). Further, the distance D1 between the silicon nitride layer 31 and the photoelectric conversion unit 11 is preferably smaller than the length L3 of the contact plug 503 (D1 <L3), and preferably smaller than the length of the contact plug 501. The length of the contact plug 501 may be considered to be equal to the length L3 of the contact plug 503. Further, the distance D1 between the silicon nitride layer 31 and the photoelectric conversion unit 11 is preferably smaller than the length L4 of the contact plug 504 (D1 <L4), and preferably smaller than the length of the contact plug 502. The length of the contact plug 502 may be considered to be equal to the length L4 of the contact plug 504. The distance D5 is substantially equal to the length L3, but the distance D5 may be smaller than the length L3 (D5 ≦ L3).

The silicon oxide film 21 is arranged between the interlayer insulating film 40 and the semiconductor substrate 10. The silicon oxide film 21 has a portion 211 provided in the pixel area PX and a portion 212 provided in the peripheral area PR. The portion 211 is arranged at least between the silicon nitride layer 31 and the photoelectric conversion unit 11. The portion 212 is arranged at least between the interlayer insulating film 40 and the peripheral transistor. The upper surface of the silicon oxide film 21 which is the surface on the interlayer insulating film 40 side (the surface opposite to the surface on the semiconductor substrate 10 side) has irregularities according to the shapes of the gate electrodes 42, 43, and 47. The upper surface of the interlayer insulating film 40, which is the surface opposite to the semiconductor substrate 10 side, is flattened and does not have irregularities according to the shapes of the gate electrodes 42, 43, and 47. Therefore, the upper surface of the interlayer insulating film 40 of the silicon oxide film 21 has a larger height difference than the upper surface of the interlayer insulating film 40. Both the interlayer insulating film 40 and the silicon oxide film 21 can be made of silicon oxide, but by measuring the concentrations of silicon (Si), oxygen (O), argon (Ar), boron (B), phosphorus (P), etc. The interlayer insulating film 40 and the silicon oxide film 21 can be distinguished from each other. The thickness T21 of the silicon oxide film 21 is, for example, 50 to 150 nm. It is better that the difference in thickness between the portion 211 and the portion 212 is small. The silicon oxide film 21 may have a substantially uniform thickness as a whole (thickness distribution is ± 10% or less). When the silicon oxide film 21 has only the portion 211, the contact plugs 503 and 504 do not penetrate the silicon oxide film 21.

A silicon nitride layer 32 is arranged between the silicon oxide film 21 and the peripheral transistor. The silicon nitride layer 32 covers the source 16, the drain 17, the gate electrode 47, and the sidewall spacer 48. The thickness T32 of the silicon nitride layer 32 is, for example, 10 to 100 nm. The silicon nitride layer 32 may be in contact with the source 16, the drain 17, the gate electrode 47, and the sidewall spacer 48. More specifically, the silicon nitride layer 32 may be in contact with the metal-containing portions 163 and 173, the silicon nitride layer 483 and the metal-containing portion 473. Therefore, the distance between the silicon nitride layer 32 and the metal-containing portions 163, 173, 473 can be zero.

By increasing the thickness T311 of the portion 311 of the silicon nitride layer 31, contamination via the interlayer insulating film 40 can be reduced. In particular, it is preferable that the thickness T311 is larger than the thickness T32 of the silicon nitride layer 32. The thickness T311 is preferably 110% or more of the thickness T32, and the thickness T311 may be 150% or more of the thickness T32. The thickness T311 may be 300% or less of the thickness T32, and the thickness T311 may be 150% or less of the thickness T32.

By separating the upper surface of the portion 312 from the semiconductor substrate 10 as much as possible, damage to the photoelectric conversion unit 11 can be reduced. The distance between the upper surface of the portion 312 and the semiconductor substrate 10 is represented by the sum (D1 + T312) of the thickness T312 of the portion 312 and the distance D1 between the portion 312 and the semiconductor substrate 10. The distance between the upper surface of the portion 312 and the semiconductor substrate 10 is preferably larger than the thickness T42 of the gate electrode 42. By providing the silicon oxide film 21, this distance D1 can be increased.

By increasing the thickness T312 as much as possible, contamination through the dielectric region 61 can be reduced. The thickness T312 is preferably 25% or more of the thickness T32, and more preferably 50% or more of the thickness T32. The thickness T312 may be smaller than the thickness T32, and the thickness T312 may be 75% or less of the thickness T32. When the thickness of the silicon nitride layer 31 is 150% or less of the thickness of the silicon nitride layer 32, the thickness T32 can be between the thickness T312 and the thickness T311. If the thickness T311 is sufficiently larger than the thickness T32, the thickness T312 may be larger than the thickness T32.

If the silicon oxide film 21 is present in only one of the portion 211 and the portion 212, a height difference may occur in the base of the interlayer insulating film 40 between the pixel area PX and the peripheral area PR. On the other hand, by providing both the portion 211 and the portion 212, the height of the base of the interlayer insulating film 40 in the pixel area PX and the peripheral area PR is higher or lower than in the case where only one of the portion 211 and the portion 212 is provided. The difference can be reduced. Therefore, the flatness of the upper surface of the interlayer insulating film 40 can be improved, and the light interference unevenness caused by the difference in the optical path length for each pixel can be reduced. Further, the reliability of the contact plugs 501, 502, 503, and 504 can be improved and the reliability of the wiring layer can be improved. The thickness T21 of the silicon oxide film 21 can be made larger than the thickness T311 of the portion 311 of the silicon nitride layer 31 and the thickness T32 of the silicon nitride layer 32 (T21> T311, T32).

The silicon nitride layer 32 can suppress the diffusion of metal from the metal-containing portions 163, 173, and 473. By arranging the silicon nitride layer 32 on the side of the metal-containing portions 163, 173, and 473 with respect to the portion 212 of the silicon oxide film 21, the diffusion of the metal in the metal-containing portions 163, 173, and 473 can be effectively suppressed. It is effective that the distance between the silicon nitride layer 32 and the metal-containing portions 163, 173, and 473 is small, and it is preferable to make this distance zero as described above.

The photoelectric conversion device APR may further include at least one of the silicon oxide layer 22, the silicon nitride layer 33, and the silicon oxide layer 23 arranged on the semiconductor substrate 10. In this example, all three layers are provided, but among these three layers, it is particularly preferable to provide the silicon nitride layer 33. The silicon nitride layer 33 is arranged between the silicon oxide film 21 and the photoelectric conversion unit 11. The silicon oxide layer 22 is arranged between the silicon oxide film 21 and the silicon nitride layer 33. The silicon oxide layer 23 is arranged between the semiconductor substrate 10 and the silicon nitride layer 33. In the pixel area PX, the insulator film 49, which is a multi-layer film including the silicon oxide layer 22, the silicon nitride layer 33, and the silicon oxide layer 23, covers the semiconductor substrate 10 and the gate electrodes 42, 43. The contact plugs 501 and 502 penetrate the silicon oxide layer 22, the silicon nitride layer 33, and the silicon oxide layer 23 in addition to the interlayer insulating film 40. The Kotact plugs 501 and 502 may be in contact with the silicon oxide layer 22, the silicon nitride layer 33, and the silicon oxide layer 23. Typically, the barrier metal of the contact plugs 501 and 502 is in contact with the silicon oxide film 21 and the silicon nitride layer 32.

The silicon nitride layer 33 may have a function of preventing reflection of light incident on the photoelectric conversion unit 11. Further, the silicon nitride layer 33 and the silicon nitride layer 31 are laminated via the silicon oxide film 21 to generate multiple reflections, whereby the antireflection function can be further enhanced. The portion of the silicon nitride layer 33 that covers the semiconductor region other than the photoelectric conversion unit 11 may have a function of protecting the semiconductor substrate 10 from contamination or damage. Since the silicon nitride layer 31 is not provided on the semiconductor region other than the photoelectric conversion unit 11, the silicon nitride layer 33 plays a part of the role played by the silicon nitride layer 31 on the photoelectric conversion unit 11. .. The silicon oxide layer 23 may have a function as a buffer layer for preventing the silicon nitride layer 33 from coming into contact with the semiconductor substrate 10. Since the silicon nitride layer 33 is separated from the semiconductor substrate 10, the generation of dark current can be suppressed. The distance D3 between the silicon nitride layer 33 and the semiconductor substrate 10 is preferably larger than the distance between the silicon nitride layer 32 and the metal-containing portions 163 and 173. In this example, the gate insulating film 24 extends from between the semiconductor substrate 10 and the gate electrodes 42 and 43 onto the semiconductor region not covered by the gate electrodes 42 and 43. Therefore, the distance D3 between the silicon nitride layer 33 and the semiconductor substrate 10 is equal to the sum of the thickness of the silicon oxide layer 23 and the thickness between the gate insulating film 24.

When the dielectric region 61 is made of silicon nitride, the silicon nitride layer 31 and the dielectric region 61 are made of the same material. With such a configuration, reflection at the interface between the silicon nitride layer 31 and the dielectric region 61 is less likely to occur, and the light utilization efficiency is improved.

The silicon oxide layer 23, the silicon nitride layer 33, the silicon oxide layer 22, the silicon oxide film 21, and the silicon nitride layer 31 on the photoelectric conversion unit 11 are antireflection layers for light to be incident on the semiconductor substrate 10. Functions as. The distance D2 between the silicon nitride layer 31 and the silicon nitride layer 33 is important for the performance of the multilayer antireflection layer. This is because multiple reflections occur between the silicon nitride layer 33 and the silicon nitride layer 31, and the reflection is reduced by the interference of the multiple reflected light. In order to control this distance D2, the total thickness of the silicon oxide layer 22 and the silicon oxide film 21 may be controlled. The distance D2 between the silicon nitride layer 31 and the silicon nitride layer 33 is λ / 8n to 4λ / 8n (λ: wavelength of incident light (400 nm ≦ λ ≦ 800 nm), n: refractive index of silicon oxide (n≈1. 5)) is preferable. The distance D2 is, for example, 50 to 150 nm. In order to improve the sensitivity and prevent stray light, the distance L3 should be less than the maximum value of λ, that is, less than 800 nm.

The thickness of the silicon oxide layer 23 is, for example, 5 to 20 nm, the thickness T33 of the silicon nitride layer 33 is, for example, 20 to 100 nm, and the thickness of the silicon oxide layer 22 is, for example, 10 to 100 nm. The thickness of the silicon oxide film 21 is, for example, 20 to 200 nm, and the thickness of the silicon nitride layer 31 is, for example, 20 to 100 nm. The thickness of the silicon oxide film 21 can be made larger than the thickness of the silicon oxide layer 22.

To obtain the effect of improving the performance and reliability of the photoelectric conversion device APR, the more suitable relationships regarding the dimensions and distances of the above-mentioned members such as layers and films can be summarized as follows: D3 <T312 <T32≤T33 <T311 < T21 <D2 <D1 <T42 <L4 <D5 ≦ L3. Further, T21 <100 nm, L4> 200 nm, and L3 <800 nm. It is not necessary to satisfy this relationship for all dimensions and distances, and at least two combinations of dimensions and distances may satisfy the magnitude relationship specified here.

A method of manufacturing the photoelectric conversion device APR will be described with reference to FIGS. 4 to 8. 4 to 8 show the structure of the portion corresponding to the cross-sectional view shown in FIG. 3 in the order of processes, but the order of the processes does not necessarily have to be as shown in FIGS. 4 to 8. In FIGS. 4 to 8, the display of the reference numeral is omitted for the portion that does not need to be changed from the existing portion.

In the step a shown in FIG. 4A, a semiconductor substrate 10 having an element region defined by the element separation region 9 is prepared. The element separation region 9 can be formed by a well-known method having a LOCOS structure or an STI structure. A p-type semiconductor region 112 or an n-type semiconductor region 111 is formed as a well region in the element region of the semiconductor substrate 10.

In the step b shown in FIG. 4B, the gate electrodes 42, 43, and 47 are formed on the semiconductor substrate 10. First, the gate insulating films 24 and 26 are formed on the semiconductor substrate 10, and then a conductor film made of polysilicon or the like is formed on the gate insulating films 24 and 26. By patterning this conductor film, the gate electrodes 42, 43, 47 are formed. Further, the semiconductor regions 113, 121, 131, 14, 131, 171 are formed by ion implantation. The semiconductor region 111 may be formed after the gate electrode 42 is formed.

In the step c shown in FIG. 4 (c), the insulator film 490 is formed so as to cover the photoelectric conversion unit 11. The insulator film 490 is a multilayer layer including a silicon oxide layer 220, a silicon nitride layer 330 between the silicon oxide layer 220 and the semiconductor substrate 10, and a silicon oxide layer 230 between the silicon nitride layer 330 and the semiconductor substrate 10. It is a membrane. The insulator film 490 is formed by laminating a silicon oxide layer 230, a silicon nitride layer 330, and a silicon oxide layer 220 in this order from the semiconductor substrate 10 side. Each layer of the insulator film 490 can be formed by a thermal CVD (Chemical Vapor Deposition) method, for example, an LP (Low Pressure) -CVD method.

In the step d shown in FIG. 4D, the sidewall spacer 48 is formed from the insulator film 490. The sidewall spacer 48 can be formed by masking the insulator film 490 with a resist pattern in the pixel area PX and anisotropically etching the insulator film 490 in the peripheral area PR. The silicon nitride layer 483 of the sidewall spacer 48 is formed from the silicon nitride layer 330 of the insulator film 490, and the silicon oxide layer 482 of the sidewall spacer 48 is formed from the silicon oxide layer 230 of the insulator film 490. The sidewall spacer 48 may include a silicon oxide layer (not shown) formed from the silicon oxide layer 220.

The portion of the insulator film 490 located in the pixel area PX remains as the insulator film 49. The silicon oxide layer 22 of the insulator film 49 is formed from the silicon oxide layer 220 of the insulator film 490. The silicon nitride layer 33 of the insulator film 49 is formed from the silicon nitride layer 330 of the insulator film 490. The silicon oxide layer 23 of the insulator film 49 is formed from the silicon oxide layer 230 of the insulator film 490.

Further, in step d, the sidewall spacer 48 is used as a mask to form a medium-concentration semiconductor region 162 of the source 16 and a medium-concentration semiconductor region 172 of the drain 17.

In the step e shown in FIG. 5 (e), a portion of the insulator film 49 located above the photoelectric conversion unit 11 and a metal film 300 in contact with the semiconductor substrate 10 are formed. The metal film 300 is preferably in contact with the silicon oxide layer 22 of the insulator film 49. In other words, at the stage of forming the metal film 300, it is preferable that the silicon oxide layer 22 remains on the silicon nitride layer 33 of the insulator film 49. The metal film 300 can also contact the gate electrode 47. The metal film 300 is, for example, a cobalt film, a nickel film, a tungsten film, or a titanium film. The metal film 300 can be formed into a film by, for example, a sputtering method so as to cover the semiconductor regions 162 and 172 and the gate electrode 47 in the peripheral area PR.

In the peripheral area PR, it is necessary to expose the semiconductor regions 162 and 172 of the semiconductor substrate 10 and the gate electrode 47. Therefore, the semiconductor regions 162 and 172 and the gate electrode 47 may react with oxygen in the atmosphere to form a natural oxide film on the surface. Alternatively, a part of the insulator film 490 or the gate insulating film 26 may remain on the surfaces of the semiconductor regions 162 and 172 and the gate electrode 47. If a natural oxide film or an insulator film is present between the metal film 300 formed on the metal film 300 and silicon, the reaction due to the heat treatment may be hindered and poor formation of the metal-containing portion may occur. In order to avoid this, the natural oxide film and the insulator film are removed by etching immediately before forming the metal film 300. For etching, for example, wet etching using a chemical solution containing hydrofluoric acid can be used.

With the etching of the natural oxide film and the insulator film, the portion of the insulator film 49 which is the base thereof, which is located on the photoelectric conversion unit 11, may become thin. Specifically, the silicon oxide layer 22 of the insulator film 49 is thinned by etching.

In the step f shown in FIG. 5 (f), the metal-containing portions 163, 173, and 473 are formed on the semiconductor substrate 10 by using the metal film 300. After the metal film 300 is formed, heat treatment is performed so that the metal of the metal film 300 reacts with the silicon (single crystal silicon) of the semiconductor substrate 10 and the silicon (polycrystalline silicon) of the gate electrode 47. As a result, metal-containing portions 163, 173, and 473 made of silicide, which is a compound of metal and silicon, are formed. The metal-containing portions 163, 173, and 473 can be cobalt silicide, nickel silicide, tungsten silicide, or titanium silicide, depending on the metal type of the metal film 300. In the pixel area PX, since the silicon nitride layer 33 and the silicon oxide layer 22 cover the semiconductor substrate 10, silicide is not formed. With such a configuration, the diffusion of metals such as cobalt and nickel is reduced, and it is possible to reduce the leakage current in the photoelectric conversion unit 11 and the noise (so-called white scratches) in the photoelectric conversion unit 11. The metal-containing portion may be provided in any configuration of the pixel area PX, or the metal-containing portion may not be provided in any configuration of the peripheral area PR.

After the metal-containing portions 163, 173, and 473 are formed, the unreacted metal in the metal film 300 is removed by etching.

With the etching of the metal film 300, the portion of the insulator film 49 that is the base thereof, which is located on the photoelectric conversion unit 11, may become thin. Specifically, the silicon oxide layer 22 of the insulator film 49 is thinned by etching.

The residue of the silicon oxide layer 220 remaining on the sidewall spacer 48 formed in step d can be removed by etching the natural oxide film or the insulator film described above, or etching the metal film 300.

In the step g shown in FIG. 5 (g), the silicon nitride film 320 is formed so as to cover the metal-containing portions 163, 173, and 473 on the semiconductor substrate 10. The silicon nitride film 320 is formed over the pixel area PX and the peripheral area PR, and can be formed by, for example, a plasma CVD method.

In the step h shown in FIG. 5 (h), the silicon nitride film 320 is removed on the photoelectric conversion unit 11. The portion of the silicon nitride film 320 located above the peripheral transistor remains as the silicon nitride layer 32.

With the etching of the silicon nitride film 320, the portion of the insulator film 49 that is the base thereof, which is located on the photoelectric conversion unit 11, may become thin. Specifically, the silicon oxide layer 22 of the insulator film 49 is thinned by etching.

In the step i shown in FIG. 6 (i), the silicon oxide film 21 is formed on the silicon nitride film 320 (silicon nitride layer 32) so as to cover the photoelectric conversion unit 11 provided on the semiconductor substrate 10. The silicon oxide film 21 is formed over the pixel area PX and the peripheral area PR, and can be formed by, for example, a plasma CVD method.

As described above, on the photoelectric conversion unit 11, the distance between the silicon nitride layer 31 and the semiconductor substrate 10 and the distance between the silicon nitride layer 31 and the silicon nitride layer 33 affect the reflectance. .. In the present embodiment, the optical characteristics can be optimized by forming the silicon oxide film 21 with an appropriate thickness. Further, the thickness of the silicon oxide film 21 can be set according to the thickness of the silicon oxide layer 22 thinned in some steps. The amount of decrease in the thickness of the silicon oxide layer 22 can be grasped in advance, and the thickness of the silicon oxide film 21 can be determined according to the amount of decrease. Alternatively, the thickness of the silicon oxide layer 22 may be measured at the time of manufacture, and the thickness of the silicon oxide film 21 may be determined according to the measurement result. For example, it is extremely effective to form the silicon oxide film 21 when the thickness of the silicon oxide film 21 needs to be larger than the thickness of the finally remaining silicon oxide layer 22. The thickness of the reduced-thickness silicon oxide layer 22 is, for example, 10 to 100 nm, and the thickness of the silicon oxide film 21 is, for example, 20 to 200 nm.

In the step j shown in FIG. 6J, the silicon nitride film 310 is formed on the silicon oxide film 21 so as to cover the photoelectric conversion unit 11 provided on the semiconductor substrate 10. The silicon nitride film 310 is formed over the pixel area PX and the peripheral area PR, and can be formed by, for example, a plasma CVD method. The thickness of the silicon nitride film 310 is preferably thicker than that of the silicon nitride film 320 (silicon nitride layer 32).

In the step k shown in FIG. 6 (k), the silicon nitride film 310 is removed on the pixel transistor. The portion of the silicon nitride film 310 located above the photoelectric conversion unit 11 remains as the silicon nitride layer 31. The silicon nitride film 310 can be patterned on the silicon nitride layer 31 having a desired shape by a lithography technique and an etching technique. The silicon nitride layer 31 is provided so as to extend from the n-type semiconductor region 111, that is, from the photoelectric conversion unit 11, onto a part of the gate electrodes 42 of the transfer gates TX1 and TX2. The upper surface of the silicon nitride layer 31 has a shape that follows the height difference due to the gate electrode 42. In the region where the contact plugs 501 and 502 of the pixel area PX are arranged, it is preferable to remove the silicon nitride film 310 by etching.

In the step l shown in FIG. 6 (l), the interlayer insulating film 40 is formed. The interlayer insulating film 40 is a portion of the silicon nitride film 320 located above the transistor including the electrode (silicon nitride layer 32) and a portion of the silicon nitride film 310 located above the photoelectric conversion unit 11 (nitriding). It is formed so as to cover the silicon layer 31). The interlayer insulating film 40 is flattened by using a flattening method such as a reflow method, an etchback method, or a CMP method.

In the step m shown in FIG. 7 (m), contact holes 401 and 402 located above the pixel transistors are formed in the interlayer insulating film 40, the silicon oxide film 21, and the insulator film 49. The contact holes 401 and 402 are holes provided in at least the interlayer insulating film 40.

In order to form the contact holes 401 and 402 of the pixel area PX, the interlayer insulating film 40, the silicon oxide film 21, the silicon oxide layer 22, the silicon nitride layer 33, and the silicon oxide layer 23 are sequentially etched by plasma etching. At this time, the silicon nitride layer 33 can function as an etching stopper. More specifically, the etching conditions for etching the silicon oxide layer 22 are that the etching rate for the silicon nitride layer 33 is lower than the etching rate for the silicon oxide layer 22. If the pixel area PX does not have the silicon oxide layer 22, the silicon oxide layer 22 may be replaced with the silicon oxide film 21.

The silicon nitride layer 33 as an etching stopper cancels the variation in the depths of the contact holes 401 and 402 when etching up to the upper layer of the silicon nitride layer 33. Then, damage to the semiconductor substrate 10 can be suppressed by etching the thin silicon nitride layer 33 in the vicinity of the semiconductor substrate 10 in a state where the variation in the depths of the contact holes 401 and 402 is reduced. It is preferable that the silicon nitride layer 33 is brought close to the semiconductor substrate 10, but since noise is likely to occur when the silicon nitride layer 33 comes into contact with the semiconductor substrate 10, the silicon oxide layer 23 is placed between the silicon nitride layer 33 and the semiconductor substrate 10. It is arranged.

When the step h is not performed, the silicon nitride film 320 is arranged on the pixel transistor. Then, in order to form the contact holes 401 and 402, the interlayer insulating film 40, the silicon oxide film 21, the silicon nitride film 320, the silicon oxide layer 22, the silicon nitride layer 33, and the silicon oxide layer 23 are etched in this order. In this case, the presence of the silicon nitride film 320 complicates the switching of etching conditions and the etching stop conditions, and the yield may decrease. On the other hand, by removing the silicon nitride film 320 on the pixel transistor in the step h, the number of times of switching the conditions for etching the silicon nitride layer can be reduced (it can be made once). Therefore, the contact holes 401 and 402 can be easily formed, the variation is reduced, and the yield is improved.

Similarly, when the step k is not performed, the silicon nitride film 310 is arranged on the pixel transistor. Then, in order to form the contact holes 401 and 402, the interlayer insulating film 40, the silicon nitride film 310, the silicon oxide film 21, the silicon oxide layer 22, the silicon nitride layer 33, and the silicon oxide layer 23 are etched in this order. In this case, the presence of the silicon nitride film 310 complicates the switching of etching conditions and the etching stop conditions, and the yield may decrease. On the other hand, by removing the silicon nitride film 310 on the pixel transistor in step k, the number of switching conditions for etching the silicon nitride layer 31 can be reduced (it can be made once). Therefore, the contact holes 401 and 402 can be easily formed, the variation is reduced, and the yield is improved.

By implanting ions into the semiconductor substrate 10 through the contact hole 401, the semiconductor regions 122 and 132 as contact regions are formed. By closing the contact hole 401 with a resist mask when forming the semiconductor regions 122 and 132, it is possible to suppress the injection of impurities into the channel region through the gate electrodes 42 and 43.

In the step n shown in FIG. 7 (n), contact holes 403 and 404 located above the peripheral transistors are formed in the interlayer insulating film 40, the silicon oxide film 21, and the silicon nitride film 320 (silicon nitride layer 32). The contact holes 403 and 404 are holes provided in at least the interlayer insulating film 40.

In order to form the contact holes 403 and 404 of the peripheral area PR, the interlayer insulating film 40, the silicon oxide film 21 and the silicon nitride layer 32 are sequentially etched by plasma etching. At this time, the silicon nitride layer 32 can function as an etching stopper. More specifically, the etching conditions for etching the silicon oxide film 21 are that the etching rate for the silicon nitride layer 32 is lower than the etching rate for the silicon oxide film 21. If the silicon oxide film 21 is not present in the peripheral area PR, the silicon oxide film 21 may be replaced with the interlayer insulating film 40.

The silicon nitride layer 32 as an etching stopper cancels the variation in the depths of the contact holes 403 and 404 when etching up to the upper layer of the silicon nitride layer 32. Then, the thin silicon nitride layer 32 close to the semiconductor substrate 10 is etched in a state where the variation in the depths of the contact holes 403 and 404 is reduced. As a result, damage to the semiconductor substrate 10 and scattering of metal from the metal-containing portions 163, 173, and 473 can be suppressed. Therefore, it is preferable that the silicon nitride layer 32 is as close as possible to the metal-containing portions 163, 173, 473, and it is preferable that the silicon nitride layer 32 is in contact with the metal-containing portions 163, 173, 473. Further, the silicon nitride layer 32 should be as thin as possible.

When the step k is not performed, the silicon nitride film 310 is arranged on the peripheral transistor. Then, in order to form the contact holes 403 and 404, the interlayer insulating film 40, the silicon nitride film 310, the silicon oxide film 21, and the silicon nitride layer 32 are etched in this order. In this case, the presence of the silicon nitride film 310 complicates the switching of etching conditions and the etching stop conditions, and the yield may decrease. On the other hand, by removing the silicon nitride film 310 on the peripheral transistor in the step k, the number of times of switching the conditions for etching the silicon nitride layer can be reduced (it can be made once). Therefore, the contact holes 403 and 404 can be easily formed, the variation is reduced, and the yield is improved.

In the step o shown in FIG. 7 (o), the conductor is arranged in the contact holes 401, 402, 403, 404. The conductor can be a laminate of barrier metal and tungsten. The excess conductor on the interlayer insulating film 40 is removed by a CMP method or the like to form contact plugs 501, 502, 503, 504.

It is preferable to separately form the contact holes 401 and 402 and the contact holes 403 and 404 as in steps m and n. Metal-containing portions 163, 173, 473 are formed in at least a part of the peripheral area PR, and the contact holes 403, 404 expose the metal-containing portions 163, 173, 473. In such a case, the metal in the metal-containing portions 163, 173, and 473 may be scattered by etching at the time of forming the contact holes 403 and 404 in the peripheral area PR. Therefore, when forming the contact holes 403 and 404, whether the contact holes 401 and 402 have not been formed yet, are covered with a resist mask, or are already closed with contact plugs 501 and 502. It is preferable to set it to either state. In this example, the contact holes 401 and 402 are formed before the contact holes 403 and 404 are formed, and the contact holes 403 and 404 are formed with the contact holes 401 and 402 blocked by a resist mask. The resist mask can prevent the metal of the metal-containing portions 163, 173, and 473 from entering the contact holes 401 and 402.

If the influence of the metal scattering of the metal-containing portions 163, 173, and 473 is small, the contact holes 401 and 402 and the contact holes 403 and 404 may be formed at the same time. In that case, it is preferable that the difference in thickness between the silicon nitride layer 33 and the silicon nitride layer 32 is small. For example, the difference in thickness between the silicon nitride layer 33 and the silicon nitride layer 32 is preferably 10 nm or less. If they are equivalent, the contact holes 401 and 402 of the pixel area PX and the contact holes 403 and 404 of the peripheral area PR can be formed at the same time. However, even if the difference in thickness between the silicon nitride layer 33 and the silicon nitride layer 32 is 10 nm or less, it is preferable to use separate steps such as steps m and n. In particular, when the distance between the silicon nitride layer 33 and the semiconductor substrate 10 is different from the distance between the silicon nitride layer 32 and the metal-containing parts 163 and 173, it is preferable to use separate steps such as steps m and n. ..

The order of the step m and the step n may be reversed. Further, in this example, the step o is performed after the step m and the step n. For example, after the conductor is arranged in the contact holes 401 and 402 to form the contact plugs 501 and 502, the contact holes 403 and 404 are formed. May be formed. The contact holes 401 and 402 may be formed after the conductors are arranged in the contact holes 403 and 404 to form the contact plugs 503 and 504.

In the next step, as shown in FIG. 8 (p1) corresponding to FIG. 2 (b), the interlayer insulating film 50 and the plurality of wiring layers 51, 52, 53 are formed on the interlayer insulating film 40. The wiring layers 51, 52, and 53 are copper layers, the wiring layer 51 can be formed by the single damascene method, and the wiring layers 52, 53 can be formed by the dual damascene method. The interlayer insulating layer 56 is a silicon oxide layer having a thickness of 100 nm to 1000 nm, and the diffusion prevention layer 57 is a silicon carbide layer having a thickness of 10 to 100 nm. The interlayer insulating layer 56 and the diffusion prevention layer 57 can be formed by a plasma CVD method. The interlayer insulating layer 56 can be formed by a plasma CVD method using a silane-based gas as a raw material gas.

In the step p shown in FIG. 8 (p1) corresponding to FIG. 2 (b) and FIG. 3 (p2), a resist pattern having an opening corresponding to the photoelectric conversion unit 11 is formed on the interlayer insulating film 50. Form. Then, the interlayer insulating film 50 is etched using this resist pattern as a mask. Further, the interlayer insulating film 40 is etched to form an opening 406 in which the silicon nitride film 310 (silicon nitride layer 31) forms a bottom. When etching the interlayer insulating film 40, the silicon nitride layer 31 can function as an etching stopper. More specifically, the etching condition for etching the interlayer insulating film 40 is that the etching rate for the silicon nitride layer 31 is lower than the etching rate for the interlayer insulating film 40.

The silicon nitride layer 31 can be etched by etching during the formation of the opening 406. By etching the portion of the silicon nitride layer 31 below the opening 406, the thickness is reduced from the thickness T311 to the thickness T312. As a result, the portion 311 and the portion 312 are formed. The thickness T311 of the thickness T312 may be 25 to 75%. By making the silicon nitride layer 31 sufficiently thick, it is possible to reduce the possibility that the opening 406 penetrates the silicon nitride layer 31 when the opening 406 is formed. Further, the silicon nitride layer 31 may have a function of reducing plasma damage to the photoelectric conversion unit 11 at the time of etching for forming the opening 406. The effect of the silicon nitride layer 31 to reduce plasma damage when the opening 406 is formed also works effectively by making the silicon nitride layer 31 sufficiently thick.

In the step q shown in FIG. 8 (q1) corresponding to FIG. 2 (b) and FIG. 8 (q2) corresponding to FIG. 3, the dielectric region is formed by arranging the dielectric in the opening 406 as shown in FIG. The dielectric member 60 including 61 is formed. By arranging a dielectric having a higher refractive index than the plurality of interlayer insulating layers 56, for example, silicon nitride in the opening 406, an optical wave guide in which the dielectric region 61 becomes a core and the plurality of interlayer insulating layers 56 are clads is configured. To. The dielectric arranged in the opening 406 does not have to have a higher refractive index than the plurality of interlayer insulating layers 56, and may be, for example, silicon oxide. Even if the thickness of the silicon nitride layer 31 changes due to etching when the opening 406 is formed in the interlayer insulating film 40, if silicon nitride is used for the dielectric region 61, the interface between the silicon nitride layer 31 and the dielectric region 61 is used. The effect of the position on the optical characteristics is reduced.

A detailed example of a method for forming the dielectric member 60 will be described. First, the opening 406 is embedded using silicon nitride having a higher refractive index than silicon oxide, which is the main material constituting the plurality of interlayer insulating layers 56. Specifically, silicon nitride is deposited on the entire surface of the semiconductor substrate 10 by the HDP (High Density Plasma) -CVD method, and the silicon nitride is embedded in the opening 406. The silicon nitride layer 31 may have a function of reducing plasma damage to the photoelectric conversion unit 11 even when a dielectric is deposited by the plasma CVD method. The effect of reducing plasma damage when the dielectric is embedded in the opening 406 also works effectively by making the silicon nitride layer 31 sufficiently thick. Then, the excess silicon nitride formed in the peripheral area PR is removed by plasma etching. Further, the silicon nitride on the interlayer insulating film 50 outside the opening 406 is flattened by a CMP (Chemical Mechanical Polishing) method. At this time, all the silicon nitride arranged on the interlayer insulating film 50 is not removed, but is left as the dielectric film 62. The dielectric film 62 is a layer having a thickness of, for example, 100 nm to 500 nm, which extends from the top of the dielectric region 61 to the upper surface of the interlayer insulating film 50. This is to suppress damage to the wiring layer.

Next, in the peripheral area PR, the dielectric film 62 is removed by etching. Since the dielectric film 62 made of silicon nitride has a high residual stress, it is possible to reduce the warp of the semiconductor substrate 10 and the peeling of the dielectric film 62 and the interlayer insulating film 50 by reducing the area of the dielectric film 62.

In the next step r, as shown in FIG. 2B, the interlayer insulating film 70 is formed so as to cover the dielectric film 62. The interlayer insulating film 70 is made of, for example, silicon oxide, and can be formed by a plasma CVD method using silane as a raw material gas.

In the next step s, as shown in FIG. 2B, a via hole is formed in the interlayer insulating film 70 in the peripheral area PR. Since the dielectric film 62 is removed from the peripheral area PR, it becomes easy to form a via hole that penetrates the interlayer insulating film 70 and the interlayer insulating film 50 and reaches the wiring layer 53. A via plug 54 is formed in the via hole. The wiring layer 55 is formed on the interlayer insulating film 70. The wiring layer 55 can be made of an aluminum layer and can be patterned so as to include a pad electrode and a light-shielding pattern.

In the next step t, as shown in FIG. 2B, a silicon nitride film is formed by a plasma CVD method, and the silicon nitride film is processed so as to have an in-layer lens 81 to form an inorganic material film 80. Form.

In the next step u, as shown in FIG. 2B, an organic material film 90 composed of a flattening layer 91, a color filter layer 92, a flattening layer 93, and a microlens layer 94 is formed on the inorganic material film 80. do.

In the next step v, the wafer is diced and divided into a plurality of semiconductor device ICs.

In the next step w, the semiconductor device IC is mounted on the package PKG.

By the above steps, the photoelectric conversion device APR can be manufactured.

It is advantageous for improving reliability that the silicon oxide film 21 has a portion 211 in the pixel area PX and a portion 212 in the peripheral area PR. This is because the silicon oxide film 21 has the portion 211 and the portion 212 to reduce the difference between the pixel area PX and the peripheral area PR in the height of the structure formed on the semiconductor substrate 10. The structure formed on the semiconductor substrate 10 includes gate electrodes 42, 43, silicon nitride layers 31, 32, 33, and the like. In the pixel area PX, in addition to the silicon oxide layer 22, the silicon oxide film 21, and the like, there is a silicon nitride layer 31, and the total height is larger than that of the silicon nitride layer 32 and the like in the peripheral area PR. This height difference is followed by the height difference of the upper surface of the interlayer insulating film 40 formed on the structure. The interlayer insulating film 40 is flattened by the CMP method. At this time, if the height difference of the upper surface of the interlayer insulating film 40 is large, the height difference cannot be eliminated, and a portion having a large distance from the semiconductor substrate 10 and a portion having a small distance are likely to occur on the upper surface of the interlayer insulating film 40. That is, even after the interlayer insulating film 40 is flattened, the interlayer insulating film 40 may be high in the pixel area PX having a high structure height, and the interlayer insulating film 40 may be low in the low peripheral area PR. Further, also in the pixel area PX, the interlayer insulating film 40 may become lower as it is closer to the peripheral area PR. In such a shape, there is a difference in the thickness to be etched in the etching when forming the contact holes 401, 402, 403, 404. Therefore, there is a possibility that an opening defect may occur or etching damage may be given to the semiconductor substrate 10. In this case, there is a concern that the contact plug may be short-circuited or the image quality may be deteriorated. Further, in the step of removing the metal material when the contact plugs 501, 502, 503, 504 and the wiring layer 51 are formed by the damascene method, the metal may remain in an unintended portion. In this case, there is a concern that the contact plug or wiring may be short-circuited.

In the manufacturing method described above, step j (and step k) can also be performed after step g (and step h). Then, the silicon nitride layer 31 (silicon nitride film 310) can be made thicker than the silicon nitride layer 32 (silicon nitride film 320). However, it is preferable that the silicon nitride layer 31 (silicon nitride film 310) is separated from the photoelectric conversion unit 11 and the silicon nitride layer 32 (silicon nitride film 320) is brought close to the metal-containing portions 163, 173, and 473. Therefore, it is preferable to perform the step g and the step h after the step j and the step k.

At least one of step h, step i, and step k can be omitted. However, in order to facilitate the formation of contact holes as described above, it is preferable to perform steps h and k to eliminate duplication of the silicon nitride film. Further, in order to separate the silicon nitride layer 31 (silicon nitride film 310) from the photoelectric conversion unit 11, it is preferable to perform step i to form the silicon oxide film 21. Step i is also preferable in adjusting the distance between the silicon nitride layer 31 and the silicon nitride layer 33 of the photoelectric conversion unit 11 to optimize the optical characteristics.

The silicon nitride film 320 to be the silicon nitride layer 32 may be different in thickness, composition, film quality, film formation method and / or film formation conditions from the silicon nitride film 310 to be the silicon nitride layer 31.

As described above, the silicon nitride layer 31 is preferably thick, and the silicon nitride layer 32 is preferably thin. In the present embodiment, since the silicon nitride film 310 and the silicon nitride film 320 are formed by separate steps g and j, it is easy to optimize the thickness. The difference in thickness between the silicon nitride film 320 and the silicon nitride film 310 is preferably 5 nm or more. The thickness of both can be 10 to 100 nm, and the difference in thickness between the silicon nitride film 320 and the silicon nitride film 310 may be 50 nm or less.

The silicon nitride film 310 and the silicon nitride film 320 may have different compositions. For example, the composition ratio of silicon (Si) and nitrogen (N) may be different, or the concentrations of elements other than silicon (Si) and nitrogen (N), such as argon (Ar) and chlorine (Cl), are different. May be good.

The silicon nitride film 310 and the silicon nitride film 320 may have different film qualities. The residual stress may be different between the silicon nitride film 310 (silicon nitride layer 31) and the silicon nitride film 320 (silicon nitride layer 32). The residual stress of the silicon nitride film 310 (silicon nitride layer 31) is preferably smaller than the residual stress of the silicon nitride film 320 (silicon nitride layer 32). The effect of residual stress will be described. The silicon nitride layer 32 can apply compression or tensile stress to the channel region of the semiconductor substrate 10 to cause strain in the silicon crystal and improve the mobility of carriers passing therethrough. By improving the mobility of the majority carriers of the transistor, the drive capacity is improved. Whether it is compression or tension, and the magnitude of the stress thereof can be arbitrarily selected depending on the desired effect. The silicon nitride layer 32 can also improve the driving ability of the transistor. In the pixel area PX, there is a concern that the film may peel off in the case of a film having a large compression or tensile residual stress of the silicon nitride film 310 due to the problem of adhesion to the silicon oxide layer 22. Therefore, in this embodiment, it is preferable that at least a part of the silicon nitride film 310 in the pixel area PX is removed. For the same reason, it is preferable that the residual stress of the silicon nitride layer 31 formed in the pixel area PX is small. That is, it is preferable that the silicon nitride layer 32 and the silicon nitride layer 31 have different residual stresses. The silicon nitride layer 32 and the silicon nitride layer 31 are formed in different steps under different conditions. Therefore, the residual stress can be individually selected, and films having different residual stress can be formed. The silicon nitride layer 32 and the silicon nitride layer 31 are both insulating films made of silicon nitride, and are deposited by, for example, a plasma CVD method. By adjusting parameters such as plasma temperature and pressure, it is possible to control the residual stress of the deposited film. Further, the residual stress of the silicon nitride layer 32 can be changed by adding a heat treatment step. In this case, since it is necessary to heat-treat only the silicon nitride layer 32, the heat treatment may be performed before depositing the silicon nitride film 310. Since the residual stress differs between the silicon nitride layer 32 and the silicon nitride layer 31, it is possible to improve the driving ability of the transistor and suppress the film peeling at the same time. From this, the performance of the photoelectric conversion device APR can be improved.

The film forming method of the silicon nitride film 310 and the silicon nitride film 320 may be different. For example, the silicon nitride film 320 may be formed by a thermal CVD method, and the silicon nitride film 310 may be formed by a plasma CVD method. One of the silicon nitride film 310 and the silicon nitride film 320 is formed using DCS (dichlorosilane) as a raw material gas, and the other of the silicon nitride film 310 and the silicon nitride film 320 is formed using HCD (hexachlorodisilane) as a raw material gas. You may.

The film forming conditions of the silicon nitride film 310 and the silicon nitride film 320 may be different. The plasma power, gas flow rate, gas pressure, and film formation temperature of one of the silicon nitride film 310 and the silicon nitride film 320 may be different from those of the other of the silicon nitride film 310 and the silicon nitride film 320.

(Second Embodiment)
FIG. 9 is a schematic cross-sectional view of the photoelectric conversion device APR according to the second embodiment. FIG. 9 is a cross section of a portion corresponding to the schematic cross-sectional view of FIG. In FIG. 9, the wiring layer 51 shown in FIG. 3 is omitted.

In the present embodiment, similarly to the silicon nitride layer 31 in the pixel area PX, the silicon nitride layer 34 is arranged between the interlayer insulating film 40 and the silicon oxide film 21 in the peripheral area PR. The contact plugs 503 and 504 do not penetrate the silicon nitride layer 34, and an interlayer insulating film 40 is interposed between the contact plugs 503 and 504 and the silicon nitride layer 34. By arranging the silicon nitride layer 34, it is possible to reduce the height difference of the base of the interlayer insulating film 40 due to the thickness of the silicon nitride layer 31. Further, it is possible to reduce the height difference of the base of the interlayer insulating film 40 due to the fact that the silicon nitride layer 31 is thicker than the silicon nitride layer 32. Further, it is possible to reduce the height difference of the base of the interlayer insulating film 40 due to the thickness of the insulating film 49.

The present embodiment differs in the patterning of the silicon nitride film 310 in step j of the manufacturing method of the first embodiment. In the first embodiment, after the silicon nitride film 310 is formed, the silicon nitride film 310 in the peripheral area PR is removed by etching, but in the present embodiment, the silicon nitride film 310 is left in at least a part of the peripheral area PR. .. When the silicon nitride film 310 is patterned, the portion of the silicon nitride film 310 at an arbitrary position of the peripheral area PR is patterned so as to remain as the silicon nitride layer 34. That is, a part of the silicon nitride film 310 is located between the silicon nitride film 320 and the interlayer insulating film 40. The thickness of the silicon nitride layer 34 is equivalent to the thickness of the silicon nitride layer 31, and is 95 to 105% of the thickness of the silicon nitride layer 31 even if an error is taken into consideration.

In the present embodiment, the reliability of the photoelectric conversion device APR can be improved for the same reason that the silicon oxide film 21 has the portion 211 in the pixel area PX and the portion 212 in the peripheral area PR in the first embodiment. .. That is, under the interlayer insulating film 40, the height difference between the pixel area PX and the peripheral area PR due to at least the thickness of the silicon nitride film 310 can be reduced, and the flatness of the upper surface of the interlayer insulating film 40 can be improved. Is.

Here, the position of the silicon nitride layer 34 is preferably a position avoiding the position where the contact plugs 501, 502, 503, and 504 are formed in a later step. In other words, the silicon nitride layer 34 is provided apart from the contact plugs 501, 502, 503, 504. For that purpose, the silicon nitride film 310 may be patterned so that the silicon nitride layer 34 has an opening corresponding to the contact plugs 503 and 504. This is because, as described in steps n and m, when the contact holes 401, 402, 403, and 404 are formed, if the silicon nitride film 310 is etched, it is difficult to switch the etching conditions or set the etching stop conditions. This is because it becomes. As described above, according to the present embodiment, by leaving at least a part of the silicon nitride film 310 in the peripheral area PR, it is possible to suppress the occurrence of defects and suppress the deterioration of image quality. ..

(Third Embodiment)
FIG. 10 is a schematic cross-sectional view of the photoelectric conversion device APR according to the third embodiment. FIG. 10 is a cross section of a portion corresponding to the schematic cross-sectional view of FIG. In FIG. 9, the wiring layer 51 shown in FIG. 3 is omitted.

In the present embodiment, in the pixel area PX, the semiconductor substrate 10 is provided with a charge holding unit 18 for holding the charges generated by the photoelectric conversion unit 11. The charge generated by the photoelectric conversion unit 11 is transferred to the charge holding unit 18 by the transfer gate including the gate electrode 41. The charge held by the charge holding unit 18 is transferred to the charge detection unit 12 by a transfer gate including the gate electrode 42. Since the thickness of the gate electrode 41 may be considered to be equal to the thickness of the gate electrode 42, the thickness of the gate electrode 41 is shown as T42. The charge holding unit 18 includes an n-type semiconductor region 181 as a charge holding region, a p-type semiconductor region 182 as a well region, and a p-type semiconductor region 183 between the semiconductor region 181 and the surface of the semiconductor substrate 10. And include.

The photoelectric conversion device APR of the present embodiment further includes a light-shielding film 58 that covers the charge-holding portion 18 between the silicon oxide film 21 and the charge-holding portion 18. The light-shielding film 58 has an opening 580 above the photoelectric conversion unit 11, and the photoelectric conversion unit 11 receives light through the opening 580. In other words, the light-shielding film 58 does not overlap the portion of the photoelectric conversion unit 11 below the opening 580. The global electronic shutter function can be realized by providing the charge holding portion 18 shielded by the light-shielding film 58. In this example, the light-shielding film 58 overlaps a part of the photoelectric conversion unit 11 in order to enhance the light-shielding property to the charge holding unit 18.

A height difference may occur between the pixel area PX and the peripheral area PR by the thickness of the light-shielding film 58. The silicon oxide film 21 has a portion 213 located between the interlayer insulating film 40 and the light-shielding film 58. By locating the portion 212 of the silicon oxide film 21 in the peripheral area PR, the height difference due to the thickness of the light-shielding film 58 can be reduced. A silicon oxide film 25 is provided between the light-shielding film 58 and the silicon oxide layer 22. The portion 253 of the silicon oxide film 25 located below the light-shielding film 58 may have a function of flattening by the gate electrodes 41 and 42 to alleviate the height difference of the base of the light-shielding film 58. The silicon oxide film 25 has a portion 252 located between the silicon oxide film 21 and the silicon nitride layer 32.

Although not shown, the light-shielding film 58 is a metal-containing member, and a contact plug in contact with the light-shielding film 58 can be formed in a contact hole penetrating the interlayer insulating film 40 and the silicon oxide film 21. In that case, it is preferable to provide a silicon nitride layer between the interlayer insulating film 40 and the silicon oxide film 21 as an etching stopper for the contact hole and for preventing the diffusion of the metal of the light-shielding film 58.

(About equipment equipped with a photoelectric conversion device)
The device EQP shown in FIG. 1 (a) will be described in detail. The photoelectric conversion device APR may include a package PKG containing the semiconductor device IC in addition to the semiconductor device IC having the semiconductor substrate 10. The package PKG is a bonding wire or bump that connects a substrate on which a semiconductor device IC is fixed, a lid such as glass facing the semiconductor device IC, and a terminal provided on the substrate and a terminal provided on the semiconductor device IC. And the like, and may include.

The equipment EQP may further include at least one of an optical system OPT, a control device CTRL, a processing device PRCS, a display device DSPL, and a storage device MMRY. The optical system OPT forms an image on the photoelectric conversion device APR, and is, for example, a lens, a shutter, or a mirror. The control device CTRL controls the photoelectric conversion device APR, and is a semiconductor device such as an ASIC. The processing device PRCS processes the signal output from the photoelectric conversion device APR, and is a semiconductor device such as a CPU or an ASIC for forming an AFE (analog front end) or a DFE (digital front end). The display device DSPL is an EL display device or a liquid crystal display device that displays information (images) obtained by the photoelectric conversion device APR. The storage device MMRY is a magnetic device or a semiconductor device that stores information (images) obtained by the photoelectric conversion device APR. The storage device MMRY is a volatile memory such as SRAM or DRAM, or a non-volatile memory such as a flash memory or a hard disk drive. The mechanical device MCHN has a moving part or a propulsion part such as a motor or an engine. In the device EQP, the signal output from the photoelectric conversion device APR is displayed on the display device DSPL, or transmitted to the outside by a communication device (not shown) included in the device EQP. Therefore, it is preferable that the device EQP further includes a storage device MMRY and a processing device PRCS in addition to the storage circuit unit and the arithmetic circuit unit of the photoelectric conversion device APR.

The device EQP shown in FIG. 1 (a) can be an electronic device such as an information terminal (for example, a smartphone or a wearable terminal) or a camera (for example, an interchangeable lens camera, a compact camera, a video camera, a surveillance camera) having a shooting function. .. The mechanical device MCHN in the camera can drive the components of the optical system OPT for zooming, focusing, and shutter operation. Further, the device EQP may be a transportation device (mobile body) such as a vehicle, a ship, or a flying object. The mechanical device MCHN in the transportation equipment can be used as a mobile device. The equipment EQP as a transportation device is suitable for transporting a photoelectric conversion device APR and for assisting and / or automating operation (maneuvering) by a photographing function. The processing device PRCS for assisting and / or automating the operation (maneuvering) can perform processing for operating the mechanical device MCNH as a mobile device based on the information obtained by the photoelectric conversion device APR.

If the photoelectric conversion device APR according to the present embodiment is used, high performance can be achieved. Therefore, when the photoelectric conversion device APR is mounted on the transportation device to take an image of the outside of the transportation device or measure the external environment, excellent image quality and measurement accuracy can be obtained. It can also be reliable enough to be mounted on equipment used in harsh environments such as transportation equipment. Therefore, in manufacturing and selling the transportation equipment, it is advantageous to decide to mount the photoelectric conversion device APR of the present embodiment on the transportation equipment in order to improve the performance of the transportation equipment.

The embodiments described above can be appropriately changed as long as they do not deviate from the technical idea. It should be noted that the disclosure content of the embodiment includes not only what is specified in the present specification but also all matters that can be grasped from the present specification and the drawings attached to the present specification.

10 Semiconductor substrate 11 Photoelectric conversion part 40 Interlayer insulating film 163, 173 Metal-containing part 47 Gate electrode 48 Sidewall spacer 31 Silicon nitride layer 310 Silicon nitride film 32 Silicon nitride layer 320 Silicon nitride film 21 Silicon oxide film 503 Contact plug

Claims (10)

It is a photoelectric conversion device
A semiconductor substrate having a photoelectric conversion unit and
The silicide portion provided on the semiconductor substrate and
An interlayer insulating film arranged on the semiconductor substrate so as to cover the silicide portion, and
A dielectric region arranged on the photoelectric conversion unit so as to be surrounded by the interlayer insulating film,
A light-shielding film having a portion located between the interlayer insulating film and the semiconductor substrate,
A contact plug that comes into contact with the interlayer insulating film and the silicide portion,
A first silicon nitride layer arranged between the interlayer insulating film and the photoelectric conversion unit,
A silicon oxide film having a portion arranged between the first silicon nitride layer and the photoelectric conversion portion and a portion arranged between the interlayer insulating film and the silicide portion.
A second silicon nitride layer arranged between the silicon oxide film and the silicide portion,
A photoelectric conversion device characterized by being provided with. It has an electrode arranged on the semiconductor substrate and has an electrode.
The photoelectric conversion device according to claim 1, wherein the silicide portion is arranged on the electrode. It has a sidewall spacer that covers the side surface of the electrode.
The photoelectric conversion device according to claim 2, wherein the second silicon nitride layer is arranged between the silicon oxide film and the sidewall spacer. It has an impurity region provided in the semiconductor substrate and has an impurity region.
The photoelectric conversion device according to any one of claims 1 to 3, wherein the silicide portion is arranged on the impurity region. The photoelectric conversion device according to any one of claims 1 to 4, wherein the dielectric region contains silicon nitride. The photoelectric conversion device according to any one of claims 1 to 5, wherein the thickness of the first silicon nitride layer is larger than the thickness of the second silicon nitride layer. The semiconductor substrate has a charge holding unit that holds the charges generated by the photoelectric conversion unit.
The photoelectric conversion device according to any one of claims 1 to 6, wherein the light-shielding film is arranged so as to cover the charge holding portion. The photoelectric conversion device according to any one of claims 1 to 7, wherein the contact plug penetrates the silicon oxide film. Has other contact plugs,
The one according to any one of claims 1 to 8, wherein the other contact plug penetrates the interlayer insulating film, the silicon oxide film, and the second silicon nitride layer and comes into contact with the silicide portion. Photoelectric converter. A device including the photoelectric conversion device according to any one of claims 1 to 9.
Control based on the optical system that forms an image on the photoelectric conversion device, the control device that controls the photoelectric conversion device, the processing device that processes the signal output from the photoelectric conversion device, and the information obtained by the photoelectric conversion device. A device further comprising at least one of a mechanical device, a display device for displaying information obtained by the photoelectric conversion device, and a storage device for storing information obtained by the photoelectric conversion device.

Images