JP2007159085A - Bias circuit and amplifier using same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bias circuit and amplifier using the same in which the sneak path of a current of an AC signal to an output terminal is reduced and variations of output voltages can be reduced. <P>SOLUTION: The bias circuit in one embodiment includes: a first transistor including a collector connected to an input terminal and an emitter connected to a power line; a first impedance element connected between the base of the first transistor and an output terminal; a second transistor including a base connected to the input terminal and a collector connected to the power line; and a second impedance element connected between the emitter of the second transistor and the output terminal. The first and second impedance elements have impedance greater than input impedance of an emitter amplifier circuit in an AC signal input to the emitter amplifier circuit connected to the output terminal. An amplifier in one embodiment comprises the bias circuit. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a bias circuit and an amplifying apparatus using the bias circuit.

  A bias circuit for supplying a bias to an input terminal of a grounded emitter amplifier circuit is known. Patent Documents 1 and 2 describe an emitter-follower type bias circuit. Patent Document 3 describes a bias circuit in which an emitter follower type bias circuit and a current mirror type bias circuit are combined. Specifically, the bias circuit described in Patent Document 3 includes an emitter follower transistor and a current mirror transistor. The base of the emitter follower transistor is connected to the collector of the current mirror transistor and the constant current circuit, and the emitter of the emitter follower transistor is connected to the base of the current mirror transistor and the grounded emitter amplifier circuit. That is, the current mirror transistor and the grounded emitter transistor in the grounded emitter amplifier circuit form a current mirror circuit.

  As described above, since the output terminals of the bias circuits described in Patent Documents 1, 2, and 3 are directly connected to the input terminals of the grounded emitter amplifier circuit, the output terminals of these bias circuits are connected to the grounded emitter amplifier circuit. A part of the current of the alternating current signal to be inputted will wrap around. As a result, the current of the AC signal input to the grounded emitter amplifier circuit is reduced. Further, in the bias circuit described in Patent Document 3, since the output voltage is stabilized by the loop processing including the emitter follower transistor and the current mirror transistor, the voltage amplitude of the AC signal input to the grounded emitter amplifier circuit is canceled. It will be. As a result, the voltage amplitude of the AC signal input to the grounded emitter amplifier circuit is reduced.

These problems can be solved by the bias circuits described in Patent Documents 4 and 5. In the bias circuit described in Patent Document 4, a resistance element is provided in series between the output terminal and the emitter of the emitter follower transistor. Similarly, the bias circuit described in Patent Document 5 has a resistance element in series between the output terminal, the emitter of the emitter follower transistor, and the base of the current mirror transistor. In the bias circuits described in Patent Documents 4 and 5, the resistance element reduces the sneak current of the AC signal to be input to the grounded emitter amplifier circuit. As a result, a decrease in the current of the AC signal input to the grounded emitter amplifier circuit is reduced. In the bias circuits described in Patent Documents 4 and 5, the resistance element reduces fluctuations in the voltage of the emitter of the emitter follower transistor and the base of the current mirror transistor. Therefore, the emitter follower transistor, the current mirror transistor, Loop processing including is not performed. As a result, a decrease in the voltage amplitude of the AC signal input to the grounded emitter amplifier circuit is reduced.
US Pat. No. 3,999,140 US Pat. No. 6,946,913 US Pat. No. 6,456,163 US Pat. No. 6,778,018 US Pat. No. 6300837

  By the way, since the base voltage-base current characteristic of the transistor is an exponential function characteristic, in the grounded-emitter transistor in the grounded-emitter amplifier circuit, when the AC signal is input, the base is higher than when the AC signal is not input. The direct current component of the current increases. The DC component of this base current is supplied from a bias circuit. Therefore, when a resistor element is included in the output as in the bias circuits described in Patent Documents 4 and 5, the amount of voltage drop in the resistor element increases, and the output voltage of the bias circuit decreases.

  Further, in the grounded emitter transistor in the grounded emitter amplifier circuit, the direct current component of the base current varies according to the amplitude of the alternating current signal input to the base. Therefore, in the bias circuits described in Patent Documents 4 and 5, the voltage in the resistance element The amount of drop fluctuates and the output voltage of the bias circuit fluctuates. That is, the bias voltage at the base of the grounded emitter transistor in the grounded emitter amplifier circuit varies. As a result, the waveform of the output signal of the grounded emitter amplifier circuit is distorted.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a bias circuit capable of reducing the wraparound of the current of the AC signal to the output terminal and reducing the fluctuation of the output voltage, and an amplifying apparatus using the bias circuit. It is said.

  A first bias circuit according to the present invention is (1) a bias circuit including an input terminal connected to a constant current circuit and an output terminal connected to an input terminal of a grounded emitter amplifier circuit that amplifies an AC signal. (2) a first transistor having a collector connected to the input terminal, an emitter connected to the first power supply line, and a base; and (3) connected between the base and output terminal of the first transistor. (4) a second transistor having a base connected to the input terminal, a collector connected to the second power supply line, and an emitter; and (5) an emitter of the second transistor. And a second impedance element connected between the output terminal and the output terminal. (6) The impedance of the first impedance element and the impedance of the second impedance element at the frequency of the AC signal are respectively larger than the input impedance of the grounded-emitter amplifier circuit at the frequency. Note that the second transistor may be a bipolar transistor or a field effect transistor.

  According to the first bias circuit, the first impedance element is provided between the output terminal and the base of the first transistor, and the frequency of the AC signal to be input to the input terminal of the grounded emitter amplifier circuit. Has an impedance larger than the input impedance of the grounded-emitter amplifier circuit, the wraparound of the AC signal to the first transistor is reduced. Similarly, a second impedance element is provided between the output terminal and the emitter (or source) of the second transistor, and is grounded at the frequency of the AC signal to be input to the input terminal of the grounded emitter amplifier circuit. Since the impedance is higher than the input impedance of the amplifier circuit, the wraparound of the AC signal to the second transistor is reduced. Therefore, according to the first bias circuit, it is possible to reduce the AC signal to be input to the grounded-emitter amplifier circuit from reaching the output terminal of the first bias circuit.

  By the way, if the second impedance element has an impedance with respect to the direct current, the voltage drop amount of the second impedance element varies due to the variation of the output current, and as a result, the output voltage varies. However, according to the first bias circuit, since the second impedance element is included in the loop including the first transistor and the second transistor, even if the output current fluctuates, The output voltage is held constant by loop processing including the second transistor, the second transistor, and the second impedance element.

  A second bias circuit of the present invention is (1) a bias circuit having an input terminal connected to a constant current circuit and an output terminal connected to an input terminal of a grounded emitter amplifier circuit for amplifying an AC signal. (2) a bias correction circuit having an input terminal and an output terminal connected to the input terminal of the second bias circuit; and (3) a current mirror having an input terminal and an output terminal connected to the output terminal of the bias correction circuit. A circuit, (4) a first transistor having a collector connected to the output terminal of the current mirror circuit, an emitter connected to the first power supply line, and a base, and (5) a base and a first transistor of the first transistor A first impedance element connected between the output terminals of the two bias circuits, (6) a base connected to the output terminal of the current mirror circuit, and a second power supply A second transistor having a collector and an emitter connected to each other, and (7) a second impedance element connected between the emitter of the second transistor and the output terminal of the second bias circuit. Yes. The bias correction circuit includes: (8) a third transistor having a collector connected to the input terminal of the bias correction circuit, an emitter connected to the first power supply line, and a base; and (9) an input terminal of the bias correction circuit. A fourth transistor having a base connected to the second power supply line, a collector connected to the second power supply line, and an emitter electrically connected to the base of the third transistor; and (10) a base of the third transistor. A third impedance element having one end and the other end connected; (11) a base connected to the other end of the third impedance element; a collector connected to the output terminal of the bias correction circuit; and a first power supply And a fifth transistor having an emitter connected to the line. (12) The impedance of the first impedance element and the impedance of the second impedance element at the frequency of the AC signal are each greater than the input impedance of the grounded emitter amplifier circuit at the frequency. Note that the second transistor and the fourth transistor may be bipolar transistors or field effect transistors.

  Also in the second bias circuit, the first impedance element is provided between the output terminal and the base of the first transistor, and the second impedance element is the emitter of the output terminal and the second transistor (or The impedance of the first impedance element and the second impedance element is greater than the input impedance of the grounded emitter amplifier circuit at the frequency of the AC signal to be input to the input terminal of the grounded emitter amplifier circuit. Therefore, it is possible to reduce the AC signal to be input to the grounded emitter amplifier circuit from flowing into the output terminal of the second bias circuit. Also in this second bias circuit, since the second impedance element is included in the loop including the first transistor and the second transistor, even if the output current fluctuates, the first transistor, The output voltage is held constant by loop processing including the second transistor and the second impedance element.

  In the second bias circuit, since the first impedance element is inserted in the base of the first transistor, the output voltage includes the base voltage of the first transistor and the voltage drop amount of the first impedance element. The sum of Since the base current of the first transistor, that is, the collector current (Ic / β) corresponding to the current amplification factor of the first transistor flows through the first impedance element, the variation in the current amplification factor of the first transistor and the first There is a possibility that the voltage drop amount of the first impedance element varies due to the variation of the impedance of the first impedance element, and the output voltage of the second bias circuit varies. Further, the voltage drop amount of the first impedance element fluctuates due to the temperature fluctuation of the current amplification factor of the first transistor and the temperature fluctuation of the impedance of the first impedance element, and the output voltage of the second bias circuit changes. May fluctuate.

  However, in the second bias circuit, the bias correction circuit includes the fifth transistor and the fourth transistor that constitute a circuit similar to the circuit including the first transistor and the second transistor, And a third impedance element is inserted in the base of the fifth transistor, so that the base voltage of the fifth transistor is the third transistor. This is a voltage obtained by subtracting the voltage drop amount of the third impedance element from the base voltage. Accordingly, the base voltage of the fifth transistor varies due to variations in the current amplification factor of the fifth transistor and variations in the impedance of the third impedance element, for example, the voltage drop amount of the first impedance element and the When the voltage drop amount of the impedance element 3 increases, it decreases. As a result, the collector current of the fifth transistor is reduced. In the second bias circuit, the current mirror circuit supplies a current proportional to the collector current of the fifth transistor to the collector of the first transistor and the base of the second transistor, so that the collector current of the fifth transistor is When it decreases, the collector current of the first transistor decreases and the base current of the second transistor decreases. As a result, the voltage drop amount of the first impedance element is reduced, and the base voltage of the first transistor is reduced. On the other hand, for example, when the voltage drop amount of the first impedance element and the voltage drop amount of the third impedance element decrease, the base voltage of the fifth transistor rises, the collector current of the fifth transistor, The collector current of the transistor and the base current of the second transistor increase. As a result, the amount of voltage drop of the first impedance element increases and the base voltage of the first transistor decreases. Therefore, according to the second bias circuit, it is possible to reduce variations in output voltage caused by variations in current amplification factor of transistors and impedances of impedance elements.

  Further, the base voltage of the fifth transistor varies due to the temperature variation of the current amplification factor of the fifth transistor and the temperature variation of the impedance of the third impedance element, for example, the voltage drop of the first impedance element. When the amount and the voltage drop amount of the third impedance element increase, they decrease. As a result, as described above, the voltage drop amount of the first impedance element is reduced, and the base voltage of the first transistor is reduced. Similarly, when the voltage drop amount of the first impedance element and the voltage drop amount of the third impedance element decrease, the base voltage of the fifth transistor rises. As a result, as in the above, As the amount of voltage drop increases, the base voltage of the first transistor rises. Therefore, in this second bias circuit, fluctuations in the output voltage due to temperature fluctuations in the current amplification factor of the transistor and the impedance of the impedance element can be reduced.

In the second bias circuit described above, the ratio of the impedance of the first impedance element to the impedance of the third impedance element is R1 to R3, and the ratio of the size of the first transistor to the size of the fifth transistor is N1 to N5. When the ratio of the input current to the output current in the current mirror circuit is P6 to P7,
R1 / R3 = N5 / N1 = P6 / P7
It is preferable that

  According to this configuration, the current mirror circuit, the first transistor, the fifth transistor, and the third impedance element can compensate for variations in the voltage drop amount and temperature variation of the first impedance element, and the second The output voltage value of the bias circuit can be made equal to the base voltage value of the third transistor. Therefore, if the base voltage of the third transistor is kept constant by a constant current supplied from an external constant current circuit, the second bias circuit is not affected by temperature fluctuations of the transistor current amplification factor and impedance of the impedance element. The output voltage can be kept constant. The transistor size is a value corresponding to the emitter cross-sectional area and a value corresponding to the maximum emitter current (maximum collector current + maximum base current).

  In the first bias circuit and the second bias circuit described above, it is preferable that at least one of the first impedance element and the second impedance element is a resistance element. According to this configuration, since the resistive element having a small occupation area is used, it is preferably applied to a semiconductor integrated circuit.

  In the first bias circuit and the second bias circuit described above, it is preferable that at least one of the first impedance element and the second impedance element is an inductor. According to this configuration, since the inductor having a small impedance with respect to the direct current is used, the voltage drop amount of the second impedance element due to the fluctuation of the output current is reduced, and as a result, the fluctuation of the output voltage is reduced.

  A first amplifying device according to the present invention includes the first bias circuit, a constant current circuit connected between an input terminal of the first bias circuit and a power supply line, and the first bias circuit. And an amplifier circuit having an input terminal connected to the output terminal. According to the first amplifying device, the bias supplied to the input terminal of the amplifying circuit is held constant by the first bias circuit, so that the waveform distortion of the output signal is reduced. In addition, according to the first amplifying device, it is reduced that the AC signal to be input to the input terminal of the amplifier circuit goes around to the output terminal of the first bias circuit, so that a decrease in gain is reduced.

  A second amplifying device of the present invention includes the above-described second bias circuit, a constant current circuit connected between an input terminal of the second bias circuit and a power supply line, and the second bias circuit. And an amplifier circuit having an input terminal connected to the output terminal. Also in this second amplifying device, the bias supplied to the input terminal of the amplifying circuit is held constant by the second bias circuit, so that the waveform distortion of the output signal is reduced. Also in this second amplifying device, the reduction in gain is reduced because the AC signal to be input to the input terminal of the amplifier circuit is reduced from wrapping around the output terminal of the second bias circuit. Further, according to the second amplifying device, even when the current amplification factor of the transistor and the impedance of the impedance element vary, the variation in bias supplied to the input terminal of the amplifier circuit can be reduced by the second bias circuit. Therefore, variation in bias current in the amplifier circuit can be reduced. Further, according to the second amplifying device, even if the current amplification factor of the transistor and the impedance of the impedance element fluctuate in temperature, the temperature fluctuation of the bias supplied to the input terminal of the amplifier circuit is reduced by the second bias circuit. Therefore, temperature variation of the bias current in the amplifier circuit can be reduced.

  ADVANTAGE OF THE INVENTION According to this invention, the bias circuit which can reduce the wraparound of the electric current of the alternating current signal to an output terminal, and can reduce the fluctuation | variation of an output voltage, and the amplifier using this bias circuit are provided.

DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals.
(First embodiment)

  FIG. 1 is a circuit diagram showing an amplifying apparatus according to the first embodiment of the present invention. An amplifying apparatus 1 shown in FIG. 1 includes a bias circuit 10, a constant current circuit 20, and an amplifying circuit 30 according to the first embodiment of the present invention.

  The bias circuit 10 has an input terminal 10i and an output terminal 10o. The input terminal 10 i of the bias circuit 10 is connected to one end of the constant current circuit 20, and the output terminal 10 o of the bias circuit 10 is connected to the input terminal 30 i of the amplifier circuit 30.

  The other end of the constant current circuit 20 is connected to the second power line 42. The constant current circuit 20 includes a constant current source or a resistance element, and supplies a constant current to the input terminal 10 i of the bias circuit 10.

  The amplifier circuit 30 is a grounded emitter amplifier circuit including a grounded emitter transistor 31. The grounded emitter transistor 31 is an NPN-type bipolar transistor. The base of the grounded emitter transistor 31 is connected to the input terminal 30i, and the collector of the grounded emitter transistor 31 is connected to the output terminal 30o. The emitter of the common-emitter transistor 31 is connected to a first power supply line (for example, a ground line) 43. A bias is supplied to the input terminal 30 i of the amplifier circuit 30 from the output terminal 10 o of the bias circuit 10, and the AC signal S is also input via the capacitive element 40. The amplifier circuit 30 outputs an output signal obtained by amplifying the amplitude of the AC signal S to the output terminal 30o.

  Next, the bias circuit 10 of this embodiment will be described. The bias circuit 10 includes a first transistor 12, a second transistor 13, a first resistance element (first impedance element) 14, and a second resistance element (second impedance element) 15.

  The first transistor 12 is an NPN bipolar transistor. The collector of the first transistor 12 is connected to the input terminal 10 i, and the emitter of the first transistor 12 is connected to the first power supply line 43. The base of the first transistor 12 is connected to one end of the first resistance element 14, and the other end of the first resistance element 14 is connected to the output terminal 10o. The collector of the first transistor 12 is also connected to the base of the second transistor 13.

  The second transistor 13 is an NPN type bipolar transistor. The base of the second transistor 13 is also connected to the input terminal 10 i, and the collector of the second transistor 13 is connected to the second power supply line 42. The emitter of the second transistor 13 is connected to one end of the second resistance element 15, and the other end of the second resistance element 15 is connected to the output terminal 10 o and the other end of the first resistance element 14. Yes. Thus, the second transistor 13 forms an emitter follower circuit.

  Each of the first resistance element 14 and the second resistance element 15 has an impedance for reducing the AC signal S input to the other end. That is, each of the first resistance element 14 and the second resistance element 15 has an impedance at the frequency of the AC signal S input to the output terminal 10o. The impedances of the first resistance element 14 and the second resistance element 15 are preferably larger than the input impedance of the amplifier circuit 30, respectively. More preferably, the impedances of the first resistance element 14 and the second resistance element 15 are each 10 times or more the input impedance of the amplifier circuit 30.

  In other words, the impedance of the first resistance element 14 is a combination of the parasitic impedance of the wiring between the other end of the first resistance element 14 and the input terminal 30 i of the amplifier circuit 30 and the input impedance of the amplifier circuit 30. It is preferable that it is larger than the impedance. More preferably, the impedance of the first resistance element 14 is a combination of the parasitic impedance of the wiring between the other end of the first resistance element 14 and the input terminal 30 i of the amplifier circuit 30 and the input impedance of the amplifier circuit 30. The impedance is 10 times or more.

  Similarly, the impedance of the second resistance element 15 is a combined impedance of the parasitic impedance of the wiring between the other end of the second resistance element 15 and the input terminal 30 i of the amplifier circuit 30 and the input impedance of the amplifier circuit 30. Larger is preferred. More preferably, the impedance of the second resistance element 15 is a combination of the parasitic impedance of the wiring between the other end of the second resistance element 15 and the input terminal 30 i of the amplifier circuit 30 and the input impedance of the amplifier circuit 30. The impedance is 10 times or more.

  For example, when the bias circuit 10 of the present embodiment is configured by a semiconductor integrated circuit, the first resistance element 14 and the second resistance element 15 each have a sheet resistance of 500 mΩ / square or more. Specifically, polysilicon, a diffusion layer, a well, a resistance metal layer, or the like can be applied to the material of the first resistance element 14 and the second resistance element 15. The polysilicon used for the first resistance element 14 and the second resistance element 15 has a resistance by reducing the impurity doping amount as compared with polysilicon for wiring described below.

  The wiring is made of a sheet resistance of less than 500 mΩ / square. Specifically, the wiring is made of a metal material such as Al, Cu, W, Au, or polysilicon. The polysilicon for wiring includes salicided polysilicon, silicided polysilicon, and polysilicon having a polymetal structure.

  Thus, the first resistance element 14 and the second resistance element 15 are distinguished from the parasitic impedance of the wiring for connecting the elements.

  The temperature characteristics of the first transistor 12 are preferably the same as the temperature characteristics of the grounded-emitter transistor 31 in the amplifier circuit 30. If the temperature characteristics of the first transistor 12 and the grounded emitter transistor 31 are the same, the fluctuation of the collector current of the grounded emitter transistor 31 due to the temperature fluctuation of the amplifier circuit 30 is suppressed, and the fluctuation of the operation of the amplifier circuit 30 is reduced. Can be suppressed.

  Next, operations of the bias circuit 10 and the amplification device 1 of the present embodiment will be described. When a constant current is input from the constant current circuit 20 via the input terminal 10i, the second transistor 13 and the first transistor 12 operate. Then, a bias is supplied to the base of the grounded-emitter transistor 31 by the emitter-follower type second transistor 13 and the current mirror type first transistor 12.

  Here, when the AC signal S is input to the base of the grounded-emitter transistor 31 via the capacitive element 40, the direct current component of the base current of the grounded-emitter transistor 31 increases.

  FIG. 2 is a diagram showing a base current-base voltage characteristic of a grounded-emitter transistor. When only the bias voltage Vdc from the bias circuit 10 is supplied to the base of the grounded emitter transistor 31, the base current of the grounded emitter transistor 31 is Idc. Here, when the AC signal S is input to the base of the grounded-emitter transistor 31, the average value of the base current I of the grounded-emitter transistor 31 due to the exponential characteristic between the base current and the base voltage of the grounded-emitter transistor 31. That is, the DC component of the base current I increases to Idc2.

  Refer to FIG. 1 again. Since the DC component Idc2 of the base current I is supplied from the bias circuit 10, the output current of the bias circuit 10 increases. That is, the current flowing through the second resistance element 15 increases. Therefore, the voltage drop amount of the second resistance element 15 increases and the voltage of the output terminal 10o decreases.

  Further, since the base voltage of the first transistor 12 also decreases, the current between the collector and the emitter of the first transistor 12 decreases, and the collector voltage of the first transistor 12 and the base voltage of the second transistor 13 increase. As a result, the emitter voltage of the second transistor 13 increases. Along with this, the voltage at the other end of the second resistance element 15, that is, the voltage at the output terminal 10o increases.

  As described above, even when the output current of the bias circuit 10 increases, the voltage of the output terminal 10o is kept at the constant value Vdc by the loop process including the first transistor 12, the second transistor 13, and the second resistance element 15. To be kept. That is, the base voltage of the grounded-emitter transistor 31 is kept at a constant value Vdc. As a result, the waveform of the output signal of the amplifier circuit 30 is not distorted.

  Next, consider a case where the amplitude of the AC signal S fluctuates. As is apparent from FIG. 2, when the amplitude of the AC signal S increases, the DC component of the base current of the grounded emitter transistor 31 is caused by the exponential characteristic between the base current and the base voltage of the grounded emitter transistor 31. Will increase. Therefore, the output current of the bias circuit 10 increases. Therefore, when the amplitude of the AC signal S increases, the bias circuit 10 operates in the same manner as described above, and the voltage at the output terminal 10o is maintained at the constant value Vdc. As a result, the waveform of the output signal of the amplifier circuit 30 is not distorted.

  When the amplitude of the AC signal S decreases, as is apparent from FIG. 2, the direct current component of the base current of the grounded emitter transistor 31 due to the exponential characteristic between the base current and the base voltage of the grounded emitter transistor 31. Decrease. For this reason, the output current of the bias circuit 10 decreases. Therefore, when the amplitude of the AC signal S decreases, the bias circuit 10 performs the operation opposite to that described above. Specifically, the current flowing through the second resistance element 15 decreases and the voltage drop amount of the second resistance element 15 decreases, whereby the voltage at the output terminal 10o increases.

  Further, since the base voltage of the first transistor 12 also increases, the current between the collector and the emitter of the first transistor 12 increases, and the collector voltage of the first transistor 12 and the base voltage of the second transistor 13 decrease. As a result, the emitter voltage of the second transistor 13 decreases. Along with this, the voltage at the other end of the second resistance element 15, that is, the voltage at the output terminal 10o decreases.

  As described above, even when the output current of the bias circuit 10 decreases, the voltage of the output terminal 10o is kept at the constant value Vdc by the loop processing including the first transistor 12, the second transistor 13, and the second resistance element 15. To be kept. As a result, the waveform of the output signal of the amplifier circuit 30 is not distorted.

  As described above, according to the bias circuit 10 of the present embodiment, the second resistance element (second impedance element) 15 is included in the loop including the first transistor 12 and the second transistor 13. Therefore, even if the output current fluctuates, the output voltage is held constant by the loop processing including the first transistor 12, the second transistor 13, and the second resistance element 15.

  Therefore, according to the amplifying apparatus 1 of the present embodiment, the bias supplied to the input terminal 30i of the amplifying circuit 30 is held constant by the bias circuit 10, so that the AC signal S input to the amplifying circuit 30 varies. However, the waveform distortion of the output signal of the amplifier circuit 30 is reduced.

  Further, according to the bias circuit 10 of the present embodiment, the first resistance element (first impedance element) 14 is provided between the output terminal 10 o and the base of the first transistor 12. Of the AC signal S to the transistor 12 is reduced. Similarly, since the second resistance element 15 is provided between the output terminal 10 o and the emitter of the second transistor 13, the wraparound of the AC signal S to the second transistor 13 is reduced.

Therefore, according to the amplifying apparatus 1 of the present embodiment, since the AC signal S to be input to the input terminal 30i of the amplifier circuit 30 is reduced from wrapping around the output terminal 10o of the bias circuit 10, a reduction in gain is reduced. Is done.
(Second Embodiment)

  FIG. 3 is a circuit diagram showing an amplifying apparatus according to the second embodiment of the present invention. An amplifying apparatus 1A shown in FIG. 3 includes a bias circuit 10A instead of the bias circuit 10 in the amplifying apparatus 1 of the first embodiment. The other configuration of the amplifying apparatus 1A is the same as that of the amplifying apparatus 1.

  The bias circuit 10A includes a first inductor 16 and a second inductor 17 in place of the first resistor element 14 and the second resistor element 15 in the bias circuit 10 of the first embodiment, respectively. The other configuration of the bias circuit 10A is the same as that of the bias circuit 10.

  One end of the first inductor 16 is connected to the base of the first transistor 12, and the other end of the first inductor 16 is connected to the output terminal 10o. The first inductor 16 has an impedance that reduces the AC signal S input to the other end. That is, the first inductor 16 has an impedance at the frequency of the AC signal S input to the output terminal 10o. The impedance of the first inductor 16 at the frequency of the AC signal S is preferably larger than the input impedance of the amplifier circuit 30 at the frequency of the AC signal S. More preferably, the impedance of the first inductor 16 at the frequency of the AC signal S is 10 times or more the input impedance of the amplifier circuit 30 at the frequency of the AC signal S.

  In other words, the impedance of the first inductor 16 at the frequency of the AC signal S is the parasitic impedance of the wiring between the other end of the first inductor 16 and the input terminal 30 i of the amplifier circuit 30, and the input of the amplifier circuit 30. The impedance is preferably larger than the combined impedance at the frequency of the AC signal S. More preferably, the impedance of the first inductor 16 at the frequency of the AC signal S is the parasitic impedance of the wiring between the other end of the first inductor 16 and the input terminal 30i of the amplifier circuit 30, and the input of the amplifier circuit 30. The impedance is 10 times or more of the combined impedance at the frequency of the AC signal S.

  One end of the second inductor 17 is connected to the emitter of the second transistor 13, and the other end of the second inductor 17 is connected to the output terminal 10o. The second inductor 17 has an impedance that reduces the AC signal S input to the other end. That is, the second inductor 17 has an impedance at the frequency of the AC signal S input to the output terminal 10o. The impedance of the second inductor 17 at the frequency of the AC signal S is preferably larger than the input impedance of the amplifier circuit 30 at the frequency of the AC signal S. More preferably, the impedance of the second inductor 17 at the frequency of the AC signal S is 10 times or more the input impedance of the amplifier circuit 30 at the frequency of the AC signal S.

  In other words, the impedance of the second inductor 17 at the frequency of the AC signal S is the parasitic impedance of the wiring between the other end of the second inductor 17 and the input terminal 30 i of the amplifier circuit 30, and the input of the amplifier circuit 30. The impedance is preferably larger than the combined impedance at the frequency of the AC signal S. More preferably, the impedance of the second inductor 17 at the frequency of the AC signal S is the parasitic impedance of the wiring between the other end of the second inductor 17 and the input terminal 30i of the amplifier circuit 30, and the input of the amplifier circuit 30. The impedance is 10 times or more of the combined impedance at the frequency of the AC signal S.

  Thus, according to the bias circuit 10A of the present embodiment, the first inductor (first impedance element) 16 is provided between the output terminal 10o and the base of the first transistor 12, and the amplifier circuit Since the impedance of the AC signal S to be input to the 30 input terminals 30i has an impedance larger than the input impedance of the amplifier circuit 30, the wraparound of the AC signal S to the first transistor 12 is reduced. Similarly, a second inductor (first impedance element) 15 is provided between the output terminal 10 o and the emitter of the second transistor 13, and an AC signal to be input to the input terminal 30 i of the amplifier circuit 30. Since the impedance is higher than the input impedance of the amplifier circuit 30 at the frequency S, the wraparound of the AC signal S to the second transistor 13 is reduced.

  Therefore, according to the amplifying apparatus 1A of the present embodiment, since the AC signal S to be input to the input terminal 30i of the amplifier circuit 30 is reduced from wrapping around the output terminal 10o of the bias circuit 10A, the reduction in gain is reduced. Is done.

  Further, according to the bias circuit 10A of the present embodiment, since the impedance of the second inductor 17 with respect to the DC component is small, the voltage drop amount of the second inductor 17 due to the fluctuation of the output current is reduced, and as a result, the output voltage Variability is reduced.

Therefore, according to the amplifying apparatus 1A of the present embodiment, fluctuations in the bias supplied to the input terminal 30i of the amplifying circuit 30 are reduced by the bias circuit 10A, so that the AC signal S input to the amplifying circuit 30 fluctuates. However, the waveform distortion of the output signal of the amplifier circuit 30 is reduced.
(Third embodiment)

  FIG. 4 is a circuit diagram showing an amplifying device according to the third embodiment of the present invention. An amplifying apparatus 1B shown in FIG. 4 is different from the first embodiment in that the amplifying apparatus 1 includes a bias circuit 10B instead of the bias circuit 10. Other configurations of the amplifying apparatus 1B are the same as those of the amplifying apparatus 1.

  The bias circuit 10B according to the third embodiment of the present invention is different from the bias circuit 10 in that the bias circuit 10 further includes a bias correction circuit 50 and a current mirror circuit 60. The other configuration of the bias circuit 10B is the same as that of the bias circuit 10.

  The input terminal 50 i of the bias correction circuit 50 is connected to the input terminal 10 i of the bias circuit 10, and the output terminal 50 o of the bias correction circuit 50 is connected to the input terminal 60 i of the current mirror circuit 60. An output terminal 60 o of the current mirror circuit 60 is connected to the collector of the first transistor 12 and the base of the second transistor 13.

  The bias correction circuit 50 includes a third transistor 51, a fourth transistor 52, a fifth transistor 53, a third resistance element (third impedance element) 54, and a fourth resistance element 55. The third transistor 51 is an NPN bipolar transistor. The collector of the third transistor 51 is connected to the input terminal 50 i of the bias correction circuit 50, and the emitter of the third transistor 51 is connected to the first power supply line 43. The base of the third transistor 51 is connected to one end of the third resistance element 54 and one end of the fourth resistance element 55. The collector of the third transistor 51 is also connected to the base of the fourth transistor 52.

  The fourth transistor 52 is an NPN type bipolar transistor. The base of the fourth transistor 52 is also connected to the input terminal 50 i of the bias correction circuit 50, and the collector of the fourth transistor 52 is connected to the second power supply line 42. The emitter of the fourth transistor 52 is connected to the other end of the fourth resistance element 55. That is, the emitter of the fourth transistor 52 is electrically connected to the base of the third transistor 51 and one end of the third resistor element 54 via the fourth resistor element 55. The other end of the third resistance element 54 is connected to the base of the fifth transistor 53.

  The fifth transistor 53 is an NPN bipolar transistor. The collector of the fifth transistor 53 is connected to the output terminal 50 o of the bias correction circuit 50, and the emitter of the fifth transistor 53 is connected to the first power supply line 43.

  As described above, the third transistor 51 and the fifth transistor 53 form a current mirror circuit, similarly to the first transistor 12 and the grounded-emitter transistor 31. The fourth transistor 52 constitutes an emitter follower circuit, similarly to the second transistor 13.

  The current mirror circuit 60 includes a sixth transistor 61 and a seventh transistor 62. The sixth transistor 61 and the seventh transistor 62 are PNP-type bipolar transistors. The collector of the sixth transistor 61 is connected to the input terminal 60 i of the current mirror circuit 60, and the emitter of the sixth transistor 61 is connected to the second power supply line 42. The base of the sixth transistor 61 is connected to the collector of the sixth transistor 61 and the base of the seventh transistor 62. The collector of the seventh transistor 62 is connected to the output terminal 60 o of the current mirror circuit 60, and the emitter of the seventh transistor 62 is connected to the second power supply line 42.

  Next, the operation of the bias circuit 10B will be described. When a constant current is input from the constant current circuit 20 through the input terminal 10 i, a bias is applied to the base of the fifth transistor 53 by the emitter-follower type fourth transistor 52 and the current mirror type third transistor 51. Supplied. Then, a current flows through the collector of the fifth transistor 53, and a mirror current of this current is generated by the current mirror circuit 60. The mirror current is supplied to the collector of the first transistor 12 and the base of the second transistor 13, and is biased to the base of the grounded-emitter transistor 31 by the emitter-follower type second transistor 13 and the current mirror type first transistor 12. Is supplied.

Here, the base voltage value VbeA of the grounded-emitter transistor 31, that is, the output voltage value of the bias circuit 10B, is expressed by the base voltage value Vbe1 of the first transistor 12 and the first resistance element as shown in the following equation (1). 14 voltage drop values R1 × Ic1 / β.
VbeA = Vbe1 + R1 × Ib1 = Vbe1 + R1 × Ic1 / β (1)
Ib1: Base current value of the first transistor Ic1: Collector current value of the first transistor β: Current amplification factor of each transistor R1: Resistance value of the first resistance element Therefore, the current amplification factor of the first transistor 12 There is a possibility that the voltage drop amount of the first resistance element 14 varies due to the variation and the variation of the resistance value of the first resistance element 14, and the output voltage of the bias circuit 10B, that is, the base voltage of the grounded emitter transistor 31 may vary. is there. As a result, the collector current of the grounded-emitter transistor 31 may vary. Further, the voltage drop amount of the first resistance element 14 fluctuates due to the temperature fluctuation of the current amplification factor of the first transistor 12 and the temperature fluctuation of the resistance value of the first resistance element 14, and the output of the bias circuit 10B. There is a possibility that the voltage, that is, the base voltage of the grounded-emitter transistor 31 varies. As a result, the collector current of the grounded-emitter transistor 31 may vary.

However, the base voltage value Vbe5 of the fifth transistor 53 in the bias correction circuit 50 is a voltage drop of the third resistance element 54 from the base voltage value Vbe3 of the third transistor 51 as shown in the following equation (2). The value is obtained by subtracting the value R3 × Ic5 / β.
Vbe5 = Vbe3-R3 × Ib5 = Vbe3-R3 × Ic5 / β (2)
Ib5: Base current value of the fifth transistor Ic5: Collector current value of the fifth transistor R3: Resistance value of the third resistance element

  Therefore, the base voltage of the fifth transistor 53 varies due to variations in the current amplification factor of the fifth transistor 53 and variations in the resistance value of the third resistance element 54, for example, It decreases when the voltage drop amount and the voltage drop amount of the third resistance element 54 increase. Then, the collector current of the fifth transistor 53, the collector current of the sixth transistor 61, and the collector current of the seventh transistor 62 are decreased, the collector current of the first transistor 12 is decreased, and the second transistor 13 is decreased. Decreases the base current. As a result, the amount of voltage drop of the first resistance element 14 decreases and the base voltage of the first transistor 12 decreases.

  On the other hand, for example, when the voltage drop amount of the first resistance element 14 and the voltage drop amount of the third resistance element 54 decrease, the base voltage of the fifth transistor 53 increases. Then, the collector current of the fifth transistor 53, the collector current of the sixth transistor 61, and the collector current of the seventh transistor 62 are increased, and the collector current of the first transistor 12 and the base current of the second transistor 13 are increased. To increase. As a result, the voltage drop amount of the first resistance element 14 increases and the base voltage of the first transistor 12 increases. Therefore, in the bias circuit 10B, it is possible to reduce variations in output voltage due to variations in transistor current amplification factors and resistance values of resistance elements, that is, variations in base voltage of the grounded-emitter transistor 31. As a result, variations in collector current of the grounded-emitter transistor 31 can be reduced.

  Further, the base voltage of the fifth transistor 53 varies due to the temperature variation of the current amplification factor of the fifth transistor 53 and the temperature variation of the resistance value of the third resistance element 54, for example, the first resistance It decreases when the voltage drop amount of the element 14 and the voltage drop amount of the third resistance element 54 increase. As a result, as described above, the voltage drop amount of the first resistance element 14 decreases and the base voltage of the first transistor 12 decreases. Similarly, when the voltage drop amount of the first resistance element 14 and the voltage drop amount of the third resistance element 54 decrease, the base voltage of the fifth transistor 53 increases. As a result, as described above, the voltage drop amount of the first resistance element 14 increases and the base voltage of the first transistor increases. Therefore, in the bias circuit 10B, it is possible to reduce the fluctuation of the output voltage due to the temperature fluctuation of the current amplification factor of the transistor and the temperature fluctuation of the resistance value of the resistance element, that is, the fluctuation of the base voltage of the grounded emitter transistor 31. As a result, the temperature fluctuation of the collector current of the common emitter transistor 31 can be reduced.

Next, the collector current variation and temperature variation of the grounded-emitter transistor 31 will be analyzed in more detail. First, the amplification device 1 of the first embodiment is analyzed. The collector current value IcA of the grounded-emitter transistor 31 and the collector current value Ic1 of the first transistor 12 are expressed by the following equations (3) and (4).
IcA = NA × I0 × exp (VbeA) (3)
Ic1 = N1 × I0 × exp (Vbe1) (4)
NA: Size of grounded-emitter transistor 31 N1: Size of first transistor 12 I0: Proportional constant The transistor size is a value corresponding to the emitter cross-sectional area, and is the maximum emitter current (maximum collector current + maximum base current). ).
From the above equations (4) and (1), the following equation (5) is obtained.
Ic1 = N1 × I0 × exp (VbeA−R1 × Ic1 / β) (5)
Further, the following expression (6) is obtained from the above expressions (5) and (3).
IcA = NA / N1 × exp (R1 × Ic1 / β) × Ic1 (6)

Here, the constant current value Ibias from the constant current circuit 20 is expressed by the following equation (7).
Ibias = Ic1 + Ib2
= Ic1 + Ic2 / β
= Ic1 + (Ib1 + IbA) / β
= Ic1 + (Ic1 / β + IcA / β) / β (7)
Ib2: Base current value of the second transistor 13 Ic2: Collector current value of the second transistor 13 IbA: Base current value of the grounded-emitter transistor 31 Generally, since the current amplification factor of the transistor is about 100, the above (7) The second term on the right side in the equation is sufficiently smaller than the first term. Therefore, the above equation (7) can be approximated as the following equation (8).
Ibias = Ic1 (8)
Therefore, the following equation (9) is obtained from the above equations (8) and (6).
IcA = NA / N1 × exp (R1 × Ibias / β) × Ibias (9)

  According to the equation (9), the collector current value IcA of the grounded-emitter transistor 31 is not only the transistor size ratio NA / N1 and the constant current value Ibias from the constant current circuit 20, but also the first resistance element 14 It can be seen that this also depends on the resistance value R1 and the current amplification factor β of the first transistor 12. As a result, the current ratio between IcA and Ibias varies due to variations in the current amplification factor of the first transistor 12 and variations in the resistance value of the first resistance element 14, and IcA, that is, the bias current of the amplifier circuit 30 varies. there is a possibility. Further, the current ratio between IcA and Ibias fluctuates due to the temperature fluctuation of the current amplification factor of the first transistor 12 and the temperature fluctuation of the resistance value of the first resistance element 14, and IcA, that is, the bias current of the amplifier circuit 30. May fluctuate.

Next, the bias circuit 10B of this embodiment is analyzed. The collector current value Ic3 of the third transistor 51 and the collector current value Ic5 of the fifth transistor 53 in the bias correction circuit 50 are expressed by the following equations (10) and (11).
Ic3 = N3 × I0 × exp (Vbe3) (10)
Ic5 = N5 × I0 × exp (Vbe5) (11)
Vbe3: Base voltage value N3 of the third transistor 51: Size of the third transistor 51 Vbe5: Base voltage value of the fifth transistor 53 N5: Size of the fifth transistor 53 The above equations (11) and (2) Thus, the following formula (12) is obtained.
Ic5 = N5 × I0 × exp (Vbe3-R3 × Ic5 / β) (12)

Here, when the mirror ratio of the current mirror circuit, that is, the output current / input current is P7 / P6, the collector current value Ic5 of the fifth transistor 53 and the collector current value Ic1 of the first transistor 12 are expressed by the following equations: The relationship represented by (13) holds.
Ic5 / P6 = Ic1 / P7 (13)
Therefore, the following equation (14) is obtained from the above equations (13), (12), and (5).
N5 / P6 × exp (Vbe3) / exp (R3 × P6 / P7 × Ic1 / β)
= N1 / P7 × exp (VbeA) / exp (R1 × Ic1 / β) (14)
According to the above equation (14), it is understood that VbeA = Vbe3 when N5 / P6 = N1 / P7 and R3 × P6 / P7 = R1, that is, R1 / R3 = N5 / N1 = P6 / P7. . At this time, the following equation (15) is obtained from the above equations (10) and (3).
IcA = NA / N3 × IC3 (15)
Since IC3 = Ibias can be approximated, the above equation (15) can be approximated as the following equation (16).
IcA = NA / N3 × Ibias (16)

  According to the above equation (16), the collector current value IcA of the grounded-emitter transistor 31 does not depend on the transistor current amplification factor and the resistance value of the resistance element, and the transistor size ratio NA / N3 and the constant current circuit 20 It can be seen that it is determined only by the constant current value Ibias. Therefore, when the condition of R1 / R3 = N5 / N1 = P6 / P7 is satisfied, even if the transistor current amplification factor and the resistance value of the resistance element vary, the collector current of the common-emitter transistor 31 and the constant current circuit 20 The current ratio with the current is kept constant, and the collector current of the grounded-emitter transistor 31, that is, the bias current of the amplifier circuit 30, is kept constant. Further, even if the current amplification factor of the transistor and the resistance value of the resistance element fluctuate, the current ratio between the collector current of the common emitter transistor 31 and the constant current from the constant current circuit 20 is kept constant, The collector current, that is, the bias current of the amplifier circuit 30 is kept constant.

  Thus, in the bias circuit 10B of the present embodiment, R1 / R3 = N5 / N1 = P6 / P7 is preferable. However, as described above in the explanation of the operation of the bias circuit 10B, R1 / R3, N5 / N1. Even if P6 / P7 do not match, it is possible to reduce the collector current variation and temperature variation of the grounded-emitter transistor 31. Below, the simulation result is demonstrated.

  5 and 6 are diagrams showing variations in the current ratio between IcA and Ic1 in the amplifying apparatus of the first embodiment. FIG. 5 shows a simulation result of the current ratio (IcA / NA) / (Ic1 / N1) of IcA and Ic1 with respect to the current amplification factor β of the first transistor 12. FIG. The simulation result of the current ratio (IcA / NA) / (Ic1 / N1) of IcA and Ic1 with respect to the resistance value R1 of the resistance element 14 is shown. The horizontal axis in FIG. 6 is a relative value ΔR1 with respect to 500 kΩ.

  In FIG. 5, when β is 50, 75, 100, 150, 200, (IcA / NA) / (Ic1 / N1) is 7.39, 3.79, 2.72, 1.95, 1.. 65. As can be seen from FIG. 5, when β varies from 50 to 200, the variation width of (IcA / NA) / (Ic1 / N1) is 5.74. In FIG. 6, when ΔR1 is 0.8, 0.9, 1.0, 1.1, 1.2, (IcA / NA) / (Ic1 / N1) is 2.23, 2.. 46, 2.72, 3.00, and 3.32. According to FIG. 6, when R1 varies from 0.8 times to 1.2 times with respect to 500 kΩ, the variation width of (IcA / NA) / (Ic1 / N1) is 1.08.

  7 and 8 are diagrams showing variations in the current ratio between IcA and Ic3 in the amplifying apparatus according to the third embodiment. FIG. 7 shows a simulation result of the current ratio (IcA / NA) / (Ic3 / N3) of IcA and Ic3 with respect to the current amplification factor β of the first transistor 12. FIG. The simulation result of the current ratio (IcA / NA) / (Ic3 / N3) of IcA and Ic3 with respect to the resistance value of the resistance element 14 is shown. The horizontal axis in FIG. 8 is the relative value ΔR1 with respect to 500 kΩ.

  When R1 / R3 = N5 / N1 is a fixed value K1 and P6 / P7 is a variable K2, in FIG. 7, curves 71, 72, 73, 74, and 75 are represented by K2 / K1 = 0.5, 0. (IcA / NA) / (Ic3 / N3) at 75, 1.0, 1.5, and 2.0 are shown. In FIG. 8, curves 81, 82, 83, 84, and 85 are (IcA / NA) when K2 / K1 = 0.5, 0.75, 1.0, 1.5, and 2.0, respectively. / (Ic3 / N3).

  According to curve 71 in FIG. 7, when β is 50, 75, 100, 150, 200, (IcA / NA) / (Ic3 / N3) is 5.44, 3.90, 3.30, 2 respectively. 79 and 2.57, and when β varies from 50 to 200, the variation width of (IcA / NA) / (Ic3 / N3) is 2.87. According to curve 72, when β is 50, 75, 100, 150, 200, (IcA / NA) / (Ic3 / N3) is 2.20, 1.86, 1.71, 1.58, respectively. When β varies from 50 to 200, it can be seen that the variation width of (IcA / NA) / (Ic3 / N3) is 0.69. According to curve 73, since R1 / R3 = N5 / N1 = P6 / P7, (IcA / NA) / (Ic3 / N3) remains constant even if β varies from 50 to 200. I understand. According to curve 74, when β is 50, 75, 100, 150, 200, (IcA / NA) / (Ic3 / N3) is 0.25, 0.34, 0.40, 0.48, respectively. When β varies from 50 to 200, it can be seen that the variation width of (IcA / NA) / (Ic3 / N3) is 0.27. According to curve 75, when β is 50, 75, 100, 150, 200, (IcA / NA) / (Ic3 / N3) is 0.07, 0.13, 0.18, 0.26, respectively. When β is 0.30 and β varies from 50 to 200, it can be seen that the variation width of (IcA / NA) / (Ic3 / N3) is 0.23.

  Thus, according to FIG. 7, if K2 / K1 is 0.75 or more and 2.0 or less, (IcA / NA) / (Ic3 / N3) with respect to the amplification device 1 of the first embodiment. It can be seen that the variation of the can be reduced to about 1/10. Further, according to FIG. 7, if K2 / K1 = 1, that is, R1 / R3 = N5 / N1 = P6 / P7, the variation of (IcA / NA) / (Ic3 / N3) can be made zero. It can be seen that it is.

  According to the curve 81 in FIG. 8, when ΔR1 is 0.8, 0.9, 1.0, 1.1, 1.2, (IcA / NA) / (Ic3 / N3) is 2.98, respectively. , 3.14, 3.30, 3.47, 3.64, and ΔR1 varies from 0.8 times to 1.2 times with respect to 500 kΩ, (IcA / NA) / (Ic3 / N3) It can be seen that the variation width is 0.66. According to curve 82, when ΔR1 is 0.8, 0.9, 1.0, 1.1, 1.2, (IcA / NA) / (Ic3 / N3) is 1.63, 1.. When ΔR1 varies from 0.8 times to 1.2 times with respect to 500 kΩ, the variation width of (IcA / NA) / (Ic3 / N3) is 67, 1.71, 1.76, 1.80. It turns out that it is 0.17. According to the curve 83, since R1 / R3 = N5 / N1 = P6 / P7, even if ΔR1 varies from 0.8 to 1.2 times with respect to 500 kΩ, (IcA / NA) / (Ic3 / It can be seen that N3) remains constant at 1. According to curve 84, when ΔR1 is 0.8, 0.9, 1.0, 1.1, 1.2, (IcA / NA) / (Ic3 / N3) is 0.45, 0. When ΔR1 varies from 0.8 times to 1.2 times with respect to 500 kΩ, the variation width of (IcA / NA) / (Ic3 / N3) is 43,0.40,0.38,0.37. It turns out that it is 0.08. According to curve 85, when ΔR1 is 0.8, 0.9, 1.0, 1.1, 1.2, (IcA / NA) / (Ic3 / N3) is 0.22, 0. When ΔR1 varies from 0.8 times to 1.2 times with respect to 500 kΩ, the variation width of (IcA / NA) / (Ic3 / N3) is 20, 0.18, 0.17, 0.15. It turns out that it is 0.07.

  As described above, according to FIG. 8, when K2 / K1 is 0.75 or more and 2.0 or less, (IcA / NA) / (Ic3 / N3) is compared with the amplification device 1 of the first embodiment. It can be seen that the variation of the can be reduced to about 1/10. Further, according to FIG. 8, if K2 / K1 = 1, that is, R1 / R3 = N5 / N1 = P6 / P7, the variation of (IcA / NA) / (Ic3 / N3) can be made zero. It can be seen that it is.

  As described above, the effect of reducing variation in (IcA / NA) / (Ic3 / N3) when P6 / P7 is different from R1 / R3 = N5 / N1 is shown. Even if / N1 is different, R1 / R3 is different for N5 / N1 = P6 / P7, and R1 / R3, N5 / N1 and P6 / P7 are all different (IcA / NA) / ( It is clear that the effect of reducing variation in Ic3 / N3) can be obtained.

  Moreover, although the variation reduction effect of (IcA / NA) / (Ic3 / N3) was shown above, it is clear that the temperature fluctuation of (IcA / NA) / (Ic3 / N3) can also be reduced.

  Thus, since the bias circuit 10B of the third embodiment has the same configuration as that of the first embodiment, the same advantages as those of the first embodiment can be obtained. Furthermore, according to the bias circuit 10B of the third embodiment, since the bias correction circuit 50 and the current mirror circuit 60 are provided, the output voltage due to the variation in the current amplification factor of the transistor and the resistance value of the resistance element is reduced. Variations can be reduced, and fluctuations in output voltage due to temperature fluctuations in transistor current amplification factors and resistance values of resistance elements can be reduced.

  Therefore, the amplification device 1B according to the third embodiment can obtain the same advantages as those of the first embodiment. Furthermore, according to the amplifying apparatus 1B of the third embodiment, even when the current amplification factor of the transistor and the resistance value of the resistance element vary, the bias circuit 10B causes variations in bias supplied to the input terminal 30i of the amplifier circuit 30. Therefore, variation in bias current in the amplifier circuit 30 can be reduced. Further, according to the amplifying apparatus 1B of the third embodiment, even if the current amplification factor of the transistor and the resistance value of the resistance element fluctuate depending on the temperature, the temperature variation of the bias supplied to the input terminal 30i of the amplifying circuit 30 is reduced. Since it can be reduced by the bias circuit 10B, variations in the bias current in the amplifier circuit 30 can be reduced.

  The present invention is not limited to the above-described embodiment, and various modifications can be made.

  The combination of element types of the first impedance element and the second impedance element is not limited to this embodiment. For example, the first impedance element may be a resistance element, the second impedance may be an inductor, the first impedance element may be an inductor, and the second impedance may be a resistance element.

  In the first embodiment and the second embodiment, the circuit configuration using the NPN type bipolar transistor is exemplified. However, the present invention can be applied to the circuit configuration using the PNP type bipolar transistor. Further, the present invention can be applied even if the emitter follower circuit using the second transistor 13 is replaced with a source follower circuit using MOSFET. In these cases, Ib2 = 0 in the equation (7), but even when an NPN bipolar transistor is used as the second transistor 13, the second term on the right side of the equation (7) is approximated to 0. The following equation is similarly established. Similarly, the third embodiment may have a circuit configuration in which a PNP bipolar transistor is used instead of the NPN bipolar transistor, and an NPN bipolar transistor is used instead of the PNP bipolar transistor. Further, the present invention can be applied even if the emitter follower circuit using the fourth transistor 52 is replaced with a source follower circuit using MOSFET.

  In the third embodiment, the fourth resistor element 55 is connected between the emitter of the fourth transistor 52, the base of the third transistor 51, and one end of the third resistor element 54. Although the circuit 50 is illustrated, since the resistance value of the fourth resistance element 55 is not directly related to the current correction of the bias correction circuit 50, the bias correction circuit does not have the fourth resistance element 55, that is, the first Even when the emitter of the fourth transistor 52, the base of the third transistor 51, and one end of the third resistance element 54 are directly connected, the same advantages as in the third embodiment can be obtained.

  In the third embodiment, the current mirror circuit 60 constituted by PNP-type bipolar transistors is exemplified, but the configuration of the current mirror circuit is not limited to this embodiment. For example, the current mirror circuit may be constituted by a P-type MOSFET or a cascode current mirror circuit. In addition, a resistance element may be inserted in the emitter (source) of the transistor in the current mirror circuit.

  In the third embodiment, the resistance element is exemplified as the third impedance element. However, when the first impedance element is an inductor, the third impedance element is preferably an inductor.

1 is a circuit diagram showing an amplifying device according to a first embodiment of the present invention. It is a figure which shows the base current-base voltage characteristic of a common emitter transistor. It is a circuit diagram which shows the amplifier which concerns on the 2nd Embodiment of this invention. It is a circuit diagram which shows the amplifier which concerns on the 3rd Embodiment of this invention. It is a figure which shows the dispersion | variation in the current ratio of IcA and Ic1 in the amplification apparatus of 1st Embodiment. It is a figure which shows the dispersion | variation in the current ratio of IcA and Ic1 in the amplification apparatus of 1st Embodiment. It is a figure which shows the dispersion | variation in the current ratio of IcA and Ic3 in the amplifier apparatus of 3rd Embodiment. It is a figure which shows the dispersion | variation in the current ratio of IcA and Ic3 in the amplifier apparatus of 3rd Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1,1B ... Amplifying device 10, 10B ... Bias circuit, 12 ... 1st transistor, 13 ... 2nd transistor, 14 ... 1st resistance element (1st impedance element), 15 ... Resistance element (1st Impedance element), 20 ... constant current circuit, 30 ... amplifier circuit, 31 ... grounded emitter transistor, 40 ... capacitor element, 50 ... bias correction circuit, 60 ... current mirror circuit, 51 ... third transistor, 52 ... fourth. , 53... Fifth transistor, 54... Third resistance element (third impedance element).

Claims (8)

A bias circuit comprising an input terminal connected to a constant current circuit and an output terminal connected to an input terminal of a grounded emitter amplifier circuit for amplifying an AC signal,
A first transistor having a collector connected to the input terminal, an emitter connected to a first power supply line, and a base;
A first impedance element connected between the base of the first transistor and the output terminal;
A second transistor having a base connected to the input terminal, a collector connected to a second power supply line, and an emitter;
A second impedance element connected between the emitter of the second transistor and the output terminal;
With
The impedance of the first impedance element and the impedance of the second impedance element at the frequency of the AC signal are larger than the input impedance of the grounded emitter amplifier circuit at the frequency, respectively.
Bias circuit. A bias circuit comprising an input terminal connected to a constant current circuit and an output terminal connected to an input terminal of a grounded emitter amplifier circuit for amplifying an AC signal,
A first transistor having a collector connected to the input terminal, an emitter connected to a first power supply line, and a base;
A first impedance element connected between the base of the first transistor and the output terminal;
A second transistor having a gate connected to the input terminal, a drain connected to a second power supply line, and a source;
A second impedance element connected between the source of the second transistor and the output terminal;
With
The impedance of the first impedance element and the impedance of the second impedance element at the frequency of the AC signal are larger than the input impedance of the grounded emitter amplifier circuit at the frequency, respectively.
Bias circuit. A bias circuit comprising an input terminal connected to a constant current circuit and an output terminal connected to an input terminal of a grounded emitter amplifier circuit for amplifying an AC signal,
A bias correction circuit having an input terminal and an output terminal connected to the input terminal of the bias circuit;
A current mirror circuit having an input terminal and an output terminal connected to the output terminal of the bias correction circuit;
A first transistor having a collector connected to the output terminal of the current mirror circuit, an emitter connected to a first power supply line, and a base;
A first impedance element connected between the base of the first transistor and the output terminal of the bias circuit;
A second transistor having a base connected to the output terminal of the current mirror circuit, a collector connected to a second power supply line, and an emitter;
A second impedance element connected between the emitter of the second transistor and the output terminal of the bias circuit;
With
The bias correction circuit includes:
A third transistor having a collector connected to the input terminal of the bias correction circuit, an emitter connected to the first power supply line, and a base;
A fourth transistor having a base connected to the input terminal of the bias correction circuit, a collector connected to the second power supply line, and an emitter electrically connected to the base of the third transistor; ,
A third impedance element having one end and the other end connected to the base of the third transistor;
A fifth transistor having a base connected to the other end of the third impedance element, a collector connected to the output terminal of the bias correction circuit, and an emitter connected to the first power supply line;
Have
The impedance of the first impedance element and the impedance of the second impedance element at the frequency of the AC signal are larger than the input impedance of the grounded emitter amplifier circuit at the frequency, respectively.
Bias circuit. A bias circuit comprising an input terminal connected to a constant current circuit and an output terminal connected to an input terminal of a grounded emitter amplifier circuit for amplifying an AC signal,
A bias correction circuit having an input terminal and an output terminal connected to the input terminal of the bias circuit;
A current mirror circuit having an input terminal and an output terminal connected to the output terminal of the bias correction circuit;
A first transistor having a collector connected to the output terminal of the current mirror circuit, an emitter connected to a first power supply line, and a base;
A first impedance element connected between the base of the first transistor and the output terminal of the bias circuit;
A second transistor having a gate connected to the output terminal of the current mirror circuit, a drain connected to a second power supply line, and a source;
A second impedance element connected between the source of the second transistor and the output terminal of the bias circuit;
With
The bias correction circuit includes:
A third transistor having a collector connected to the input terminal of the bias correction circuit, an emitter connected to the first power supply line, and a base;
A fourth transistor having a gate connected to the input terminal of the bias correction circuit, a drain connected to the second power supply line, and a source electrically connected to the base of the third transistor; ,
A third impedance element having one end and the other end connected to the base of the third transistor;
A fifth transistor having a base connected to the other end of the third impedance element, a collector connected to the output terminal of the bias correction circuit, and an emitter connected to the first power supply line;
Have
The impedance of the first impedance element and the impedance of the second impedance element at the frequency of the AC signal are larger than the input impedance of the grounded emitter amplifier circuit at the frequency, respectively.
Bias circuit. The ratio between the impedance R1 of the first impedance element and the impedance R3 of the third impedance element is R1 to R3, and the ratio between the size N1 of the first transistor and the size N5 of the fifth transistor is N1. N5, when the ratio of the input current P6 and the output current P7 in the current mirror circuit is P6 to P7,
R1 / R3 = N5 / N1 = P6 / P7
It is characterized by
The bias circuit according to claim 3 or 4. At least one of the first impedance element and the second impedance element is a resistance element.
The bias circuit according to claim 1. At least one of the first impedance element and the second impedance element is an inductor.
The bias circuit according to claim 1. The bias circuit according to claim 1, a constant current circuit connected between an input terminal of the bias circuit and a power supply line, and an input terminal connected to the output terminal of the bias circuit. An amplifier circuit,
Amplification equipment.

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