JP2007157862A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2007157862A
JP2007157862A JP2005348602A JP2005348602A JP2007157862A JP 2007157862 A JP2007157862 A JP 2007157862A JP 2005348602 A JP2005348602 A JP 2005348602A JP 2005348602 A JP2005348602 A JP 2005348602A JP 2007157862 A JP2007157862 A JP 2007157862A
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external lead
terminal
semiconductor device
ferrite core
out terminal
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Eiji Hosokawa
英治 細川
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Fuji Electric Co Ltd
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Fuji Electric Device Technology Co Ltd
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
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    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L2224/4903—Connectors having different sizes, e.g. different diameters
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    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
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    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
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    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of inhibiting noises generated in the case of a switching operation by a small occupied area. <P>SOLUTION: A ferrite core 8 is inserted to a drain terminal 5, and sealed with a molding resin 12 including even the ferrite core 8. Consequently, noises generated in the case of the switching operation can be inhibited with the small occupied area. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

この発明はフィルターを内蔵した半導体装置に関する。   The present invention relates to a semiconductor device incorporating a filter.


半導体スイッチング素子（以下、単に素子という）は、主にスイッチングのタイミングを行うゲート信号（ここではベース信号も含む）が入力されるゲート端子（ここではベース端子も含む）と主電流が流れる経路の入出力端子となる＋主端子と−主端子の３端子を有している。ゲート信号が入ることにより素子のスイッチングが行われ、入出力端子を介して主電流がパワー経路に流れる。このスイッチング時において、ゲート信号がオフ信号になり素子に流れる主電流が遮断されるときに、主電流のｄｉ／ｄｔと回路のインダクタンスでノイズが発生することは良く知られており、このノイズは素子自身の誤動作や周辺機器への誤動作を起こす原因となっている。その対策として、素子自身のノイズ耐量を上げることや、素子の外部にフェライトコア（磁気コア）などのノイズフィルターを挿入するといった対策が取られる。
A semiconductor switching element (hereinafter simply referred to as an element) includes a gate terminal (including a base signal here) to which a gate signal (including a base signal here) for mainly performing switching timing and a path through which a main current flows. It has three terminals, a + main terminal and a −main terminal, which are input / output terminals. When the gate signal is input, the element is switched, and the main current flows through the power path via the input / output terminal. At the time of switching, it is well known that noise is generated by the main current di / dt and the inductance of the circuit when the gate signal is turned off and the main current flowing through the element is cut off. This may cause malfunction of the device itself or malfunction of peripheral devices. As countermeasures, measures such as increasing the noise tolerance of the element itself and inserting a noise filter such as a ferrite core (magnetic core) outside the element are taken.

図４は、従来の半導体装置の要部平面図である。この半導体装置はＭＯＳＦＥＴ２００の場合である。
支持板５１上にＭＯＳＦＥＴチップ５２をはんだで固着し、ゲートパッド５４とゲート端子５７をボンディングワイヤ６１で接続し、ソースパッド５３とソース端子５６をボンディングワイヤ６０で接続する。支持板５１は図示しないＭＯＳＦＥＴチップ５２の裏面に形成されるドレイン電極と固着し、ドレイン端子５５と一体となっている。ＭＯＳＦＥＴチップ５２、支持板５１、ゲート端子５７の根元５９、ドレイン端子５５の根元５９、ソース端子５６の根元５９およびボンディングワイヤ６０，６１をモールド樹脂６２で封止して、ＭＯＳＦＥＴ２００が完成する。
図５は、図４の半導体装置にフェライトコアを固着したプリント基板の要部平面図である。このプリント基板７０にはゲート駆動回路などの周辺回路６４が形成されている。配線パターン６３が形成されたプリント基板７０にＭＯＳＦＥＴ２００のゲート端子５７、ドレイン端子５５およびソース端子５６のそれぞれの先端部を固着する。ドレイン端子５５と接続する配線にはフェライトコア５８が接続されている。このフェライトコア５８の接続によりＭＯＳＦＥＴ２００が遮断するときに発生するノイズを抑制することができる。 FIG. 4 is a plan view of an essential part of a conventional semiconductor device. This semiconductor device is a MOSFET 200.
The MOSFET chip 52 is fixed to the support plate 51 with solder, the gate pad 54 and the gate terminal 57 are connected by the bonding wire 61, and the source pad 53 and the source terminal 56 are connected by the bonding wire 60. The support plate 51 is fixed to the drain electrode formed on the back surface of the MOSFET chip 52 (not shown), and is integrated with the drain terminal 55. The MOSFET chip 52, the support plate 51, the root 59 of the gate terminal 57, the root 59 of the drain terminal 55, the root 59 of the source terminal 56, and the bonding wires 60 and 61 are sealed with the mold resin 62 to complete the MOSFET 200.
FIG. 5 is a plan view of a principal part of a printed circuit board in which a ferrite core is fixed to the semiconductor device of FIG. A peripheral circuit 64 such as a gate drive circuit is formed on the printed board 70. The tips of the gate terminal 57, the drain terminal 55, and the source terminal 56 of the MOSFET 200 are fixed to the printed circuit board 70 on which the wiring pattern 63 is formed. A ferrite core 58 is connected to the wiring connected to the drain terminal 55. By connecting the ferrite core 58, noise generated when the MOSFET 200 is cut off can be suppressed.

また、特許文献１には、ノイズフィルター用プリント基板とコントロール用プリント基板の間を接続する配線に挿入していたフェライトコアをノイズフィルター用プリント基板に接続して配線の交換作業を容易にした例が記載されている。
特開２００３−２２９６９２号公報 Patent Document 1 discloses an example in which a ferrite core inserted in a wiring connecting between a noise filter printed circuit board and a control printed circuit board is connected to the noise filter printed circuit board to facilitate wiring replacement work. Is described.
Japanese Patent Laid-Open No. 2003-229692

しかし、前記のノイズに耐えるように素子自身のノイズ耐量を向上させるためには開発コスト・期間がかかる。
また、素子の外部にノイズフィルターとしてフェライトコア５８を挿入するとフェライトコア５８の取り付け工数がかかりコストが増大する。さらにフェライトコア５８を取り付けるための面積（占有面積）が増加する。
この発明の目的は、前記の課題を解決して、小さな占有面積で、スイッチング動作時に発生するノイズを抑制できる半導体装置を提供することにある。 However, in order to improve the noise immunity of the device itself so as to withstand the noise, development cost and time are required.
Further, if the ferrite core 58 is inserted as a noise filter outside the element, the man-hour for attaching the ferrite core 58 is increased and the cost is increased. Furthermore, the area (occupied area) for attaching the ferrite core 58 increases.
An object of the present invention is to solve the above-described problems and provide a semiconductor device capable of suppressing noise generated during a switching operation with a small occupied area.

前記の目的を達成するために、支持台と、該支持台上に裏面主電極が固着する半導体チップと、前記支持台と接続する第１外部導出端子と、前記半導体チップの表面主電極とボンディングワイヤで接続する第２外部導出端子と、前記支持台、前記半導体チップ、前記ボンディングワイヤ、前記第１外部導出端子の一部および前記第２外部導出端子の一部を封止するモールド樹脂を具備する半導体装置において、
前記モールド樹脂内で少なくとも前記第１外部導出端子もしくは前記第２外部導出端子に磁気コアを挿入配置する構成とする。
また、支持台と、該支持台上に裏面主電極が固着する半導体チップと、前記支持台と接続する第１外部導出端子と、前記半導体チップの表面主電極とボンディングワイヤで接続する第２外部導出端子と、前記半導体チップの制御電極と接続する第３外部導出端子と、前記支持台、前記半導体チップ、前記ボンディングワイヤ、前記第１外部導出端子の一部、前記第２外部導出端子の一部および前記第３外部導出端子の一部を封止するモールド樹脂を具備する半導体装置において、
前記モールド樹脂内で少なくとも前記第１外部導出端子もしくは前記第２外部導出端子に磁気コアを挿入配置する構成とする。 To achieve the above object, a support base, a semiconductor chip having a back main electrode fixed on the support base, a first external lead terminal connected to the support base, and a front main electrode of the semiconductor chip and bonding A second external lead terminal connected by a wire; and a mold resin for sealing the support, the semiconductor chip, the bonding wire, a part of the first external lead terminal, and a part of the second external lead terminal. In the semiconductor device to
A magnetic core is inserted and disposed at least in the first external lead-out terminal or the second external lead-out terminal in the mold resin.
A support chip; a semiconductor chip having a back surface main electrode fixed on the support board; a first external lead terminal connected to the support board; and a second external terminal connected to the front surface main electrode of the semiconductor chip with a bonding wire. A lead terminal, a third external lead terminal connected to the control electrode of the semiconductor chip, the support, the semiconductor chip, the bonding wire, a part of the first external lead terminal, one of the second external lead terminals In a semiconductor device comprising a mold resin that seals a portion of the portion and the third external lead-out terminal,
A magnetic core is inserted and disposed at least in the first external lead-out terminal or the second external lead-out terminal in the mold resin.

また、前記第１外部導出端子もしくは前記第２外部導出端子の前記モールド樹脂内の個所に磁気コアが抜け出すことがないように突起が形成されているとよい。
また、前記磁気コアの中心部に前記第１外部導出端子もしくは前記第２外部導出端子が挿入できる大きさの穴が形成され、該穴に前記突起が通過できる大きさの凹部が形成されているとよいを特徴とする。
また、前記穴は、前記凹部がなければ前記突起が通過できない大きさの穴であるとよい。
また、前記磁気コアがフェライトコアであるとよい。 In addition, a protrusion may be formed so that the magnetic core does not come out at a location in the mold resin of the first external lead-out terminal or the second external lead-out terminal.
In addition, a hole having a size capable of inserting the first external lead-out terminal or the second external lead-out terminal is formed in a central portion of the magnetic core, and a recess having a size through which the protrusion can pass is formed in the hole. It is characterized by good.
Moreover, the said hole is good in it being a hole of the magnitude | size which cannot pass the said protrusion if there is no said recessed part.
The magnetic core may be a ferrite core.

この発明によれば、主電流が流れる経路にフェライトコア（フィルター）を入れることでスイッチング動作時に発生するノイズを抑制できる。その結果、素子自身の誤動作と周辺回路の誤動作を抑制することができる。
また、フェライトコアを樹脂内に内蔵させることで、従来フェライトコアで必要とされる占有面積を減じることができる。その結果、周辺回路の面積を減少させることができる。 According to the present invention, noise generated during the switching operation can be suppressed by inserting the ferrite core (filter) in the path through which the main current flows. As a result, malfunction of the element itself and malfunction of the peripheral circuit can be suppressed.
In addition, by incorporating the ferrite core in the resin, it is possible to reduce the area occupied by the conventional ferrite core. As a result, the area of the peripheral circuit can be reduced.

実施の形態を以下の実施例で説明する。   Embodiments will be described in the following examples.

図１は、この発明の第１実施例の半導体装置の構成図であり、同図（ａ）は要部平面図、同図（ｂ）はドレイン端子の拡大図、同図（ｃ）は同図（ｂ）のＸ―Ｘ線で切断した断面図、同図（ｄ）はフェライトコアの要部平面図である。この半導体装置はＭＯＳＦＥＴ１００を例に挙げたがＩＧＢＴ（絶縁ゲート型バイポーラトランジスタ）やバイポーラトランジスタなどであっても構わない。
支持板１上にＭＯＳＦＥＴチップ２の裏面の図示しないドレイン電極をはんだで固着し、ゲートパッド４とゲート端子６をボンディングワイヤ１１（アルミニウムワイヤなど）で接続し、ソースパッド３とソース端子６をボンディングワイヤ１０で接続する。ゲートパッド４は図示しないＭＯＳＦＥＴチップ２のゲート電極と接続し、ソースパッド３は図示しないＭＯＳＦＥＴチップ２のソース電極と接続する。支持板１はドレイン電極と固着し、ドレイン端子５と一体となっている。ドレイン端子５にフェライトコア８を挿入する。フェライトコア８の中心にはソース端子５が挿入できる大きさの貫通孔１３が形成されている。ドレイン端子５の幅をａとし、ドレイン端子５の厚さをｂとし、貫通孔１３の横幅をｃとし、貫通孔１３の縦幅をｄとしたとき、ａ＜ｃ，ｂ＜ｄとする。また貫通孔１３を円形の貫通孔孔１３ａとした場合、その円の直径をｃとしたとき、ａ＜ｃとする。またフェライトコア８の外径をＤ、図５に示すようにモールド樹脂１２の厚さＬとしたとき、Ｄ＜Ｌとする。 FIG. 1 is a block diagram of a semiconductor device according to a first embodiment of the present invention. FIG. 1 (a) is a plan view of a main part, FIG. 1 (b) is an enlarged view of a drain terminal, and FIG. Sectional drawing cut | disconnected by the XX line | wire of the figure (b), The figure (d) is a principal part top view of a ferrite core. The semiconductor device is exemplified by the MOSFET 100, but may be an IGBT (Insulated Gate Bipolar Transistor) or a bipolar transistor.
A drain electrode (not shown) on the back surface of the MOSFET chip 2 is fixed on the support plate 1 with solder, the gate pad 4 and the gate terminal 6 are connected by a bonding wire 11 (such as an aluminum wire), and the source pad 3 and the source terminal 6 are bonded. Connect with wire 10. The gate pad 4 is connected to the gate electrode of the MOSFET chip 2 (not shown), and the source pad 3 is connected to the source electrode of the MOSFET chip 2 (not shown). The support plate 1 is fixed to the drain electrode and is integrated with the drain terminal 5. A ferrite core 8 is inserted into the drain terminal 5. At the center of the ferrite core 8, a through hole 13 having a size capable of inserting the source terminal 5 is formed. When the width of the drain terminal 5 is a, the thickness of the drain terminal 5 is b, the lateral width of the through hole 13 is c, and the vertical width of the through hole 13 is d, a <c and b <d. When the through hole 13 is a circular through hole 13a, a <c, where c is the diameter of the circle. When the outer diameter of the ferrite core 8 is D and the thickness L of the mold resin 12 is as shown in FIG.

ＭＯＳＦＥＴチップ２、支持板１、ゲート端子７の根元９、ドレイン端子５の根元９、ソース端子６の根元８およびフェライトコア８およびボンディングワイヤ１０，１１をモールド樹脂１２で封止して、本発明のＭＯＳＦＥＴ１００が完成する。
このように、フェライトコア８をモールド樹脂１２内に内蔵させることで、図５で示す従来のＭＯＳＦＥＴ２００の占有面積を増加させることなく、従来のフェライトコア５８の占有面積を減じることができる。その結果、周辺回路６４の占有面積を減少させることができる。
またプリント基板７０に搭載する従来のフェライトコア５８の取り付け工数が削除できて、製造コストを減少することができる。
また、この第１実施例では、ドレイン端子５にフェライトコア８を挿入したが、ソース端子６側に挿入してもよく、さらに両端子５，６に挿入してもよい。 The MOSFET chip 2, the support plate 1, the root 9 of the gate terminal 7, the root 9 of the drain terminal 5, the root 8 of the source terminal 6, the ferrite core 8, and the bonding wires 10 and 11 are sealed with a mold resin 12. The MOSFET 100 is completed.
Thus, by incorporating the ferrite core 8 in the mold resin 12, the occupation area of the conventional ferrite core 58 can be reduced without increasing the occupation area of the conventional MOSFET 200 shown in FIG. As a result, the area occupied by the peripheral circuit 64 can be reduced.
Further, the number of steps for attaching the conventional ferrite core 58 mounted on the printed circuit board 70 can be eliminated, and the manufacturing cost can be reduced.
Further, in this first embodiment, the ferrite core 8 is inserted into the drain terminal 5, but it may be inserted into the source terminal 6 side and further inserted into both terminals 5, 6.

尚、この第１実施例ではスイッチング素子を例に挙げて説明したが、ダイオードのアノード端子やカソード端子にフェライトコア８を挿入した場合もダイオードの逆回復動作時に発生するノイズを低減することができる。   In the first embodiment, the switching element has been described as an example. However, even when the ferrite core 8 is inserted into the anode terminal or the cathode terminal of the diode, noise generated during the reverse recovery operation of the diode can be reduced. .

図２は、この発明の第２実施例の半導体装置の構成図であり、同図（ａ）は要部平面図、同図（ｂ）はドレイン端子の拡大図、同図（ｃ）は同図（ｂ）のＸ―Ｘ線で切断した断面図、同図（ｄ）はフェライトコアの要部平面図である。第１実施例との違いは、フェライトコア８がモールド樹脂１２で封止されるとき、ドレイン端子５から抜けないようにドレイン端子５に突起部１４を設けた点である。
フェライトコア８の中心部の貫通孔１５にドレイン端子５の幅ａより多少大きい貫通孔１５と、ドレイン端子５に抜け落ち防止のために形成した突起部１４が通過できるよう広げた個所（凹部１６）を設ける。ドレイン端子５の横幅をａ、ドレイン端子５の厚みをｆ、突起部１４間の幅をｅ、フェライトコア８の第１幅をｈ、第２幅をｇ、凹部１６の幅をｋとしたとき、ａ＜ｈ＜ｅ、ｅ＜ｇ、ｆ＜ｋとするとよい。また、Ｄ＜Ｌとする。 2A and 2B are configuration diagrams of a semiconductor device according to a second embodiment of the present invention, in which FIG. 2A is a plan view of an essential part, FIG. 2B is an enlarged view of a drain terminal, and FIG. Sectional drawing cut | disconnected by the XX line | wire of the figure (b), The figure (d) is a principal part top view of a ferrite core. The difference from the first embodiment is that a protrusion 14 is provided on the drain terminal 5 so that the ferrite core 8 is not detached from the drain terminal 5 when the ferrite core 8 is sealed with the mold resin 12.
A portion (recess 16) widened so that a through hole 15 slightly larger than the width a of the drain terminal 5 and a projection 14 formed to prevent the drain terminal 5 from falling off can pass through the through hole 15 in the center of the ferrite core 8. Is provided. When the lateral width of the drain terminal 5 is a, the thickness of the drain terminal 5 is f, the width between the protrusions 14 is e, the first width of the ferrite core 8 is h, the second width is g, and the width of the recess 16 is k. , A <h <e, e <g, f <k. Further, D <L.

フェライトコア８をドレイン端子５に挿入する仕方は、突起部１４を凹部１６が通過できるようにフェライトコア８の位置決めをし、突起部１４を凹部１６が通過した後、フェライトコア８を回転させて、突起部１４の位置から凹部１６の位置をずらす。こうすると、フェライトコア８は突起部１４に引っかかってドレイン端子８から抜けることがなく、また、モールド樹脂１２からはみ出すことがなくなる。
ここでは、突起部１４を２個で凹部１６が４個の場合を例に挙げて説明したが、凹部１６は対角線上のみの２個であっても構わない。
また、突起部を１個とした場合は、凹部は１個以上あればよい。
また、実施例では貫通孔１５を正方形としたが、図1（ｄ）の点線で示す貫通孔１３ａのように円形としてその周囲に凹部を設けても構わない。 The ferrite core 8 is inserted into the drain terminal 5 by positioning the ferrite core 8 so that the concave portion 16 can pass through the protruding portion 14 and rotating the ferrite core 8 after the concave portion 16 passes through the protruding portion 14. The position of the recess 16 is shifted from the position of the protrusion 14. In this way, the ferrite core 8 is not caught by the protrusion 14 and does not come out of the drain terminal 8 and does not protrude from the mold resin 12.
Here, the case where the number of the protrusions 14 is two and the number of the recesses 16 is four is described as an example.
Further, when there is one protrusion, it is sufficient that there are one or more recesses.
In the embodiment, the through-hole 15 is square, but it may be circular as in the through-hole 13a shown by the dotted line in FIG.

また、図２（ｄ）に示す凹部１６を設けないで、貫通孔１５の正方形の対角線の長さをｅより大きくしてもよい。
また、貫通孔１５を長方形にして、その対角線の長さをｅより大きくし、長辺の長さをａより大きく、ｅより小さくしてもよい。 Moreover, the length of the diagonal of the square of the through-hole 15 may be made larger than e, without providing the recessed part 16 shown in FIG.2 (d).
Alternatively, the through hole 15 may be rectangular, the length of the diagonal line may be greater than e, and the length of the long side may be greater than a and less than e.

図３は、この発明の第３実施例の半導体装置のフェライトコアの要部平面図である。図２と異なる点は、フェライトコア８を２個に分割し、ドレイン端子を半月状のフェライト１７、１８でドレイン端子５を挟んで半月状のフェライト１７、１８同士を接着材１９で固着した点である。フェライトコア８の貫通孔２０の直径をｍとすると、ａ＜ｍ＜ｅとする。
また、フェライトをコノ字型に形成し、それを突き合わせて接着して、貫通孔を四角形に形成してもよい。この場合、貫通孔の短辺長がｆより大きく、対角線長がｅより小さくなるようにしておけばよい。
前記の第２実施例および第３実施例の場合も第１実施例と同様の効果が得られる。 FIG. 3 is a plan view of an essential part of the ferrite core of the semiconductor device according to the third embodiment of the present invention. The difference from FIG. 2 is that the ferrite core 8 is divided into two parts, and the drain terminal is sandwiched between the half-moon ferrites 17 and 18 and the half-moon ferrites 17 and 18 are fixed to each other with the adhesive 19. It is. When the diameter of the through hole 20 of the ferrite core 8 is m, a <m <e.
Further, the through holes may be formed in a quadrangular shape by forming the ferrite in a cono-shaped shape and bonding them together. In this case, the short side length of the through hole may be larger than f and the diagonal length may be smaller than e.
In the case of the second and third embodiments, the same effect as that of the first embodiment can be obtained.

この発明の第１実施例の半導体装置の構成図であり、（ａ）は要部平面図、（ｂ）はドレイン端子の拡大図、（ｃ）は（ｂ）のＸ―Ｘ線で切断した断面図、（ｄ）はフェライトコアの要部平面図BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram of the semiconductor device of 1st Example of this invention, (a) is a principal part top view, (b) is an enlarged view of a drain terminal, (c) is cut | disconnected by the XX line of (b) Sectional view, (d) is a plan view of the main part of the ferrite core この発明の第２実施例の半導体装置の構成図であり、（ａ）は要部平面図、（ｂ）はドレイン端子の拡大図、（ｃ）は（ｂ）のＸ―Ｘ線で切断した断面図、（ｄ）はフェライトコアの要部平面図It is a block diagram of the semiconductor device of 2nd Example of this invention, (a) is a principal part top view, (b) is an enlarged view of a drain terminal, (c) is cut | disconnected by the XX line of (b) Sectional view, (d) is a plan view of the main part of the ferrite core この発明の第３実施例の半導体装置のフェライトコアの要部平面図The principal part top view of the ferrite core of the semiconductor device of 3rd Example of this invention 従来の半導体装置の要部平面図Plan view of main part of conventional semiconductor device 図４の半導体装置にフェライトコアを固着したプリント基板の要部平面図FIG. 4 is a plan view of a principal part of a printed circuit board in which a ferrite core is fixed to the semiconductor device of FIG.

符号の説明Explanation of symbols

１ 支持板
２ ＭＯＳＦＥＴチップ
３ ソースパッド
４ ゲートパッド
５ ドレイン端子
６ ソース端子
７ ゲート端子
８ フェライトコア
９ 根元
１０、１１ ボンディングワイヤ
１２ モールド樹脂
１３、１３ａ、１５、２０ 貫通孔
１４ 突起部
１６ 凹部
１７、１８ 半月状のフェライト
１９ 接着材
１００ ＭＯＳＦＥＴ DESCRIPTION OF SYMBOLS 1 Support plate 2 MOSFET chip 3 Source pad 4 Gate pad 5 Drain terminal 6 Source terminal 7 Gate terminal 8 Ferrite core 9 Base 10, 11 Bonding wire 12 Mold resin 13, 13a, 15, 20 Through-hole 14 Protrusion 16 Recess 17, 18 Half-moon shaped ferrite 19 Adhesive 100 MOSFET

Claims (6)

支持台と、該支持台上に裏面主電極が固着する半導体チップと、前記支持台と接続する第１外部導出端子と、前記半導体チップの表面主電極とボンディングワイヤで接続する第２外部導出端子と、前記支持台、前記半導体チップ、前記ボンディングワイヤ、前記第１外部導出端子の一部および前記第２外部導出端子の一部を封止するモールド樹脂を具備する半導体装置において、
前記モールド樹脂内で少なくとも前記第１外部導出端子もしくは前記第２外部導出端子に磁気コアを挿入配置することを特徴とする半導体装置。 A support chip, a semiconductor chip having a back main electrode fixed on the support board, a first external lead terminal connected to the support base, and a second external lead terminal connected to the front main electrode of the semiconductor chip with a bonding wire And a semiconductor device comprising a mold resin for sealing the support, the semiconductor chip, the bonding wire, a part of the first external lead-out terminal, and a part of the second external lead-out terminal,
A semiconductor device, wherein a magnetic core is inserted and disposed at least in the first external lead-out terminal or the second external lead-out terminal in the mold resin. 支持台と、該支持台上に裏面主電極が固着する半導体チップと、前記支持台と接続する第１外部導出端子と、前記半導体チップの表面主電極とボンディングワイヤで接続する第２外部導出端子と、前記半導体チップの制御電極と接続する第３外部導出端子と、前記支持台、前記半導体チップ、前記ボンディングワイヤ、前記第１外部導出端子の一部、前記第２外部導出端子の一部および前記第３外部導出端子の一部を封止するモールド樹脂を具備する半導体装置において、
前記モールド樹脂内で少なくとも前記第１外部導出端子もしくは前記第２外部導出端子に磁気コアを挿入配置することを特徴とする半導体装置。 A support chip, a semiconductor chip having a back main electrode fixed on the support board, a first external lead terminal connected to the support base, and a second external lead terminal connected to the front main electrode of the semiconductor chip with a bonding wire A third external lead terminal connected to the control electrode of the semiconductor chip, the support, the semiconductor chip, the bonding wire, a part of the first external lead terminal, a part of the second external lead terminal, and In a semiconductor device comprising a mold resin for sealing a part of the third external lead-out terminal,
A semiconductor device, wherein a magnetic core is inserted and disposed at least in the first external lead-out terminal or the second external lead-out terminal in the mold resin. 前記第１外部導出端子もしくは前記第２外部導出端子の前記モールド樹脂内の個所に磁気コアが抜け出すことがないように突起が形成されていることを特徴とする請求項１または２に記載の半導体装置。 3. The semiconductor according to claim 1, wherein a protrusion is formed so that the magnetic core does not come out at a position in the mold resin of the first external lead-out terminal or the second external lead-out terminal. apparatus. 前記磁気コアの中心部に前記第１外部導出端子もしくは前記第２外部導出端子が挿入できる大きさの穴が形成され、該穴に前記突起が通過できる大きさの凹部が形成されていることを特徴とする請求項３に記載の半導体装置。 A hole having a size capable of inserting the first external lead-out terminal or the second external lead-out terminal is formed in a central portion of the magnetic core, and a recess having a size capable of passing the protrusion is formed in the hole. The semiconductor device according to claim 3. 前記穴は、前記凹部がなければ前記突起が通過できない大きさの穴であることを特徴とする請求項４に記載の半導体装置。 The semiconductor device according to claim 4, wherein the hole is a hole having a size in which the protrusion cannot pass without the recess. 前記磁気コアがフェライトコアであることを特徴とする請求項１〜５のいずれか一項に記載の半導体装置。 The semiconductor device according to claim 1, wherein the magnetic core is a ferrite core.
JP2005348602A 2005-12-02 2005-12-02 Semiconductor device Withdrawn JP2007157862A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019121745A (en) * 2018-01-11 2019-07-22 ローム株式会社 Semiconductor device and mounting structure of the same
WO2023157604A1 (en) * 2022-02-15 2023-08-24 ローム株式会社 Semiconductor device and package structure of semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03283559A (en) * 1990-03-30 1991-12-13 Toshiba Lighting & Technol Corp Electronic component

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03283559A (en) * 1990-03-30 1991-12-13 Toshiba Lighting & Technol Corp Electronic component

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019121745A (en) * 2018-01-11 2019-07-22 ローム株式会社 Semiconductor device and mounting structure of the same
JP7018319B2 (en) 2018-01-11 2022-02-10 ローム株式会社 Semiconductor device
WO2023157604A1 (en) * 2022-02-15 2023-08-24 ローム株式会社 Semiconductor device and package structure of semiconductor device

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