JP2007081146A - Semiconductor device with inductor - Google Patents

Semiconductor device with inductor Download PDF

Info

Publication number
JP2007081146A
JP2007081146A JP2005267268A JP2005267268A JP2007081146A JP 2007081146 A JP2007081146 A JP 2007081146A JP 2005267268 A JP2005267268 A JP 2005267268A JP 2005267268 A JP2005267268 A JP 2005267268A JP 2007081146 A JP2007081146 A JP 2007081146A
Authority
JP
Japan
Prior art keywords
inductor
semiconductor device
semiconductor chip
thin
conductive plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2005267268A
Other languages
Japanese (ja)
Other versions
JP2007081146A5 (en
Inventor
Osamu Hirohashi
修 広橋
Tomonori Seki
知則 関
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Device Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Device Technology Co Ltd filed Critical Fuji Electric Device Technology Co Ltd
Priority to JP2005267268A priority Critical patent/JP2007081146A/en
Publication of JP2007081146A publication Critical patent/JP2007081146A/en
Publication of JP2007081146A5 publication Critical patent/JP2007081146A5/ja
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Coils Or Transformers For Communication (AREA)
  • Dc-Dc Converters (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a low-profile semiconductor device with an inductor which is small at a low cost. <P>SOLUTION: A terminal 3a of a laminated inductor 3 is bonded on a support conductive plate 4 using an Ag paste 6. A semiconductor chip 1 is bonded on the laminated inductor 3 by way of an insulating DAF tape 7. One end of the support conductive plate 4 is connected to a terminal electrode 2 of the semiconductor chip 1 using a gold wire 8. A plurality of terminal electrodes 2 of the semiconductor chip 1 are connected respectively to a plurality of external lead-out terminals 5 provided separately using a laterally drawn gold wire 8, and the entire is sealed with a resin mode 9. By using the laminated inductor 3 with the gold wire 8 drawn laterally, the semiconductor device of an inductor is reduced in thickness. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

この発明は、携帯型電子機器などに搭載されるＤＣ／ＤＣコンバータを構成する半導体装置であって、集積回路を形成した半導体チップと薄型インダクタを積層した小型で薄型のインダクタ付半導体装置に関する。   The present invention relates to a semiconductor device constituting a DC / DC converter mounted on a portable electronic device or the like, and relates to a small and thin semiconductor device with an inductor in which a semiconductor chip on which an integrated circuit is formed and a thin inductor are laminated.

携帯電話、デジタルカメラおよびデジタルビデオカメラに代表される携帯型電子機器に使用される分散型電源ＩＣ、もしくは集中型電源の不足分を補う個別電源ＩＣは、出力部と制御部の集積回路を形成した電源ＩＣチップをリードフレームまたは基板にダイボンディングし、金線によりリードフレームのリード端子又は基板の端子にワイヤボンディングし、樹脂封止した構造をしている。この電源ＩＣとは別にインダクタやコンデンサなどを外付けで設置してＤＣ／ＤＣコンバータが構成される。
図７は、従来のＤＣ／ＤＣコンバータの要部断面図である。これは、電源ＩＣなどの半導体チップ５１、インタクタ５３および図示しないコンデンサ、抵抗などをプリント基板６１に実装した場合の構成図である。
半導体チップ５１を支持導板５４上にＡｇペースト５６を介して固着し、半導体チップ５４の端子電極５２と外部導出端子５５を金ワイヤ５８で接続し、樹脂モールド５９で封止して、電源ＩＣが形成される。この電源ＩＣの支持導板５４と外部導出端子５５の裏面をプリント基板６１の導電パターン６２にはんだ６３で固着し、またインダクタ５３の端子５３をプリント基板６１の導電パターン６２にはんだ６３で固着する。その他、図示しないコンデンサや抵抗をプリント基板６１の導電パターン６２に固着する。このインダクタ５３は積層インダクタもしくは渦巻き型インダクタ、ソレノイドインダクタやトロイダルインダクタなどの平型インダクタである。 Distributed power supply ICs used in portable electronic devices such as mobile phones, digital cameras, and digital video cameras, or individual power supply ICs that make up for the shortage of centralized power supplies form an integrated circuit for output and control The power supply IC chip is die-bonded to a lead frame or substrate, wire-bonded to a lead frame lead terminal or substrate terminal using a gold wire, and sealed with resin. In addition to the power supply IC, an inductor, a capacitor, and the like are installed externally to constitute a DC / DC converter.
FIG. 7 is a cross-sectional view of a main part of a conventional DC / DC converter. This is a configuration diagram in the case where a semiconductor chip 51 such as a power supply IC, an interactor 53, a capacitor (not shown), a resistor, and the like are mounted on a printed board 61.
The semiconductor chip 51 is fixed on the support conductive plate 54 via an Ag paste 56, the terminal electrode 52 of the semiconductor chip 54 and the external lead-out terminal 55 are connected with a gold wire 58, sealed with a resin mold 59, and the power IC Is formed. The back surface of the support conductive plate 54 and the external lead-out terminal 55 of the power supply IC is fixed to the conductive pattern 62 of the printed circuit board 61 with the solder 63, and the terminal 53 of the inductor 53 is fixed to the conductive pattern 62 of the printed circuit board 61 with the solder 63. . In addition, a capacitor and a resistor (not shown) are fixed to the conductive pattern 62 of the printed circuit board 61. The inductor 53 is a flat inductor such as a multilayer inductor, a spiral inductor, a solenoid inductor, or a toroidal inductor.

このＤＣ／ＤＣコンバータでは電源ＩＣチップである半導体チップ５１とインダクタ５３がプリント基板６１上に併設されるため、厚さは小さいが占有面積が大きくなる。そのため、このＤＣ／ＤＣコンバーダを厚さを小さくしながら小型化（占有面積の低減）することは、携帯型電子機器に搭載する場合に重要となる。
また、小型化という観点からは、多機能を有するシステムＬＳＩにおいても同様である。
システムＬＳＩにおいては、多数の機能を１チップに集約すると、半導体チップの面積が大きくなり大型化する。そこでシステムＬＳＩを複数のＬＳＩチップを積層して樹脂にて封止して形成し小型化を図ることが報告されている。
これは半導体チップ上に小さな半導体チップを積層したチップ・オン・チップであり、大きなＬＳＩチップの主表面にリードとの接続用のパッド電極と内部インターフェース用の第１パッド電極を設け、この主表面上に配置される小さなＬＳＩチップの第２パッド電極と第１パッド電極をワイヤにて電気的に接続することで、大きなＬＳＩチップの代わりに、システムＬＳＩとしての必要な回路の一部を小さなＬＳＩチップに搭載し、２つのＬＳＩチップにて所望のシステムＬＳＩとしての機能を実現するものである（例えば、特許文献１など）。 In this DC / DC converter, the semiconductor chip 51, which is a power supply IC chip, and the inductor 53 are provided on the printed circuit board 61. Therefore, although the thickness is small, the occupied area is large. For this reason, downsizing the DC / DC converter while reducing the thickness (reducing the occupied area) is important when it is mounted on a portable electronic device.
Further, from the viewpoint of miniaturization, the same applies to a multi-function system LSI.
In a system LSI, when a large number of functions are integrated into one chip, the area of the semiconductor chip increases and the size increases. Therefore, it has been reported that a system LSI is formed by laminating a plurality of LSI chips and sealing them with a resin to reduce the size.
This is a chip-on-chip in which a small semiconductor chip is stacked on a semiconductor chip. A pad electrode for connection with a lead and a first pad electrode for an internal interface are provided on the main surface of a large LSI chip. By electrically connecting the second pad electrode and the first pad electrode of a small LSI chip arranged above with a wire, a part of a necessary circuit as a system LSI can be replaced with a small LSI instead of a large LSI chip. It is mounted on a chip, and functions as a desired system LSI are realized by two LSI chips (for example, Patent Document 1).

また、コイル（インダクタ）やトランスなどの磁気誘導部品を平面型として小型化し、半導体装置を作り込んだ半導体基板上への搭載方法を改良して、超小型電力変換装置（超小型のＤＣ／ＤＣコンバータ）を実現することが報告されている（例えば、特許文献２など）。
また、積層セラミックコンデンサ上にトロイダル状の無端ソレノイドの薄膜インダクタを積層し、さらにその上に半導体チップをスタッドバンプで固着した超小型電力変換装置（超小型のＤＣ／ＤＣコンバータ）が報告されている（例えば、特許文献３など）。
特開２００４−７０１７号公報 特開平１１−２５１１５７号公報 特開２００４−７０１７号公報 In addition, magnetic induction parts such as coils (inductors) and transformers are reduced in size to a flat type, and the mounting method on a semiconductor substrate on which a semiconductor device is built is improved. It has been reported that a converter is realized (for example, Patent Document 2).
In addition, a micro power converter (ultra-small DC / DC converter) in which a toroidal endless solenoid thin film inductor is laminated on a multilayer ceramic capacitor and a semiconductor chip is fixed thereon with stud bumps has been reported. (For example, patent document 3 etc.).
JP 2004-7017 A Japanese Patent Laid-Open No. 11-251157 JP 2004-7017 A

前記の携帯型電子機器は、さらなる小型化、薄型化および低価格化が求められている。そのため、機器に内蔵される電源ＩＣチップやインダクタなどの部品とこれを実装するためのプリント基板の小型化、薄型化および低コスト化が強く要求されている。
また、前記特許文献１では、半導体チップ上に半導体チップを積層する構造であり、インダクタと半導体チップを積層した構造については触れられていない。
また、前記特許文献２や特許文献３では、半導体チップと薄型のインダクタをスタッドバンプで固着して積層することで構造としているが、積層するために図７の構造と比べる面積は小さくなるが厚みが厚くなる。
また、半導体チップの外周部に形成したスタッドパンブとインダクタの外周部に形成した端子電極とを固着するために、半導体チップとインダクタの大きさを合わせなければならず、例えば、活性領域が小さな半導体チップで特性的に十分であっても、インダクタの大きさに合わせて大きな半導体チップが必要となり低コスト化することが困難になる。また、スタッドバンプの形成工程は複雑であり製造コストは高い。 The portable electronic device is required to be further reduced in size, thickness, and price. Therefore, there is a strong demand for miniaturization, thinning, and cost reduction of components such as a power IC chip and an inductor built in the device and a printed circuit board on which the components are mounted.
In Patent Document 1, a structure in which a semiconductor chip is stacked on a semiconductor chip is described, and a structure in which an inductor and a semiconductor chip are stacked is not mentioned.
In Patent Document 2 and Patent Document 3, the semiconductor chip and the thin inductor are fixed and stacked with the stud bumps. However, the thickness is smaller than the structure of FIG. Becomes thicker.
Further, in order to fix the stud bump formed on the outer peripheral portion of the semiconductor chip and the terminal electrode formed on the outer peripheral portion of the inductor, the sizes of the semiconductor chip and the inductor must be matched. For example, the semiconductor chip having a small active region Even if the characteristics are sufficient, a large semiconductor chip is required according to the size of the inductor, making it difficult to reduce the cost. Further, the stud bump forming process is complicated and the manufacturing cost is high.

この発明の目的は、前記の課題を解決し、小型および薄型で低コストのインダクタ付半導体装置を提供することである。   SUMMARY OF THE INVENTION An object of the present invention is to solve the above-described problems and provide a semiconductor device with an inductor that is small, thin, and low in cost.

この発明により、絶縁性ＤＡＦテープで半導体チップと薄型インダクタを固着したものを導電板に固着し、半導体チップに形成した端子電極、薄型インダクタに形成した端子電極およびパッケージの外部導電端子とをそれぞれボンディングワイヤで接続することで、小型で薄型である低コストのインダクタ付半導体装置を製造することができる。
また、インダクタに０．６ｍｍ厚以下の積層インダクタを用い、ボンディングワイヤを横取り出しすることで、高さが１．２ｍｍ以下の薄型のインダクタ付半導体装置を製造することができる。
このインダクタ付半導体装置を用いることで、ＤＣ／ＤＣコンバータおよびこのＤＣ／ＤＣコンバータを搭載した携帯型電子機器の薄型化、小型化および低コスト化を図ることができる。 According to the present invention, a semiconductor chip and a thin inductor fixed with an insulating DAF tape are fixed to a conductive plate, and a terminal electrode formed on the semiconductor chip, a terminal electrode formed on the thin inductor, and an external conductive terminal of the package are bonded to each other. By connecting with a wire, a small and thin low-cost inductor-equipped semiconductor device can be manufactured.
Moreover, a thin semiconductor device with an inductor having a height of 1.2 mm or less can be manufactured by using a laminated inductor having a thickness of 0.6 mm or less as the inductor and taking out the bonding wire laterally.
By using this semiconductor device with an inductor, it is possible to reduce the thickness, size and cost of a DC / DC converter and a portable electronic device equipped with this DC / DC converter.

また、電源ＩＣチップを覆う様にインダクタが設置されているため、外部からのノイズをインダクタを形成しているフェライト基板が吸収し、外部ノイズに対しては耐ノイズ性にすぐれたＤＣ／ＤＣコンバータを構成することができる。   In addition, since the inductor is installed so as to cover the power supply IC chip, the ferrite substrate forming the inductor absorbs external noise, and the DC / DC converter has excellent noise resistance against external noise. Can be configured.

前記の目的を達成するために、半導体チップと、薄型インダクタとを積層したインダクタ付半導体装置であって、支持導板上に薄型インダクタを第１の固着材で固着し、前記薄型インダクタ上に前記半導体チップを第２の固着材で固着する、もしくは前記支持基板上に前記半導体チップを第１の固着材で固着し、前記半導体チップ上に前記薄膜インダクタを第２の固着材で固定し、前記半導体チップ上に形成した端子電極と前記支持導板もしくは前記薄膜インダクタに設けられたインダクタ端子、並びに前記端子電極と外部導出端子とをそれぞれ導線で接続した構成とする。
また、前記薄型インダクタは、積層インダクタであるとよい。
また、前記積層インダクタは、高さ方向にスパイラル状に巻かれたコイルを磁性絶縁部材に埋め込んで形成されるとよい。 In order to achieve the above object, a semiconductor device with an inductor in which a semiconductor chip and a thin inductor are laminated, the thin inductor is fixed on a supporting conductive plate with a first fixing material, and the thin inductor is fixed on the thin inductor. Fixing the semiconductor chip with a second fixing material, or fixing the semiconductor chip on the support substrate with a first fixing material, fixing the thin film inductor on the semiconductor chip with a second fixing material, and A terminal electrode formed on a semiconductor chip, an inductor terminal provided on the supporting conductive plate or the thin film inductor, and a terminal electrode and an external lead terminal are connected by conductive wires.
The thin inductor may be a multilayer inductor.
The multilayer inductor may be formed by embedding a coil wound in a spiral shape in the height direction in a magnetic insulating member.

また、前記積層インダクタの高さが、０．６ｍｍ以下であるとよい。
また、前記第１の固着材が前記薄膜インダクタと前記支持導板とを固着する場合には導電性接着材であり、前記半導体チップと前記支持導板とを固着する場合には導電性接着材もしくは絶縁性接着材であり、前記第２の固着材が絶縁性接着材であるとよい。
また、前記導電性接着材がＡｇベーストもしくははんだであるとよい。
また、前記絶縁性接着材が絶縁性ＤＡＦ（Ｄｉｅ Ａｔｔａｃｈ Ｆｉｌｍ）であるとよい。
また、前記支持導板と前記薄型インダクタと前記薄型インダクタと前記導線と前記外部導出端子とを前記支持導板の裏面と前記外部導出端子の裏面が露出するように樹脂モールドで封止するとよい。 The height of the multilayer inductor is preferably 0.6 mm or less.
The first fixing material is a conductive adhesive when the thin film inductor and the support conductive plate are fixed, and the first adhesive is a conductive adhesive when the semiconductor chip and the support conductive plate are fixed. Alternatively, it is an insulating adhesive, and the second fixing material is preferably an insulating adhesive.
The conductive adhesive is preferably Ag-based or solder.
The insulating adhesive material may be an insulating DAF (Die Attach Film).
Further, the support conductive plate, the thin inductor, the thin inductor, the conductive wire, and the external lead terminal may be sealed with a resin mold so that the back surface of the support conductive plate and the back surface of the external lead terminal are exposed.

また、前記支持導板裏面から前記樹脂モールドの上面までの高さが１．２ｍｍ以下であるとよい。
また、前記導線が金ワイヤもしくはアルミワイヤであるとよい。 Moreover, it is good in the height from the said support conducting plate back surface to the upper surface of the said resin mold being 1.2 mm or less.
Moreover, the said conducting wire is good in it being a gold wire or an aluminum wire.

実施の形態を以下の実施例にて説明する。   Embodiments will be described in the following examples.

図１は、この発明の第１実施例のインダクタ付半導体装置の構成図であり、同図（ａ）は要部斜視図、同図（ｂ）は同図（ａ）のＸ−Ｘ線で切断した要部断面図である。
支持導板４上に積層インダクタ３の端子３ａをＡｇベースト６で固着し、積層インダクタ３上に半導体チップ１を絶縁性ＤＡＦテープ７を介して固着する。支持導板４の一端は外部導出端子５の役目をしており、この支持導板４の一端（外部導出端子５）と半導体チップ１の端子電極２を金ワイヤ８で接続する。また半導体チップ１の複数の端子電極２と個別に設けた複数の外部導出端子５を金ワイヤ８でそれぞれ接続する。これら全体を樹脂モールド９で封止する。半導体チップ１の端子電極２に固着した金ワイヤ８は半導体チップ１面と平行になるように横出しして外部導出端子５と接続する。尚、Ａｇペースト６の代わりにはんだでもよい。また、金ワイヤ８の代わりにアルミワイヤを用いても構わない。 FIG. 1 is a block diagram of a semiconductor device with an inductor according to a first embodiment of the present invention, in which FIG. 1 (a) is a perspective view of the main part and FIG. 1 (b) is taken along line XX in FIG. 1 (a). It is the principal part sectional drawing cut | disconnected.
The terminal 3 a of the multilayer inductor 3 is fixed on the supporting conductive plate 4 with an Ag base 6, and the semiconductor chip 1 is fixed on the multilayer inductor 3 via an insulating DAF tape 7. One end of the support conductive plate 4 serves as an external lead-out terminal 5, and one end (external lead-out terminal 5) of the support conductive plate 4 and the terminal electrode 2 of the semiconductor chip 1 are connected by a gold wire 8. A plurality of terminal electrodes 2 of the semiconductor chip 1 and a plurality of external lead-out terminals 5 provided individually are respectively connected by gold wires 8. These are entirely sealed with a resin mold 9. The gold wire 8 fixed to the terminal electrode 2 of the semiconductor chip 1 is laterally extended so as to be parallel to the surface of the semiconductor chip 1 and connected to the external lead-out terminal 5. Note that solder may be used instead of the Ag paste 6. Further, an aluminum wire may be used instead of the gold wire 8.

前記の支持導板４や外部導出端子５は、図２に示すリードフレーム１０に積層インダクタ３を固着しその上に半導体チップ１を固着し、金ワイヤ８をボンディングした後、樹脂モールド９で封止し、不要のリードフレーム１０を切断した後のインナーリード１１である。
図３は、積層インダクタの要部構造図である。この積層インダクタ３は高さ方向にスパイラル状に伸びたコイル１４をフェライトなどの絶縁磁性部材３ｂに埋め込み、両端に端子３ａを設けた構造をしており、その積層インダクタ３の高さＨは０．５ｍｍ程度である。またこの積層インダクタ３のインダクタンスは１μＨ程度である。
前記の半導体チップ１は、携帯型電子機器に使用される分散型電源ＩＣチップ、もしくは集中型電源の不足分を補う個別電源ＩＣチップである。 The support lead plate 4 and the external lead-out terminal 5 are fixed by the resin mold 9 after the laminated inductor 3 is fixed to the lead frame 10 shown in FIG. 2, the semiconductor chip 1 is fixed thereon, and the gold wire 8 is bonded. This is the inner lead 11 after stopping and cutting the unnecessary lead frame 10.
FIG. 3 is a structural diagram of a principal part of the multilayer inductor. This multilayer inductor 3 has a structure in which a coil 14 extending in a spiral shape in the height direction is embedded in an insulating magnetic member 3b such as ferrite and terminals 3a are provided at both ends, and the height H of the multilayer inductor 3 is 0. About 5 mm. The inductance of the multilayer inductor 3 is about 1 μH.
The semiconductor chip 1 is a distributed power supply IC chip used for portable electronic devices or an individual power supply IC chip that compensates for the shortage of centralized power supplies.

この半導体チップ１の厚さは０．１４ｍｍ程度であり、またリードフレームを切断して得られた支持導板４と外部導出端子５の厚さは０．１５ｍｍ程度であり、半導体チップ１面と樹脂モールド９の表面の間の距離は０．１８ｍｍ程度である。従って、インダクタ付半導体装置の全体の厚さ（高さ）は０．９７ｍｍ程度であり、Ａｇペースト６や絶縁性ＤＡＦテープ７の厚さを入れても１．００ｍｍ以下である。また、各部の厚みにバラツキがあった場合でも全体の厚さを１．２ｍｍ以下にすることができる。
このように、積層インダクタ３を用い、ワイヤ（金ワイヤ８）を横出しすることで、インダクタ付半導体装置の厚さを１．２ｍｍ以下と薄くすることができる。横出しする方法は、半導体チップ１の端子電極２にワイヤ（金ワイヤ８）を超音波ボンダーで固着し、そのワイヤを水平に引っ張りその後外部導出端子５に超音波ボンダーで固着する。 The thickness of the semiconductor chip 1 is about 0.14 mm, and the thickness of the support conductive plate 4 and the external lead-out terminal 5 obtained by cutting the lead frame is about 0.15 mm. The distance between the surfaces of the resin mold 9 is about 0.18 mm. Therefore, the total thickness (height) of the semiconductor device with an inductor is about 0.97 mm, and even if the thickness of the Ag paste 6 and the insulating DAF tape 7 is included, it is 1.00 mm or less. Moreover, even when there is variation in the thickness of each part, the total thickness can be reduced to 1.2 mm or less.
Thus, by using the multilayer inductor 3 and laterally extending the wire (gold wire 8), the thickness of the semiconductor device with an inductor can be reduced to 1.2 mm or less. As a method of laterally extending, a wire (gold wire 8) is fixed to the terminal electrode 2 of the semiconductor chip 1 with an ultrasonic bonder, the wire is pulled horizontally, and then fixed to the external lead-out terminal 5 with an ultrasonic bonder.

また、積層インダクタ３上に半導体チップ１を乗せ、積層インダクタ３の端子３ａは支持導板４に直接接続しているのでワイヤでの接続は不要である。また、半導体チップ１とワイヤとの接続は半導体チップ１の表面で行われるために、半導体チップ１が積層インダクタ３の大きさに制約されず、積層インダクタ３より大きくも小さくもできる。そのため、要求される活性領域の面積が小さい場合には小さな半導体チップ１を積層インダクタ３に乗せることができて、低コスト化を図ることができる。
積層インダクタ３の他に、渦巻きインダクタ、ソレノイドインダクタ、トロイダルインダクタなどの薄型インダクタも用いることができる。
また、このインダクタ付半導体装置の用途は、ＤＣ／ＤＣコンバータに限らずインダクタと集積回路の組み合わせ用途であれば他の用途にも使える。 Further, since the semiconductor chip 1 is placed on the multilayer inductor 3 and the terminal 3a of the multilayer inductor 3 is directly connected to the support conductive plate 4, connection with a wire is not necessary. Further, since the connection between the semiconductor chip 1 and the wire is performed on the surface of the semiconductor chip 1, the semiconductor chip 1 is not limited by the size of the multilayer inductor 3 and can be larger or smaller than the multilayer inductor 3. Therefore, when the required area of the active region is small, a small semiconductor chip 1 can be placed on the multilayer inductor 3 and the cost can be reduced.
In addition to the multilayer inductor 3, a thin inductor such as a spiral inductor, a solenoid inductor, or a toroidal inductor can also be used.
The application of the semiconductor device with an inductor is not limited to the DC / DC converter, and can be used for other applications as long as it is a combination of an inductor and an integrated circuit.

図４は、この発明の第２実施例のインダクタ付半導体装置の構成図であり、同図（ａ）は要部斜視図、同図（ｂ）は同図（ａ）のＸ−Ｘ線で切断した要部断面図である。
第１実施例との違いは、積層インダクタ３と半導体チップ１を上下入れ換えて、半導体チップ１上に積層インダクタ３を固着した点である。この場合は、金ワイヤ８を半導体チップ１の外周部に形成された端子電極２にボンディングする都合上、端子電極２が形成される箇所だけ半導体チップ１を積層インダクタ３より大きくする必要がある。一方、端子電極２が形成されない箇所では積層インダクタ３は半導体チップ１からはみ出しても構わない。
また、第２実施例の場合には、半導体チップ１を支持導板４にＡｇベースト６またははんだを介して固着するために、半導体チップ１で発生した熱を効率よく支持導板４に放散させることができるので、発生損失の大きな半導体チップ１の場合に適用される。また発熱が小さな半導体チップ１ではＡｇペースト６の代わりに絶縁性ＤＡＦテープ７のような絶縁性接着材を用いてもよい。 FIGS. 4A and 4B are configuration diagrams of a semiconductor device with an inductor according to a second embodiment of the present invention. FIG. 4A is a perspective view of the main part, and FIG. 4B is a sectional view taken along line XX in FIG. It is the principal part sectional drawing cut | disconnected.
The difference from the first embodiment is that the laminated inductor 3 is fixed on the semiconductor chip 1 by switching the laminated inductor 3 and the semiconductor chip 1 upside down. In this case, for the convenience of bonding the gold wire 8 to the terminal electrode 2 formed on the outer peripheral portion of the semiconductor chip 1, it is necessary to make the semiconductor chip 1 larger than the multilayer inductor 3 only at a location where the terminal electrode 2 is formed. On the other hand, the laminated inductor 3 may protrude from the semiconductor chip 1 at a location where the terminal electrode 2 is not formed.
In the case of the second embodiment, the heat generated in the semiconductor chip 1 is efficiently dissipated to the support conductive plate 4 in order to fix the semiconductor chip 1 to the support conductive plate 4 via the Ag base 6 or solder. Therefore, the present invention is applied to the case of the semiconductor chip 1 having a large generation loss. Further, in the semiconductor chip 1 that generates a small amount of heat, an insulating adhesive such as an insulating DAF tape 7 may be used instead of the Ag paste 6.

尚、リードフレーム１０の形状は図５のような形状をしており、図２とは異なる。図中の１３は半導体チップ１を固着するダイパッドである。尚、図５（ａ）は切断前の要部平面図、図５（ｂ）は切断後の要部断面図である。   The lead frame 10 has a shape as shown in FIG. 5 and is different from that shown in FIG. Reference numeral 13 in the drawing denotes a die pad for fixing the semiconductor chip 1. 5A is a plan view of the main part before cutting, and FIG. 5B is a cross-sectional view of the main part after cutting.

図６は、この発明の第３実施例のインダクタ付半導体装置の要部断面図である。これは、樹脂封止していないインダクタ付半導体装置の例である。図６では、この樹脂モールドで封止していないインダクタ付半導体装置３０と他の部品（コンデンサ２３た抵抗２４など）と一緒にプリント基板２１の導電パターン２２にはんだなどの固着材２５で固着した後で、一緒に樹脂モールド３１で封止した例を示している。
この場合は、プリント基板２１の導電パターン２２に積層インダクタ３を固着材２５で固着し、半導体チップ１の端子電極２を金ワイヤ８でプリント基板２１の導電パターン２２に接続する。
このように、インダクタ付半導体装置３０はパッケージされない状態で、プリント基板２１の導電パターン２２に固着して使用される場合もある。このような構成にしたものは、前記したＤＣ／ＤＣコンバータ以外の変換装置にも適用することができる。 FIG. 6 is a cross-sectional view of an essential part of a semiconductor device with an inductor according to a third embodiment of the present invention. This is an example of a semiconductor device with an inductor that is not resin-sealed. In FIG. 6, the inductor-attached semiconductor device 30 not sealed with the resin mold and other components (such as the resistor 24 having the capacitor 23) are fixed to the conductive pattern 22 of the printed circuit board 21 with a fixing material 25 such as solder. An example of sealing with a resin mold 31 later is shown.
In this case, the laminated inductor 3 is fixed to the conductive pattern 22 of the printed board 21 with the fixing material 25, and the terminal electrode 2 of the semiconductor chip 1 is connected to the conductive pattern 22 of the printed board 21 with the gold wire 8.
As described above, the inductor-attached semiconductor device 30 may be used while being fixed to the conductive pattern 22 of the printed circuit board 21 without being packaged. What was constituted in this way can be applied also to converters other than the above-mentioned DC / DC converter.

この発明の第１実施例のインダクタ付半導体装置の構成図であり、（ａ）は要部斜視図、（ｂ）は（ａ）のＸ−Ｘ線で切断した要部断面図BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram of the semiconductor device with an inductor of 1st Example of this invention, (a) is a principal part perspective view, (b) is principal part sectional drawing cut | disconnected by the XX line of (a). リードフレームの要部平面図であり、（ａ）は切断前の要部平面図、（ｂ）は切断後の要部平面図FIG. 3 is a plan view of the main part of the lead frame, (a) is a plan view of the main part before cutting, and (b) is a plan view of the main part after cutting. 積層インダクタの要部構造図Multilayer inductor structure diagram この発明の第２実施例のインダクタ付半導体装置の構成図であり、（ａ）は要部斜視図、（ｂ）は（ａ）のＸ−Ｘ線で切断した要部断面図It is a block diagram of the semiconductor device with an inductor of 2nd Example of this invention, (a) is a principal part perspective view, (b) is principal part sectional drawing cut | disconnected by the XX line of (a). 別のリードフレームの要部平面図であり、（ａ）は切断前の要部平面図、（ｂ）は切断後の要部平面図It is a principal part top view of another lead frame, (a) is a principal part top view before cutting, (b) is a principal part top view after cutting この発明の第３実施例のインダクタ付半導体装置の要部断面図Sectional drawing of the principal part of the semiconductor device with an inductor of 3rd Example of this invention 図７は、従来のＤＣ／ＤＣコンバータの要部断面図FIG. 7 is a sectional view of the main part of a conventional DC / DC converter.

符号の説明Explanation of symbols

１ 半導体チップ
２ 端子電極
３ 積層インダクタ
３ａ 端子
３ｂ 絶縁磁性部材
４ 支持導板
５ 外部導出端子
６ Ａｇペースト
７ 絶縁性ＤＡＦテープ
８ 金ワイヤ
９ 樹脂モールド
１０ リードフレーム
１１ インナーリード
１２ コイル
１３ ダイパッド
２１ プリント基板
２２ 導電パターン
２３ コンデンサ
２４ 抵抗
２５ 固着材
３０ 樹脂モールドされないインダクタ付半導体装置
３１ 樹脂モールド DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Terminal electrode 3 Multilayer inductor 3a Terminal 3b Insulating magnetic member 4 Supporting conductive plate 5 External lead-out terminal 6 Ag paste 7 Insulating DAF tape 8 Gold wire 9 Resin mold 10 Lead frame 11 Inner lead 12 Coil 13 Die pad 21 Printed circuit board 22 Conductive Pattern 23 Capacitor 24 Resistance 25 Fixing Material 30 Semiconductor Device with Inductor Not Resin Molded 31 Resin Molded

Claims (10)

半導体チップと、薄型インダクタとを積層したインダクタ付半導体装置であって、
支持導板上に薄型インダクタを第１の固着材で固着し、前記薄型インダクタ上に前記半導体チップを第２の固着材で固着する、もしくは前記支持基板上に前記半導体チップを第１の固着材で固着し、前記半導体チップ上に前記薄膜インダクタを第２の固着材で固定して、前記半導体チップ上に形成した端子電極と前記支持導板もしくは前記薄膜インダクタに設けられたインダクタ端子、並びに前記端子電極と外部導出端子とをそれぞれ導線で接続することを特徴とするインダクタ付半導体装置。 A semiconductor device with an inductor in which a semiconductor chip and a thin inductor are laminated,
A thin inductor is fixed on the supporting conductive plate with a first fixing material, and the semiconductor chip is fixed on the thin inductor with a second fixing material, or the semiconductor chip is fixed on the supporting substrate with a first fixing material. And fixing the thin film inductor on the semiconductor chip with a second fixing material, a terminal electrode formed on the semiconductor chip and an inductor terminal provided on the supporting conductive plate or the thin film inductor, and the A semiconductor device with an inductor, wherein a terminal electrode and an external lead-out terminal are each connected by a conductive wire. 前記薄型インダクタは、積層インダクタであることを特徴とする請求項１に記載のインダクタ付半導体装置。 The semiconductor device with an inductor according to claim 1, wherein the thin inductor is a multilayer inductor. 前記積層インダクタは、高さ方向にスパイラル状に巻かれたコイルを磁性絶縁部材に埋め込んで形成されることを特徴とする請求項２に記載のインダクタ付半導体装置。 3. The semiconductor device with an inductor according to claim 2, wherein the multilayer inductor is formed by embedding a coil wound in a spiral shape in a height direction in a magnetic insulating member. 前記積層インダクタの高さが、０．６ｍｍ以下であることを特徴とする請求項３に記載のインダクタ付半導体装置。 The semiconductor device with an inductor according to claim 3, wherein a height of the multilayer inductor is 0.6 mm or less. 前記第１の固着材が前記薄膜インダクタと前記支持導板とを固着する場合には導電性接着材であり、前記半導体チップと前記支持導板とを固着する場合には導電性接着材もしくは絶縁性接着材であり、前記第２の固着材が絶縁性接着材であることを特徴とする請求項１に記載のインダクタ付半導体装置。 When the first fixing material fixes the thin-film inductor and the supporting conductive plate, it is a conductive adhesive, and when the semiconductor chip and the supporting conductive plate are fixed, a conductive adhesive or insulating material is used. The semiconductor device with an inductor according to claim 1, wherein the second fixing material is an insulating adhesive. 前記導電性接着材がＡｇベーストもしくははんだであることを特徴とする請求項５に記載のインダクタ付半導体装置。 6. The semiconductor device with an inductor according to claim 5, wherein the conductive adhesive is Ag-based or solder. 前記絶縁性接着材が絶縁性ＤＡＦ（Ｄｉｅ Ａｔｔａｃｈ Ｆｉｌｍ）であることを特徴とする請求項６に記載のインダクタ付半導体装置。 The semiconductor device with an inductor according to claim 6, wherein the insulating adhesive is an insulating DAF (Die Attach Film). 前記支持導板と前記薄型インダクタと前記薄型インダクタと前記導線と前記外部導出端子とを前記支持導板の裏面と前記外部導出端子の裏面が露出するように樹脂モールドで封止することを特徴とする請求項１に記載のインダクタ付半導体装置。 The support conductive plate, the thin inductor, the thin inductor, the conductive wire, and the external lead terminal are sealed with a resin mold so that a back surface of the support conductive plate and a back surface of the external lead terminal are exposed. The semiconductor device with an inductor according to claim 1. 前記支持導板裏面から前記樹脂モールドの上面までの高さが１．２ｍｍ以下であることを特徴とする請求項８に記載のインダクタ付半導体装置。 The semiconductor device with an inductor according to claim 8, wherein a height from a back surface of the support conductive plate to an upper surface of the resin mold is 1.2 mm or less. 前記導線が金ワイヤもしくはアルミワイヤであることを特徴とする請求項１に記載のインダクタ付半導体装置。 The semiconductor device with an inductor according to claim 1, wherein the conducting wire is a gold wire or an aluminum wire.
JP2005267268A 2005-09-14 2005-09-14 Semiconductor device with inductor Withdrawn JP2007081146A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005267268A JP2007081146A (en) 2005-09-14 2005-09-14 Semiconductor device with inductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005267268A JP2007081146A (en) 2005-09-14 2005-09-14 Semiconductor device with inductor

Publications (2)

Publication Number Publication Date
JP2007081146A true JP2007081146A (en) 2007-03-29
JP2007081146A5 JP2007081146A5 (en) 2007-06-21

Family

ID=37941118

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005267268A Withdrawn JP2007081146A (en) 2005-09-14 2005-09-14 Semiconductor device with inductor

Country Status (1)

Country Link
JP (1) JP2007081146A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008251901A (en) * 2007-03-30 2008-10-16 Fuji Electric Device Technology Co Ltd Composite semiconductor device
JP2009142018A (en) * 2007-12-05 2009-06-25 Fuji Electric Device Technology Co Ltd Micro-power conversion device
JP2010056463A (en) * 2008-08-29 2010-03-11 Tdk Corp Electronic component module and method of manufacturing the same
WO2010087407A1 (en) 2009-01-28 2010-08-05 日立金属株式会社 Semiconductor device and power supply circuit
CN109712948A (en) * 2019-01-24 2019-05-03 广东气派科技有限公司 A kind of chip-packaging structure of integrated passive device
CN112701055A (en) * 2020-12-22 2021-04-23 杰群电子科技（东莞）有限公司 Packaging method and packaging structure of embedded element

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04184834A (en) * 1990-11-16 1992-07-01 Omron Corp Switch
JP2000509560A (en) * 1996-08-09 2000-07-25 ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング Multi-chip module
JP2001127199A (en) * 1999-10-29 2001-05-11 Matsushita Electronics Industry Corp Resin-sealed semiconductor device and its manufacturing method
JP2002133385A (en) * 2000-10-20 2002-05-10 Dainippon Printing Co Ltd Noncontact/contact ic module and ic card
JP2002233140A (en) * 2001-01-30 2002-08-16 Fuji Electric Co Ltd Microminiature power converter
JP2003142832A (en) * 2001-11-05 2003-05-16 Matsushita Electric Ind Co Ltd Module with built-in part, package, and its manufacturing method
JP2005005548A (en) * 2003-06-13 2005-01-06 Sony Corp Semiconductor device, its packaging structure, and its manufacturing process

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04184834A (en) * 1990-11-16 1992-07-01 Omron Corp Switch
JP2000509560A (en) * 1996-08-09 2000-07-25 ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング Multi-chip module
JP2001127199A (en) * 1999-10-29 2001-05-11 Matsushita Electronics Industry Corp Resin-sealed semiconductor device and its manufacturing method
JP2002133385A (en) * 2000-10-20 2002-05-10 Dainippon Printing Co Ltd Noncontact/contact ic module and ic card
JP2002233140A (en) * 2001-01-30 2002-08-16 Fuji Electric Co Ltd Microminiature power converter
JP2003142832A (en) * 2001-11-05 2003-05-16 Matsushita Electric Ind Co Ltd Module with built-in part, package, and its manufacturing method
JP2005005548A (en) * 2003-06-13 2005-01-06 Sony Corp Semiconductor device, its packaging structure, and its manufacturing process

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008251901A (en) * 2007-03-30 2008-10-16 Fuji Electric Device Technology Co Ltd Composite semiconductor device
JP2009142018A (en) * 2007-12-05 2009-06-25 Fuji Electric Device Technology Co Ltd Micro-power conversion device
US8031041B2 (en) 2007-12-05 2011-10-04 Fuji Electric Systems Co., Ltd. Micro power converter
JP2010056463A (en) * 2008-08-29 2010-03-11 Tdk Corp Electronic component module and method of manufacturing the same
WO2010087407A1 (en) 2009-01-28 2010-08-05 日立金属株式会社 Semiconductor device and power supply circuit
US8592967B2 (en) 2009-01-28 2013-11-26 Hitachi Metals, Ltd. Semiconductor apparatus and power supply circuit
CN109712948A (en) * 2019-01-24 2019-05-03 广东气派科技有限公司 A kind of chip-packaging structure of integrated passive device
CN112701055A (en) * 2020-12-22 2021-04-23 杰群电子科技（东莞）有限公司 Packaging method and packaging structure of embedded element
CN112701055B (en) * 2020-12-22 2022-04-22 杰群电子科技（东莞）有限公司 Packaging method and packaging structure of embedded element

Similar Documents

Publication Publication Date Title
JP5614286B2 (en) Semiconductor device and power supply circuit
US7868431B2 (en) Compact power semiconductor package and method with stacked inductor and integrated circuit die
US8217748B2 (en) Compact inductive power electronics package
US10389241B2 (en) Power supply converter and method for manufacturing the same
TWI385778B (en) Semiconductor power device having a stacked discrete inductor structure
JP3679687B2 (en) Hybrid integrated circuit device
TWI579982B (en) Power Module Package
US8063472B2 (en) Semiconductor package with stacked dice for a buck converter
JP2006304591A (en) Primary-side active circuit device for switch mode power supply
JP2007081146A (en) Semiconductor device with inductor
JP2007318954A (en) Micro dc-dc converter module
TW200832670A (en) Electronic device with inductor and integrated componentry
US7649746B2 (en) Semiconductor device with inductor
JP4936103B2 (en) DC-DC converter
JP2010287684A (en) Inductor element, dc (direct current)-dc converter module with the inductor element, method of manufacturing dc-dc converter, and electronic apparatus
JPWO2016076162A1 (en) Composite electronic component and DCDC converter module
JP2008017540A (en) Microminiature power converter
US11870341B2 (en) Isolated power converter package with molded transformer
JP2013004912A (en) Semiconductor module
JP2005229766A (en) Power supply module and method for manufacturing same
JP2004165429A (en) Semiconductor device and its manufacturing method, passive element and its accumulation structure, and lead frame
JP2010251559A (en) Electronic circuit device
CN112312678A (en) Structure and method of non-packaged chip direct-buried printed circuit board and chip packaging structure
CN106601694B (en) Stack structure and manufacturing method thereof
US12027436B2 (en) Package with clip having through hole accommodating component-related structure

Legal Events

Date Code Title Description
A521 Written amendment

Effective date: 20070509

Free format text: JAPANESE INTERMEDIATE CODE: A523

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080812

RD02 Notification of acceptance of power of attorney

Effective date: 20081216

Free format text: JAPANESE INTERMEDIATE CODE: A7422

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20090219

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20091112

A977 Report on retrieval

Effective date: 20100709

Free format text: JAPANESE INTERMEDIATE CODE: A971007

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100727

A761 Written withdrawal of application

Free format text: JAPANESE INTERMEDIATE CODE: A761

Effective date: 20101004