JP2007146336A - Knitting machine - Google Patents

Knitting machine Download PDF

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JP2007146336A
JP2007146336A JP2005344124A JP2005344124A JP2007146336A JP 2007146336 A JP2007146336 A JP 2007146336A JP 2005344124 A JP2005344124 A JP 2005344124A JP 2005344124 A JP2005344124 A JP 2005344124A JP 2007146336 A JP2007146336 A JP 2007146336A
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abnormality
load
knitting machine
signal
coil
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Akihiro Kamiyama
晃弘 上山
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Shima Seiki Mfg Ltd
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Shima Seiki Mfg Ltd
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Priority to JP2005344124A priority Critical patent/JP2007146336A/en
Priority to CN2006101635159A priority patent/CN1974905B/en
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Abstract

<P>PROBLEM TO BE SOLVED: To prevent failure from secondarily increasing and specify the source of failure when load or control element of a knitting machine is broken down. <P>SOLUTION: In a knitting machine in which pulse driving is carried out by connecting FET122 to a coil 8 of actuator of the knitting machine, a resistance R2 for detecting electric current is provided and peak value and average value of the current waveform are monitored by comparators 32 and 34 and whether the current waveform is lower than monitoring level of breaking of wire or not is monitored by a comparator 36. The waveforms of clock signal, data signal and load pulse of FPGA4 for control are further monitored by an output pin of FPGA4. When any abnormality is detected, the cause is recorded and displayed and knitting action of the knitting machine is stopped. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

この発明は横編機や丸編機、経編機、靴下や手袋の編機などの編機に関し、特にそのパルス動作負荷と制御素子との異常検出に関する。   The present invention relates to a knitting machine such as a flat knitting machine, a circular knitting machine, a warp knitting machine, a sock or a glove knitting machine, and more particularly to detection of an abnormality between a pulse operation load and a control element.

横編機や丸編機、経編機、靴下や手袋の編機、などの編機では、選針アクチュエータやトランスファージャック、ループプレッサなどの選択アクチュエータを使用する。これらのアクチュエータには電磁石が設けられ、そのコイルを制御素子を介してパルス制御する。なお選針アクチュエータや選択アクチュエータを総称して、選択アクチュエータという。さらに故障と異常は同義語である。また編機では、選択アクチュエータ以外に、ヤーンキャリアの連行を制御するためのキープソレノイド等が使用され、同様に制御素子を介してパルス制御される。   In a knitting machine such as a flat knitting machine, a circular knitting machine, a warp knitting machine, a sock or glove knitting machine, a selection actuator such as a needle selection actuator, a transfer jack or a loop presser is used. These actuators are provided with electromagnets, and the coils are pulse-controlled through control elements. The needle selection actuator and the selection actuator are collectively referred to as a selection actuator. Furthermore, failure and abnormality are synonymous. In the knitting machine, in addition to the selected actuator, a keep solenoid or the like for controlling entrainment of the yarn carrier is used, and similarly, pulse control is performed via the control element.

選択アクチュエータなどの負荷が故障により短絡すると、制御素子側に過電流が流れ、制御素子も2次的に故障する。また制御素子が故障により短絡すると、負荷側も過電流により2次的に故障する。そのため異常が2次的に拡大し、かつ負荷も制御素子も異常になった後では、何れが原因で故障したのかの特定が困難である。   When a load such as a selected actuator is short-circuited due to a failure, an overcurrent flows to the control element side, and the control element also secondarily fails. Further, when the control element is short-circuited due to a failure, the load side also secondarily fails due to an overcurrent. For this reason, after the abnormality has expanded secondarily and the load and the control element have become abnormal, it is difficult to identify which caused the failure.

この発明の課題は、編機の負荷あるいは制御素子が故障した際に、故障が2次的に拡大するのを防止すると共に、故障原因を特定できるようにすることにある。
この発明の副次的な課題は、制御素子を制御する制御ICの異常やピンの短絡等も検出することにある。
この発明の副次的な課題はまた、負荷や制御素子が故障した際に、故障が2次的に拡大するのを確実に防止すると共に、故障原因をオペレータ等が容易に確認できるようにすることにある。
An object of the present invention is to prevent a failure from being secondarily expanded when a load or a control element of a knitting machine fails, and to identify the cause of the failure.
A secondary problem of the present invention is to detect an abnormality of a control IC that controls a control element, a short circuit of a pin, and the like.
A secondary problem of the present invention is that when a load or a control element breaks down, it is possible to reliably prevent the failure from being secondaryly expanded and to make it easy for an operator to confirm the cause of the failure. There is.

この発明は、制御素子に接続されてパルス的に動作する負荷の異常を検出するようにした編機において、前記負荷を流れる電流のピーク値を監視し、ピーク値が第1の所定値を越える場合に負荷の短絡を検出するための短絡検出手段と、前記負荷を流れる電流の平均値を監視し、平均値が第2の所定値を越える場合に、制御素子の異常を検出するための平均値検出手段と、負荷の短絡もしくは制御素子の異常を検出した際に、負荷の動作を停止させるための停止手段、とを設けたことを特徴とする。   According to the present invention, in a knitting machine that is connected to a control element and detects an abnormality of a load that operates in a pulse manner, the peak value of a current flowing through the load is monitored, and the peak value exceeds a first predetermined value. A short-circuit detecting means for detecting a short-circuit of the load and an average value for monitoring an average value of the current flowing through the load and detecting an abnormality of the control element when the average value exceeds a second predetermined value A value detection means and a stop means for stopping the operation of the load when a short circuit of the load or an abnormality of the control element is detected are provided.

好ましくは、前記制御素子を制御するための制御ICの出力ピン側の電位波形を監視するための手段をさらに設けて、制御ICの異常を検出する。   Preferably, a means for monitoring a potential waveform on the output pin side of the control IC for controlling the control element is further provided to detect abnormality of the control IC.

また好ましくは、前記停止手段を異常検出時に負荷の電源を遮断するように構成し、さらに異常検出時に異常原因を出力するための手段とを設ける。   Preferably, the stopping means is configured to shut off the power supply of the load when an abnormality is detected, and further provided with means for outputting the cause of the abnormality when the abnormality is detected.

好ましくは、前記負荷がアクチュエータで、前記制御素子が該負荷をチョッパ制御する。   Preferably, the load is an actuator, and the control element performs chopper control of the load.

この発明では、異常が負荷側から始まったのか制御素子側から始まったのかを識別できると共に、異常の発生時に停止手段で負荷を停止させて異常が2次的に拡大するのを防止する。異常の2次的拡大を防止するので、異常の原因が負荷側か制御素子側かメンテナンス時等に特定できる。   According to the present invention, it is possible to identify whether the abnormality has started from the load side or from the control element side, and when the abnormality occurs, the load is stopped by the stop means to prevent the abnormality from being secondarily enlarged. Since secondary expansion of the abnormality is prevented, the cause of the abnormality can be specified at the load side or the control element side during maintenance.

制御素子を制御するための制御ICの出力ピン側の電位波形を監視すると、出力信号のパルス幅等の波形が正常かどうかからIC内部の異常や出力ピンの短絡も検出できる。   When the potential waveform on the output pin side of the control IC for controlling the control element is monitored, it is possible to detect an abnormality inside the IC and a short circuit of the output pin from whether or not the waveform such as the pulse width of the output signal is normal.

異常検出時に負荷の電源を遮断するとより確実に異常が拡大するのを防止できる。また異常検出時に、異常原因をモニタやログファイルあるいは編機に接続したLAN等に出力すると、オペレータ等はそれから異常原因を容易に知ることができる。   If the load power supply is shut off when an abnormality is detected, the abnormality can be prevented from expanding more reliably. In addition, when an abnormality is detected, if the cause of the abnormality is output to a monitor, a log file, or a LAN connected to the knitting machine, the operator can easily know the cause of the abnormality.

負荷には電磁石やソレノイドのコイルを用いる場合が重要で、コイル負荷が短絡すると制御素子は簡単に故障する。また制御素子が短絡しても、パルス動作用に設計されたコイルは簡単に短絡する。特にパルスにより負荷をチョッパ制御する場合、負荷をオンさせるパルスが複数なので、単パルスで駆動するキープソレノイドよりも制御素子は故障しやすく、また負荷電流のピーク値と平均値とを別々に検出することが容易である。   It is important to use an electromagnet or solenoid coil as the load. If the coil load is short-circuited, the control element can easily fail. Even if the control element is short-circuited, the coil designed for pulse operation is easily short-circuited. Especially when the load is chopper controlled by pulses, there are multiple pulses to turn on the load, so the control element is more prone to failure than the keep solenoid driven by a single pulse, and the peak value and average value of the load current are detected separately. Is easy.

以下に本発明を実施するための最適実施例を示す。   In the following, an optimum embodiment for carrying out the present invention will be shown.

図1〜図6に、実施例とその変形とを示す。各図において、2はCPUで、横編機や丸編機、経編機などの編機のコントローラ内に設けられ、編機全体を制御する。4はFPGA(フィールド・プログラマブル・ゲート・アレイ)で、6はPLD(プログラマブル・ロジック・デバイス)である。8は選択アクチュエータのコイルで、ここでは編機の針やトランスファージャック,ループプレッサーなどの可動部材を選択するためのアクチュエータのコイルで、具体的にはこれらの選択用電磁石のコイルである。10,12はFETで、他のMOSトランジスタスイッチ、バイポーラトランジスタスイッチ,あるいはリレーなどでもよい。D1はダイオード、R1は抵抗で、FET10をオフしている際に、コイル8の電力を消費するために用いる。   1 to 6 show an embodiment and its modifications. In each figure, reference numeral 2 denotes a CPU, which is provided in a controller of a knitting machine such as a flat knitting machine, a circular knitting machine or a warp knitting machine, and controls the entire knitting machine. 4 is an FPGA (Field Programmable Gate Array), and 6 is a PLD (Programmable Logic Device). Reference numeral 8 denotes a coil of a selection actuator. Here, a coil of an actuator for selecting a movable member such as a needle of a knitting machine, a transfer jack, or a loop presser, specifically, a coil of an electromagnet for selection thereof. Reference numerals 10 and 12 denote FETs, which may be other MOS transistor switches, bipolar transistor switches, or relays. D1 is a diode, R1 is a resistor, and is used to consume power of the coil 8 when the FET 10 is turned off.

CPU2には故障処理部14と、液晶タッチパネルなどの表示部16並びにログファイル18を設け、故障が発生すると表示部16に故障の発生とその原因とを表示し、ログファイル18には故障が発生したコイルを特定するデータ、故障の原因(エラーコードで、コイルの短絡、FETの短絡故障、断線、FPGA等の異常で、異常の生じた信号の種類)並びに故障の発生日時などを記録する。CPU2とFPGA4はPCIなどのバス20で接続され、22は入力インターフェース、24はFPGA内の制御信号生成部で、クロック信号やデータ信号、ロードパルス信号などの制御用信号を発生し、これらの出力ピンにロードパルスチェック部26とデータ信号チェック部28並びにクロック信号チェック部30を接続して、ロードパルス信号やデータ信号並びにクロック信号をチェックする。FPGA4で発生した異常検出信号をe4と呼び、クロック信号異常、データ信号異常、ロードパルス異常などの種別が異常検出信号e4に記載されている。   The CPU 2 is provided with a failure processing unit 14, a display unit 16 such as a liquid crystal touch panel, and a log file 18. When a failure occurs, the occurrence and cause of the failure are displayed on the display unit 16, and the failure occurs in the log file 18. The data for identifying the coil, the cause of the failure (error code, coil short-circuit, FET short-circuit failure, disconnection, type of signal that caused an abnormality such as FPGA) and the date and time of occurrence of the failure are recorded. The CPU 2 and the FPGA 4 are connected by a bus 20 such as a PCI, 22 is an input interface, 24 is a control signal generator in the FPGA, and generates control signals such as a clock signal, a data signal, and a load pulse signal. The load pulse check unit 26, the data signal check unit 28, and the clock signal check unit 30 are connected to the pins to check the load pulse signal, the data signal, and the clock signal. An abnormality detection signal generated in the FPGA 4 is called e4, and types such as a clock signal abnormality, a data signal abnormality, and a load pulse abnormality are described in the abnormality detection signal e4.

R2は電流検出用の抵抗で、コイル8が短絡した際や、FET12が故障により短絡した際に過電流を制限し、故障が拡大するのを遅らせる意味も持ち、抵抗R2を流れる電流をiとする。R3〜R5は抵抗で、C1〜C3はコンデンサである。抵抗R3とコンデンサC1,抵抗R4とコンデンサC2,抵抗R5とコンデンサC3とでそれぞれ積分回路を構成し、32〜36はコンパレータである。ここで積分回路(R3,C1),(R5,C3)を用いるのは、FET12のオン時に突入電流があり、これがノイズとなるのを避けるためである。また抵抗R3とコンデンサC1で構成するピーク電流監視用の積分回路の時定数は、抵抗R4とコンデンサC2で構成する平均電流監視用の積分回路の時定数よりも短くする。コンデンサC1の出力電圧はピーク電流監視信号v1で、電流iのピーク値に対応する電圧であり、コンデンサC2の出力電圧は平均電流監視信号v2で、FET12のオンのデューテイ比を表す信号となる。コンデンサC3の出力電圧が断線監視信号v3で、断線監視信号v3はピーク電流監視信号v1あるいは平均電流監視信号v2で代用しても良い。   R2 is a resistance for current detection, and has the meaning of limiting the overcurrent when the coil 8 is short-circuited or when the FET 12 is short-circuited due to a failure and delaying the expansion of the failure. The current flowing through the resistor R2 is i. To do. R3 to R5 are resistors, and C1 to C3 are capacitors. The resistor R3 and the capacitor C1, the resistor R4 and the capacitor C2, the resistor R5 and the capacitor C3 constitute an integrating circuit, and 32 to 36 are comparators. The reason why the integrating circuits (R3, C1) and (R5, C3) are used here is to avoid an inrush current when the FET 12 is turned on, which becomes a noise. The time constant of the integrating circuit for monitoring the peak current constituted by the resistor R3 and the capacitor C1 is made shorter than the time constant of the integrating circuit for monitoring the average current constituted by the resistor R4 and the capacitor C2. The output voltage of the capacitor C1 is a peak current monitoring signal v1, which is a voltage corresponding to the peak value of the current i. The output voltage of the capacitor C2 is an average current monitoring signal v2, which is a signal representing the on-duty ratio of the FET 12. The output voltage of the capacitor C3 may be the disconnection monitoring signal v3, and the disconnection monitoring signal v3 may be replaced by the peak current monitoring signal v1 or the average current monitoring signal v2.

IC38はコンパレータ32〜36の出力を監視し、ref1〜ref3はコンパレータ32〜36への比較電位である。IC38は、コンパレータ32がオンからオフに変化することにより、コイル8の短絡を意味する異常検出信号e1を出力する。IC38はまた、コンパレータ34がオンからオフに変化することにより、FET12の短絡故障を内容とする異常検出信号e2を出力する。さらにコンパレータ36がオンからオフへ変化すると、コイル8などの断線を内容とする異常検出信号e3を出力する。なお電源Vcc、コイル8,抵抗R1,ダイオードD1,FET10,12からグラウンドラインまでは、図示しない編機のキャリッジ内に設けられ、CPU2からPLD6までの部分や抵抗R3〜R5からIC38までの部分は編機のコントローラ側に設けられている。異常検出信号e1〜e3はCPU2へフィードバックする。   The IC 38 monitors the outputs of the comparators 32 to 36, and ref1 to ref3 are comparison potentials to the comparators 32 to 36. The IC 38 outputs an abnormality detection signal e1 that means a short circuit of the coil 8 when the comparator 32 changes from on to off. The IC 38 also outputs an abnormality detection signal e2 containing the short-circuit failure of the FET 12 as the comparator 34 changes from on to off. Further, when the comparator 36 changes from on to off, an abnormality detection signal e3 containing the disconnection of the coil 8 or the like is output. The power supply Vcc, coil 8, resistor R1, diode D1, FETs 10 and 12 to the ground line are provided in the carriage of the knitting machine (not shown). The parts from CPU2 to PLD6 and the parts from resistors R3 to R5 to IC38 are provided. It is provided on the controller side of the knitting machine. The abnormality detection signals e1 to e3 are fed back to the CPU 2.

図1のCPU2はFPGA4以外に種々の部材を制御しており、FPGA4はPLD6以外に他の制御用ICなどを介して、ヤーンキャリアの連行制御用のキープソレノイド(単パルスにより動作するソレノイド)などを制御する。またPLD6は編機の選針装置やトランスファージャックあるいはループプレッサーなどの選択アクチュエータ毎に設けられ、1つの選択アクチュエータには通常複数の電磁石が設けられ、例えば信号P’,P''により同じ選択アクチュエータの他のコイルを制御する。また電源Vccは直流電源とし、選択アクチュエータ毎に独立してオン/オフできるようにしてある。   The CPU 2 in FIG. 1 controls various members in addition to the FPGA 4, and the FPGA 4 keeps the yarn carrier entrainment control solenoid (a solenoid operated by a single pulse) through other control ICs in addition to the PLD 6. To control. Further, the PLD 6 is provided for each selection actuator such as a needle selection device of a knitting machine, a transfer jack or a loop presser, and one selection actuator is usually provided with a plurality of electromagnets, for example, the same selection actuator by signals P ′ and P ″. Control other coils. The power source Vcc is a DC power source and can be turned on / off independently for each selected actuator.

図2は変形例の電流監視用IC40を示し、信号v1,v2をADコンバータ42でAD変換し、比較電圧記憶部44に記憶した3つの比較電圧ref1〜ref3を用い、ピーク電流監視信号v1を比較電圧ref1と比較し、平均電流監視信号v2を比較電圧ref2と比較する。信号v2を断線監視信号に兼用して、これを比較電圧ref3と比較する。断線の有無をより正確に検出する場合、FET12のオン/オフと同期した変化が電流iに生じていることを利用できる。そこでこの場合、例えば信号v2がFET12のオン/オフに同期して比較電圧ref3以上の振幅で変化しているかどうかを検出すると良い。選択アクチュエータのコイル8の短絡、制御用のFET12の故障(短絡)並びに選択アクチュエータのコイル8等の断線などを比較部46で検出すると、その結果を出力インターフェース48から、前記の異常検出信号e1〜e3として出力する。   FIG. 2 shows a modified current monitoring IC 40. The signals v1 and v2 are AD converted by the AD converter 42, and the three comparison voltages ref1 to ref3 stored in the comparison voltage storage unit 44 are used to obtain the peak current monitoring signal v1. Compared with the comparison voltage ref1, the average current monitoring signal v2 is compared with the comparison voltage ref2. The signal v2 is also used as a disconnection monitoring signal and is compared with the comparison voltage ref3. In the case of more accurately detecting the presence or absence of disconnection, it can be used that the current i changes in synchronization with the on / off of the FET 12. Therefore, in this case, for example, it is preferable to detect whether or not the signal v2 changes with an amplitude greater than or equal to the comparison voltage ref3 in synchronization with the on / off of the FET 12. When the comparison unit 46 detects a short circuit of the coil 8 of the selected actuator, a failure (short circuit) of the control FET 12, a disconnection of the coil 8, etc. of the selected actuator, the result is output from the output interface 48 to the abnormality detection signals e 1 to e. Output as e3.

図2のIC40では、所定のタイミングで信号を読み込むことができる。そこで読み込みタイミングを変えて抵抗R2の電圧を読み込むことにより、積分回路を不要にできる。例えばFPGA4やPLD6から信号PをIC40へ入力し、信号Pがオンからオフへ変化する付近のタイミングの電圧をピーク値の監視信号と断線の監視信号に用い、この電圧が所定値を越えるとコイル8の短絡、他の所定値未満で断線を検出できる。またオフ後所定時間経過後の信号を平均値の監視信号に用い、この信号が更に他の所定値を越えるとFET12の短絡故障とする。   The IC 40 in FIG. 2 can read a signal at a predetermined timing. Therefore, the integration circuit can be made unnecessary by changing the reading timing and reading the voltage of the resistor R2. For example, when a signal P is input from the FPGA 4 or PLD 6 to the IC 40 and a voltage at a timing near the time when the signal P changes from on to off is used as a peak value monitoring signal and a disconnection monitoring signal. Disconnection can be detected with a short circuit of 8 or less than another predetermined value. Further, a signal after a predetermined time has elapsed after being turned off is used as an average value monitoring signal. If this signal further exceeds another predetermined value, a short-circuit failure of the FET 12 is assumed.

図3〜図5に実施例の動作波形を示す。図3の1)はFET10の制御信号Enを示し、コイル8を動作させる際には、制御信号Enをハイレベルにし、FET10をオン(導通)させる。FET12は制御信号Pによりパルス的にオンし、コイル8を1回動作させて針などを選択する場合、複数のパルスによりチョッパ制御で選択を行う。パルス信号Pのデューテイ比はコイル8の温度や周囲温度などにより変化させる。また針を2段の選択アクチュエータで選択する場合、2段目の選択アクチュエータでは周囲に有る選択済の針の本数が変化する。ここで選択済みの針は選択アクチュエータ内の永久磁石で吸引され、選択アクチュエータ内のコイルは永久磁石による吸引を打ち消すための磁束を発生させる。永久磁石からの磁束は選択済みの針に流れ込んでいるため、2段目の選択に必要なコイル電流の値は1段目で選択済みの針の本数で変化することがある。このような場合にも信号Pのデューテイ比を変化させる。図3の2)での実線の波形は、信号Pの標準的な波形を、鎖線の波形は起動時などのデューテイ比を高くする際の波形を示す。図3の3)は抵抗R2を流れる電流iの標準的な波形で、FET12をオンした際に突入電流が生じている。   3 to 5 show operation waveforms of the embodiment. 3 shows the control signal En of the FET 10, and when the coil 8 is operated, the control signal En is set to high level to turn on the FET 10. The FET 12 is turned on in a pulse manner by the control signal P, and when the coil 8 is operated once to select a needle or the like, selection is performed by chopper control using a plurality of pulses. The duty ratio of the pulse signal P is changed according to the temperature of the coil 8 or the ambient temperature. When selecting a needle with a two-stage selection actuator, the number of selected needles around the second-stage selection actuator changes. Here, the selected needle is attracted by the permanent magnet in the selected actuator, and the coil in the selected actuator generates a magnetic flux for canceling the attraction by the permanent magnet. Since the magnetic flux from the permanent magnet flows into the selected needle, the value of the coil current required for the second stage selection may vary depending on the number of needles selected in the first stage. Even in such a case, the duty ratio of the signal P is changed. The solid line waveform in 2) of FIG. 3 shows a standard waveform of the signal P, and the chain line waveform shows a waveform when the duty ratio is increased at the time of activation or the like. 3) in FIG. 3 is a standard waveform of the current i flowing through the resistor R2, and an inrush current is generated when the FET 12 is turned on.

図4の2)はピーク電流監視信号v1の波形を示し、実線は正常時の波形を、1点鎖線は異常時の波形を示し、2点鎖線は比較電圧ref1を示す。コイル8が短絡すると、例えばコイル8内の巻線の溶着や導電性の異物の付着のために短絡が生じると、電流iのピーク値が増し、これに伴って図4の2)の1点鎖線のようなピーク値の高い信号v1が生じる。そこでこの信号を比較電圧ref1と比較することにより、コイル8の短絡を検出できる。   2) of FIG. 4 shows the waveform of the peak current monitoring signal v1, the solid line shows the waveform at normal time, the one-dot chain line shows the waveform at abnormality, and the two-dot chain line shows the comparison voltage ref1. When the coil 8 is short-circuited, for example, when the short-circuit occurs due to welding of the winding in the coil 8 or adhesion of conductive foreign matter, the peak value of the current i increases, and accordingly, one point of 2) in FIG. A signal v1 having a high peak value such as a chain line is generated. Therefore, a short circuit of the coil 8 can be detected by comparing this signal with the comparison voltage ref1.

FET12が故障して短絡すると、平均電流監視信号v2は図4の3)の1点鎖線のように、ほぼ一定の高い値となる。そこでこれを比較電圧ref2と比較することにより、FET12の故障を検出できる。なおFET12が故障する場合、ソースとドレイン間が短絡する場合がほとんどである。さらにFET12をオンさせるデューテイ比を増した場合、3)の破線のように信号v2が変化するが、比較電圧ref2を適当な値に選ぶと、FET12の短絡(デューテイ比100%)と、起動時などにデューテイ比を増した際とを区別して検出できる。図4の4)は断線監視信号v3の波形を示し、コイル8やFET12などに断線が生じていない際の信号v3の最小値よりも低くなるように、比較電圧ref3を選ぶ。そこでコイル8あるいはFET12の周囲などに断線が生じると、信号v3が比較電圧ref3を下回って断線を検出できる。   When the FET 12 fails and is short-circuited, the average current monitoring signal v2 becomes a substantially constant high value as indicated by the one-dot chain line in 3) of FIG. Therefore, the failure of the FET 12 can be detected by comparing this with the comparison voltage ref2. When the FET 12 fails, the source and the drain are almost short-circuited. Further, when the duty ratio for turning on the FET 12 is increased, the signal v2 changes as indicated by the broken line in 3). However, if the comparison voltage ref2 is selected to an appropriate value, the FET 12 is short-circuited (duty ratio 100%) and For example, it can be detected separately from when the duty ratio is increased. 4) shows the waveform of the disconnection monitoring signal v3, and the comparison voltage ref3 is selected so as to be lower than the minimum value of the signal v3 when no disconnection occurs in the coil 8, the FET 12, or the like. Therefore, when a break occurs around the coil 8 or the FET 12, the signal v3 falls below the comparison voltage ref3, and the break can be detected.

図5は、FPGA4の出力ピンでの異常の検出を示し、○印は監視対象となる信号の立ち上がりや立ち下がりである。クロック信号の出力ピンの電位波形を監視し、所定の時間間隔τ1内にクロック信号の立ち上がりもしくは立ち下がりがあるかどうかを検出する。例えばこの時間τ1をクロック信号の1/2周期よりも長い時間とすれば、この間に立ち上がりもしくは立ち下がりが存在するはずである。立ち上がりも立ち下がりも存在しない場合、クロック信号の発生部あるいは出力ピンが異常である。2)はデータ信号の出力ピンの電位波形の監視を示し、データ信号の立ち上がりから所定の時間τ2以内に立ち下がりがあるかどうかを検出する。2)では3パルス分について監視対象を○印で示すが、実際はそれ以降のパルスに対しても監視を続行する。さらに2)ではアクティブハイとして示すので、データ信号の立ち下がりを監視するが、アクティブロウの場合立ち上がりを検出する。   FIG. 5 shows the detection of an abnormality at the output pin of the FPGA 4, and the circles indicate the rise or fall of the signal to be monitored. The potential waveform of the output pin of the clock signal is monitored to detect whether the clock signal rises or falls within a predetermined time interval τ1. For example, if the time τ1 is longer than ½ period of the clock signal, there should be a rise or fall during this time. When neither rising nor falling edge exists, the clock signal generation unit or the output pin is abnormal. 2) shows the monitoring of the potential waveform of the output pin of the data signal, and detects whether there is a fall within a predetermined time τ2 from the rise of the data signal. In 2), the monitoring target is indicated by a circle for 3 pulses, but actually monitoring is continued for the subsequent pulses. Further, in 2), since it is shown as active high, the falling of the data signal is monitored, but when it is active low, the rising is detected.

図5の3)はロードパルス信号の出力ピンの電位波形の監視を示し、PLD6はロードパルス信号を受け取ることにより、データ信号の読み取りをエネーブルにする。そして編機のキャリッジが編成を実行している間は、所定の時間τ3内にロードパルス信号の立ち上がりもしくは立ち下がりが存在するはずである。そこで立ち上がりもしくは立ち下がりの有無からロードパルス信号の異常をチェックする。   5) shows monitoring of the potential waveform at the output pin of the load pulse signal, and the PLD 6 enables the reading of the data signal by receiving the load pulse signal. While the carriage of the knitting machine is performing knitting, the load pulse signal should rise or fall within a predetermined time τ3. Therefore, the load pulse signal is checked for abnormalities based on the presence or absence of rise or fall.

さらにFPGA4の出力ピンの短絡が生じると、ピンの電位は特定の値に固定される。そこで出力ピンの電位波形を監視すると、出力ピンの短絡時にも異常を検出できる。出力ピンの電位波形の監視は、ピン自体の電位波形で行っても、ピンに接続された配線の電位波形で監視しても良い。またPLD6はFPGA4に比べて簡単なICで、異常の発生は大部分FPGA4側にあるので、FPGA4側の出力ピンの電位波形を監視する。なおPLD6側の入力ピンに短絡等の異常が生じると、FPGA4側の出力ピンの電位波形の異常で検出できる。   Further, when the output pin of the FPGA 4 is short-circuited, the pin potential is fixed to a specific value. Therefore, if the potential waveform of the output pin is monitored, an abnormality can be detected even when the output pin is short-circuited. The potential waveform of the output pin may be monitored with the potential waveform of the pin itself or with the potential waveform of the wiring connected to the pin. The PLD 6 is a simpler IC than the FPGA 4 and the occurrence of abnormality is mostly on the FPGA 4 side. Therefore, the potential waveform of the output pin on the FPGA 4 side is monitored. If an abnormality such as a short circuit occurs in the input pin on the PLD 6 side, it can be detected by an abnormality in the potential waveform of the output pin on the FPGA 4 side.

図6に編機のアクチュエータの診断アルゴリズムを示し、FET12のオン時のピーク電流が所定値以上の場合、アクチュエータのコイル8の短絡を検出する。電流監視用の抵抗R2に流れる電流の平均値が所定値以上の場合、FET12の短絡故障を検出する。さらに電圧v3の最低値が所定値以下の場合、コイル8の断線を検出する。またこれ以外にFPGA4の異常を、異常検出信号e4により検出する。   FIG. 6 shows a diagnosis algorithm for the actuator of the knitting machine. When the peak current when the FET 12 is on is a predetermined value or more, a short circuit of the coil 8 of the actuator is detected. When the average value of the current flowing through the current monitoring resistor R2 is equal to or greater than a predetermined value, a short circuit failure of the FET 12 is detected. Further, when the minimum value of the voltage v3 is equal to or less than a predetermined value, the disconnection of the coil 8 is detected. In addition, an abnormality of the FPGA 4 is detected by the abnormality detection signal e4.

各異常原因に対して、故障が生じたアクチュエータ及びそのコイルを特定するデータ、あるいはFPGAを特定するデータと、異常の原因(コイルの短絡、FETの故障、断線、制御素子の異常の種別からなるエラーコード)、及び異常の発生日時をログファイル18に記録する。またCPU2あるいはFPGA4などにより、電源Vccをコイル8から遮断し、異常を起こしたコイル8を備えたキャリッジでの編成動作を停止する。編機が複数のキャリッジを備えている場合、異常の生じたコイル8やFET12のあるキャリッジのみ編成動作を停止して、他のキャリッジで編成を続行する。さらにモニタ16に故障が発生したこととその原因とを表示し、メンテナンスを待つ。また編機がLANに接続されている場合、LANに異常の発生とその原因とを出力する。異常の発生により編成を停止するのは、例えばコイル8が短絡すると過電流のため次にFET12が故障し、FET12が故障すると同様に過電流のため次にコイル8が短絡するからである。   For each cause of abnormality, data identifying the actuator and its coil in which the failure occurred, or data identifying the FPGA, and the cause of the abnormality (coil short circuit, FET failure, disconnection, control element abnormality type) Error code) and the date and time of occurrence of the abnormality are recorded in the log file 18. Further, the CPU 2 or the FPGA 4 or the like cuts off the power source Vcc from the coil 8 and stops the knitting operation in the carriage including the coil 8 in which an abnormality has occurred. When the knitting machine includes a plurality of carriages, the knitting operation is stopped only for the carriage having the coil 8 or the FET 12 in which an abnormality has occurred, and the knitting is continued with another carriage. Further, the monitor 16 displays that a failure has occurred and its cause, and waits for maintenance. When the knitting machine is connected to the LAN, the occurrence of the abnormality and the cause thereof are output to the LAN. The reason why the knitting is stopped due to the occurrence of an abnormality is that, for example, when the coil 8 is short-circuited, the FET 12 fails next due to overcurrent, and when the FET 12 fails, the coil 8 is next short-circuited due to overcurrent.

実施例では以下の効果が得られる。
(1) アクチュエータのコイル8の短絡、制御用のスイッチ(FET12)の故障(短絡)、断線、並びに制御用IC4の故障の原因を特定しながら異常を検出できる。
(2) ピーク電流監視信号v1を用いることにより、アクチュエータのコイル8の短絡を確実に検出できる。
(3) 平均電流監視信号v2を用いることにより、FET12などのスイッチの故障を確実に検出できる。なおピーク電流監視信号v1ではFET12などのスイッチの故障は検出できず、また平均電流監視信号v2でコイル8の短絡を検出すると、コイル8をオンさせるデューテイ比を高くした場合との区別が難しい。
(4) コイル8の断線やFET12の周囲の断線などを検出できる。
(5) 制御IC4の内部異常や出力ピンの短絡等の異常を監視できる。
(6) 抵抗R2により短絡電流を制限し、異常がコイル8とFET12の間で2次的に拡大するのを遅らせることができる。
In the embodiment, the following effects can be obtained.
(1) Abnormalities can be detected while identifying the cause of the short circuit of the actuator coil 8, the failure (short circuit) of the control switch (FET 12), the disconnection, and the failure of the control IC 4.
(2) By using the peak current monitoring signal v1, a short circuit of the coil 8 of the actuator can be reliably detected.
(3) By using the average current monitoring signal v2, a failure of a switch such as the FET 12 can be reliably detected. Note that a failure of a switch such as the FET 12 cannot be detected with the peak current monitoring signal v1, and if a short circuit of the coil 8 is detected with the average current monitoring signal v2, it is difficult to distinguish from a case where the duty ratio for turning on the coil 8 is increased.
(4) Disconnection of the coil 8 or disconnection around the FET 12 can be detected.
(5) It is possible to monitor abnormalities such as internal abnormalities of the control IC 4 and output pin shorts.
(6) The resistance R2 can limit the short-circuit current and delay the secondary expansion of the abnormality between the coil 8 and the FET 12.

実施例の編機のアクチュエータの診断装置のブロック図Block diagram of the diagnosis device for the actuator of the knitting machine of the embodiment 変形例の電流監視用ICのブロック図Block diagram of a current monitoring IC of a modified example 図1の診断装置の波形図で、1)は回生用FETの制御信号Enの波形を、2)は選択アクチュエータの制御信号Pの波形を、3)は電流検出抵抗R2への電流iの波形を示す。In the waveform diagram of the diagnostic apparatus of FIG. 1, 1) shows the waveform of the control signal En of the regenerative FET, 2) shows the waveform of the control signal P of the selected actuator, and 3) shows the waveform of the current i to the current detection resistor R2. Indicates. 図1の診断装置の波形図で、1)は電流検出抵抗R2への電流iの波形を示し、2)はピーク電流監視信号v1を、3)は平均電流監視信号v2を、4)は断線監視信号v3の波形を、それぞれ示す。1) shows the waveform of the current i to the current detection resistor R2, 2) shows the peak current monitoring signal v1, 3) shows the average current monitoring signal v2, and 4) shows disconnection. The waveforms of the monitoring signal v3 are shown respectively. 制御ICの自己診断信号の波形図で、1)はクロック信号の監視を、2)はデータ信号の監視を、3)ロードパルス信号の監視を示す。In the waveform diagram of the self-diagnosis signal of the control IC, 1) shows monitoring of the clock signal, 2) shows monitoring of the data signal, and 3) shows monitoring of the load pulse signal. 実施例の制御フローチャートで、アクチュエータの異常を検出し、編機を停止させて異常原因を表示するまでの処理を示す。In the control flowchart of an Example, the process until it detects an abnormality of an actuator, stops a knitting machine, and displays the cause of abnormality is shown.

符号の説明Explanation of symbols

2 CPU
4 FPGA
6 PLD
8 選択アクチュエータのコイル
10,12 FET
14 故障処理部
16 表示部
18 ログファイル
20 バス
22 入力インターフェース
24 制御信号生成部
26 ロードパルスチェック部
28 データ信号チェック部
30 クロック信号チェック部
32〜36 コンパレータ
38,40 IC
42 ADコンバータ
44 比較電圧記憶部
46 比較部
48 出力インターフェース
D1 ダイオード
R1〜R5 抵抗
C1〜C3 コンデンサ
Vcc 電源
P 制御信号
v1 ピーク電流監視信号
v2 平均電流監視信号
v3 断線監視信号
e1〜e4 異常検出信号
2 CPU
4 FPGA
6 PLD
8 Selected actuator coil 10, 12 FET
14 Fault processing unit 16 Display unit 18 Log file 20 Bus 22 Input interface 24 Control signal generation unit 26 Load pulse check unit 28 Data signal check unit 30 Clock signal check unit 32-36 Comparator 38, 40 IC
42 AD Converter 44 Comparison Voltage Storage Unit 46 Comparison Unit 48 Output Interface D1 Diodes R1 to R5 Resistors C1 to C3 Capacitor Vcc Power Supply P Control Signal v1 Peak Current Monitoring Signal
v2 Average current monitoring signal v3 Disconnection monitoring signal
e1 to e4 error detection signal

Claims (4)

制御素子に接続されてパルス的に動作する負荷の異常を検出するようにした編機において、
前記負荷を流れる電流のピーク値を監視し、ピーク値が第1の所定値を越える場合に負荷の短絡を検出するための短絡検出手段と、
前記負荷を流れる電流の平均値を監視し、平均値が第2の所定値を越える場合に、制御素子の異常を検出するための平均値検出手段と、
負荷の短絡もしくは制御素子の異常を検出した際に、負荷の動作を停止させるための停止手段、とを設けたことを特徴とする編機。
In a knitting machine that is connected to a control element and detects a load abnormality that operates in a pulse manner,
Short-circuit detection means for monitoring a peak value of the current flowing through the load and detecting a short-circuit of the load when the peak value exceeds a first predetermined value;
An average value detecting means for monitoring an average value of the current flowing through the load and detecting an abnormality of the control element when the average value exceeds a second predetermined value;
A knitting machine, comprising: a stopping means for stopping the operation of the load when a short circuit of the load or an abnormality of the control element is detected.
前記制御素子を制御するための制御ICの出力ピン側の電位波形を監視するための手段をさらに設けて、制御ICの異常を検出するようにしたことを特徴とする、請求項1の編機。 2. The knitting machine according to claim 1, further comprising means for monitoring a potential waveform on the output pin side of the control IC for controlling the control element so as to detect an abnormality of the control IC. . 前記停止手段を異常検出時に負荷の電源を遮断するように構成し、さらに異常検出時に異常原因を出力するための手段とを設けたことを特徴とする、請求項1または2の編機。 The knitting machine according to claim 1 or 2, wherein the stopping means is configured to shut off a load power supply when an abnormality is detected, and further provided with means for outputting the cause of the abnormality when the abnormality is detected. 前記負荷がアクチュエータで、前記制御素子が該負荷をチョッパ制御することを特徴とする、請求項1〜3のいずれかの編機。 The knitting machine according to any one of claims 1 to 3, wherein the load is an actuator and the control element performs chopper control of the load.
JP2005344124A 2005-11-29 2005-11-29 Knitting machine Pending JP2007146336A (en)

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