JP6688131B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device that detects a structural defect caused by an initial defect or a random defect of a semiconductor integrated circuit element.

  Currently, IDDQ (quiescent power supply current) measurement is performed in a shipping test in order to prevent a defective product from leaking to the market. The IDDQ measurement is a method of measuring a minute power supply current flowing through a semiconductor integrated circuit element in a stationary state and detecting a structural failure of the semiconductor integrated circuit based on the magnitude of the measured value. However, the semiconductor integrated circuit is required to have higher reliability, and a means for detecting a structural defect of the semiconductor integrated circuit due to a random defect after the shipment of the IC is required not only when the IC is shipped. ing. Therefore, a semiconductor integrated circuit having an automatic inspection function has been developed in order to detect structural defects of elements in the semiconductor integrated circuit.

  The self-check type integrated circuit described in Patent Document 1 includes a current value detection unit, a main function unit, and a defect detection unit. When power is supplied to the self-check circuit, power is supplied to the main function unit via the current value detection unit. The current value detection unit outputs the current value flowing to the main function unit to the defect detection unit. The defect detection unit determines a defect based on the current value (value converted into voltage) input from the current detection unit, and sends out a defect detection signal. A diode is used as the current detector.

  When the forward current flowing through the diode increases, the forward voltage increases, and when the forward current decreases, the forward voltage decreases. Utilizing this characteristic, the upper limit value and the lower limit value of the forward voltage are set, and the defect of the main function unit is detected.

Japanese Patent No. 3171239

  In the self-check integrated circuit described in Patent Document 1, a large current difference is required to detect a defect by the diode. Further, the self-check circuit described in Patent Document 1 detects a defect during circuit operation. In this case, even if a part of the integrated circuit has a structural defect, the fluctuation of the current flowing through the circuit during the circuit operation is small. Therefore, defect detection is difficult.

  Therefore, an object of the present invention is to provide a semiconductor device capable of detecting a structural failure of a semiconductor integrated circuit with higher accuracy.

  In the present invention, the first main terminal of a transistor refers to an electrode into which a current flows into the transistor regardless of whether it is a MOS transistor or a bipolar transistor. Further, the second main terminal of the transistor means an electrode through which current flows from the transistor. For example, in an NMOS transistor, the first main terminal is the drain and the second main terminal is the source. The first main terminal of the PMOS transistor is the source and the second main terminal is the drain. In the NPN transistor, the first main terminal is the collector and the second main terminal is the emitter. The first main terminal of the PNP transistor is the emitter, and the second main terminal is the collector. The control terminal is an electrode that controls the current flowing from the first main terminal toward the second main terminal. The gate of the MOS transistor corresponds to the control terminal of the base of the bipolar transistor.

In the present invention, the main conductive path refers to a current path through which a current flows from the first main terminal toward the second main terminal.

In the present invention, the sleep mode refers to a circuit state in which the state of the circuit does not change with time. The normal mode refers to a circuit state in which the state of the circuit changes with time, that is, a circuit operation is being executed. In short, the normal mode is a circuit state other than the sleep mode.

  In the present invention, the circuit to be diagnosed refers to the circuit which is used for measuring the quiescent current while being transited or transited to two circuit states of the sleep mode and the normal mode.

In the present invention, the quiescent current means a circuit current flowing through the circuit to be diagnosed in the sleep mode.

  A semiconductor device according to the present invention has a circuit to be diagnosed that can shift or transition to a predetermined normal mode when a power supply voltage is supplied and to a predetermined sleep mode when a power supply voltage is supplied. When the circuit under test is in sleep mode, the current measurement circuit that converts the quiescent current of the circuit under test to a voltage and outputs it, and the magnitude of the voltage output from the current measurement circuit are compared with a predetermined reference voltage, and compared. It has a voltage comparison circuit for outputting the result.

  Further, the current measuring circuit which constitutes the diagnostic circuit includes a transistor having a first main terminal, a second main terminal, and a control terminal, and a main conductive path is formed between the first main terminal and the second main terminal. Have. Further, it has a resistor connected in parallel with the main conductive path, and a control signal for turning the transistor on or off is applied to the control terminal of the transistor, the transistor is turned on in the normal mode by the control signal, and the transistor is turned off in the sleep mode. The quiescent current is controlled so as to flow through the resistor.

  In addition, the quiescent current measured by the current measuring circuit of the diagnostic circuit is converted into the measured voltage by the resistance, and the measured voltage is compared with the reference voltage generated by the reference voltage generation circuit by the voltage comparison circuit, and the measured voltage is output from the voltage comparison circuit. A normal / abnormal determination signal indicating whether or not there is a failure in the diagnostic circuit is output.

  A semiconductor device that constitutes another diagnostic circuit uses a power supply terminal, an output terminal, a sleep notification terminal, and a quiescent current measurement terminal. Further, the semiconductor device includes a current measuring circuit and a voltage comparing circuit. The first power supply voltage is supplied to the current measuring circuit, but the first power supply voltage is supplied to the circuit to be diagnosed in the sleep mode, and the second power supply voltage is supplied through the power supply path different from the first power supply voltage in the normal mode. Is supplied. A switch is used so that the first power supply voltage or the second power supply voltage is selectively supplied to the power supply terminal which is also the quiescent current measuring terminal of the circuit to be diagnosed.

  According to the present invention, it is possible to provide a semiconductor device capable of detecting a structural defect of a semiconductor integrated circuit with higher accuracy.

It is a block diagram which shows the structure of the semiconductor device which concerns on the 1st Embodiment of this invention. FIG. 3 is a first circuit diagram showing a detailed configuration of the semiconductor device of FIG. 1. FIG. 3 is a second circuit diagram showing a detailed configuration of the semiconductor device of FIG. 1. FIG. 6 is a third circuit diagram showing a detailed configuration of the semiconductor device of FIG. 1. FIG. 6 is a fourth circuit diagram showing a detailed configuration of the semiconductor device of FIG. 1. It is a block diagram which shows the structure of the semiconductor device which concerns on the 2nd Embodiment of this invention. FIG. 4 is a circuit diagram showing a detailed configuration of the semiconductor device of FIG. 3. It is a block diagram which shows the structure of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is a block diagram which shows the structure of the semiconductor device which concerns on the 4th Embodiment of this invention. It is a block diagram which shows the structure of the semiconductor device which concerns on the 5th Embodiment of this invention. 8 is a timing chart showing an example of a determination signal of the semiconductor device of FIG. 7. 9 is a timing chart showing another example of the determination signal of the semiconductor device of FIG. 7. It is a block diagram which shows the structure of the semiconductor device which concerns on the 6th Embodiment of this invention. 11 is a table showing an example of determination signals of the semiconductor device of FIG. 10. It is a block diagram which shows the structure of the semiconductor device which concerns on the 7th Embodiment of this invention. FIG. 13 is a circuit diagram showing a detailed configuration of the semiconductor device of FIG. 12. FIG. 16 is a block diagram showing an example in which a diagnostic circuit according to the present invention is incorporated in a power supply regulator according to the eighth embodiment of the present invention. It is a circuit diagram which shows an example which applied the diagnostic circuit of FIG. 14 to the switching regulator which is one of the power supply regulators.

(First embodiment)
FIG. 1 is a block diagram showing the configuration of a semiconductor device 100a including a diagnostic circuit 1 according to the first embodiment of the present invention. Hereinafter, a semiconductor device 100a including the diagnostic circuit 1 of FIG. 1 will be described with reference to the drawings. In addition, those having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.

  The semiconductor device 100a of FIG. 1 includes a diagnostic circuit 1 and a circuit to be diagnosed 10. The diagnostic circuit 1 includes a current measurement circuit 20, a reference voltage generation circuit 30, and a voltage comparison circuit 40. The semiconductor device 100a also has a power supply terminal VDD, a ground terminal GND, a notification terminal T1, and an output terminal OUT. The power supply voltage Vdd is supplied to the power supply terminal VDD. The ground terminal GND is set to the ground potential.

The circuit to be diagnosed 10 has a sleep mode function and a timer 11. The current measuring circuit 20 of the diagnostic circuit 1 and the circuit to be diagnosed 10 are connected in series between the power supply terminal VDD and the ground terminal GND. The power supply voltage Vdd is supplied from the power supply terminal VDD to the circuit to be diagnosed 10 through the current measuring circuit 20. The circuit to be diagnosed 10 enters the sleep mode by the sleep mode function for a certain period after the supply of the power supply voltage Vdd is started. The sleep mode is a state in which the power supply voltage Vdd is supplied but the circuit under diagnosis 10 is not operating. When in the sleep mode, the circuit to be diagnosed 10 outputs the sleep signal S10 to the current measuring circuit 20 of the diagnostic circuit 1 via the signal line P10. As a result, the current measuring circuit 20 operates. As a result, the quiescent current I20 flows from the power supply terminal VDD to the circuit under test 10 through the current measuring circuit 20. The quiescent current means a current flowing through the circuit under diagnosis 10 when the circuit under diagnosis 10 is not operating. Here, when there is a structural defect in the circuit element inside the circuit to be diagnosed 10, a quiescent current I20 having a magnitude different from that when the circuit element has a normal structure flows. The structural failure is, for example, when the transistor inside the circuit to be diagnosed 10 is broken and the leak current is large, when the threshold voltage of the MOS transistor (metal oxide semiconductor field effect transistor) is largely deviated from the reference value, This is because the resistance value of the resistor largely deviates from the reference value due to variations, the capacitance of the capacitor largely deviates from the reference value due to variations, or the wiring is cut or short-circuited.

  The current measurement circuit 20 is connected to the voltage comparison circuit 40, generates a measurement voltage V20 according to the magnitude of the quiescent current I20 flowing through the circuit to be diagnosed 10, and outputs it to the voltage comparison circuit 40.

The reference voltage generation circuit 30 is connected to the voltage comparison circuit 40, generates at least one of the reference voltages V30a and V30b, and outputs it to the voltage comparison circuit 40. The reference voltages V30a and V30b serve as a reference for determining whether or not the measured voltage V20 is within a predetermined range. When the voltage comparison circuit 40 is composed of a window comparator, two reference voltages V30a and V30b are used. When the voltage comparison circuit 40 is composed of a single-stage comparator, it is sufficient to use either one of the reference voltages V30a and V30b.

The voltage comparison circuit 40 is connected to the notification terminal T1 of the semiconductor device 100a. For example, when the voltage comparison circuit 40 is composed of a single-stage comparator, the measured voltage V20 is compared with one of the reference voltages V30a and V30b, and the notification signal S40 is generated according to the comparison result, and the notification is sent. It is output to the terminal T1. For example, when the measurement voltage V20 is equal to or higher than the reference voltage V30a (V20 ≧ V30a), the voltage comparison circuit 40 outputs the high-level notification signal S40, and when the measurement voltage V20 is lower than the reference voltage V30 (V20 A low-level notification signal S40 is output to <V30a). When the notification signal S40 is at a low level, for example, there is a structural defect in the circuit element inside the circuit to be diagnosed 10, and when the notification signal S40 is at a high level, the inside of the circuit to be diagnosed 10 is diagnosed. A normal / abnormal determination is made assuming that the circuit element has no structural defect.

When a window comparator is used for the voltage comparison circuit 40, two reference voltages V30a and V30b are used. For example, when the measured voltage V20 is V30b ≦ V20 ≦ V30a, the diagnosis target circuit 10 is determined to be normal, and when V20 <V30b or V20> V30a, it is determined to be abnormal.

Note that another IC (Integrated Circuit) (not shown) is connected to the notification terminal T1 of the semiconductor device 100a. The notification signal S40 is input to the other IC (not shown) via the notification terminal T1. If the diagnosis result of the circuit to be diagnosed 10 is abnormal, another IC (not shown) stops the power supply to the semiconductor device 100a, stops the supply of the clock signal to the semiconductor device 100a, or the like (not shown). Control such as notifying the display device that the diagnosis result is abnormal is performed.

The circuit to be diagnosed 10 is connected to the output terminal OUT of the semiconductor device 100a, and the load 90 is connected to the output terminal OUT. The load 90 is, for example, a motor, an LED (light emitting diode), or the like. When the diagnosis result of the circuit under test 10 is normal, the sleep mode of the circuit under test 10 is released by the timer 11 after a lapse of a certain period from the start of supply of the power supply voltage Vdd. As a result, the circuit under test 10 transitions to the normal mode. In the normal mode, the circuit under test 10 does not output the sleep signal S10 to the current measuring circuit 20. Therefore, the current measuring circuit 20 stops its operation. As a result, the power supply voltage Vdd is supplied from the power supply terminal VDD to the circuit under test 10 via the current measuring circuit 20. As a result, the circuit to be diagnosed 10 outputs the output signal S100 to the output terminal OUT and drives the load 90.

When the circuit to be diagnosed 10 is in the normal mode, the current flowing through the circuit to be diagnosed 10 fluctuates greatly, so it is difficult to detect structural defects inside the circuit to be diagnosed 10. However, in the semiconductor device 100a according to the first embodiment of FIG. 1, when the circuit to be diagnosed 10 is in the sleep mode, the structural failure of the circuit element inside the circuit to be diagnosed 10 may occur due to the magnitude of the quiescent current I20. It is detected and output to the notification terminal T1 as the notification signal S40. Therefore, the structural failure of the semiconductor integrated circuit can be detected with higher accuracy. Moreover, since the circuit to be diagnosed 10 has a built-in sleep function, there is no need to externally enter the sleep mode.

The diagnosis circuit 1 may be connected between the circuit to be diagnosed 10 and the ground terminal GND. The reference voltage generation circuit 30 of the diagnostic circuit 1 may be provided outside the semiconductor device 100a. In this case, a terminal for inputting at least one of the reference voltages V30a and V30b is required, but it becomes easy to individually adjust the heights of the reference voltages V30a and V30b.

  FIG. 2A is a first circuit diagram showing a detailed configuration of the semiconductor device 100a including the diagnostic circuit 1 according to the first embodiment of the present invention in FIG. Hereinafter, a semiconductor device 100aa including the diagnostic circuit 1 of FIG. 2A will be described with reference to the drawings.

  The semiconductor device 100aa in FIG. 2A includes a diagnostic circuit 1 and a circuit to be diagnosed 10. The diagnostic circuit 1 includes a current measuring circuit 20aa, a reference voltage generating circuit 30, and a voltage comparing circuit 40. Further, the semiconductor device 100aa has a power supply terminal VDD, a ground terminal GND, a notification terminal T1, and an output terminal OUT. A power supply voltage Vdd is applied to the power supply terminal VDD. The ground terminal GND is set to the ground potential. The current measuring circuit 20aa and the circuit to be diagnosed 10 are connected in series, the current measuring circuit 20aa is connected to the power supply terminal VDD, and the circuit to be diagnosed 10 is connected to the ground terminal GND.

The circuit to be diagnosed 10 has a sleep mode function and a timer 11. The circuit to be diagnosed 10 is controlled so as to be able to shift between the two modes of the sleep mode and the normal mode. The current measuring circuit 20aa of the diagnostic circuit 1 includes a PMOS transistor (P-channel type metal oxide semiconductor field effect transistor) Q20aa and a resistor R20aa. The circuit under test 10 is connected between the drain D of the PMOS transistor Q20aa of the current measuring circuit 20aa and the ground terminal GND. The circuit to be diagnosed 10 is connected to the gate G of the PMOS transistor Q20aa of the current measuring circuit 20aa via the signal line P10. The source S of the PMOS transistor Q20aa of the current measuring circuit 20aa is connected to the power supply terminal VDD. The main conductive path of the PMOS transistor Q20aa is formed between the source S and the drain D. The main conductive path of the PMOS transistor Q20aa and the resistor R20aa are connected in parallel. The PMOS transistor Q20aa functions as a switch that short-circuits the resistor R20aa. The sleep signal S10 controls the gate G of the PMOS transistor Q20aa so that the PMOS transistor Q20aa is turned off when the circuit under test 10 is in the sleep mode and is turned on when the circuit under test 10 is in the normal mode.

When the circuit under test 10 is in the sleep mode, the sleep signal S10 is applied from the circuit under test 10 to the gate G of the PMOS transistor Q20aa so that the PMOS transistor Q20aa is turned off. Therefore, when the circuit under test 10 is in the sleep mode, the quiescent current I20 flows through the circuit under test 10 through the resistor R20aa. The quiescent current is a current flowing through the circuit to be diagnosed 10 in the sleep mode.

When the circuit under test 10 is in the normal mode, the sleep signal S10 is applied from the circuit under test 10 to the gate G of the PMOS transistor Q20aa so that the PMOS transistor Q20aa is turned on. Therefore, when the circuit to be diagnosed 10 is in the normal mode, a current flows between the main conductive path, that is, the source S and the drain D. Since the ON resistance when the PMOS transistor Q20aa is turned on, that is, the resistance value between the source S and the drain D is sufficiently smaller than the resistance value of the resistor R20aa, the PMOS transistor Q20aa of the power transistor VDD does not go through the resistor R20aa. Current is supplied to the circuit to be diagnosed 10 through the main conductive path.

The size of the resistor R20aa is determined by the power supply voltage Vdd, the quiescent current I20, the circuit configuration of the voltage comparison circuit 40, the dynamic range, and the like. The size of the resistor R20aa is, for example, 1 kΩ to 500 kΩ. The on resistance of the PMOS transistor Q20aa is, for example, 10 mΩ to 10Ω. Therefore, the resistance R20aa is in the range of 100 times to 50,000,000 times the ON resistance of the PMOS transistor. Considering the operation of the circuit under test 10 in the normal mode, the smaller the on resistance of the PMOS transistor, the better.

The drain D of the PMOS transistor Q20aa of the current measuring circuit 20aa is connected to the non-inverting input terminal (+) of the comparator CMP40 of the voltage comparison circuit 40. The resistor R20aa of the current measuring circuit 20 is connected in parallel with the main conductive path of the source S and the drain D of the PMOS transistor Q20aa.

The circuit to be diagnosed 10 enters the sleep mode by the sleep mode function for a certain period after the supply of the power supply voltage Vdd is started. In the sleep mode, the circuit to be diagnosed 10 outputs the sleep signal S10 to the gate G of the PMOS transistor Q20aa of the current measuring circuit 20aa of the diagnosis circuit 1 via the signal line P10. This turns off the PMOS transistor Q20aa of the current measuring circuit 20aa. As a result, the quiescent current I20 flows from the power supply terminal VDD to the circuit to be diagnosed 10 through the resistor R20aa of the current measuring circuit 20aa. Here, when there is a structural defect in the circuit element inside the circuit to be diagnosed 10, a quiescent current I20 having a magnitude different from that when the circuit element has a normal structure flows. The resistor R20aa of the current measurement circuit 20aa generates a measurement voltage V20 according to the magnitude of the quiescent current I20 and outputs it to the non-inverting input terminal (+) of the comparator CMP40 of the voltage comparison circuit 40.

The reference voltage generation circuit 30 includes a resistor R30 and a resistor R31. The resistors R30 and R31 are connected in series between the power supply terminal VDD and the ground terminal GND. The common connection point of the resistors R30 and R31 of the reference voltage generation circuit 30 is connected to the inverting input terminal (−) of the comparator CMP40 of the voltage comparison circuit 40. The voltage at the common connection point between the resistor R30 and the resistor R31 of the reference voltage generation circuit 30 is supplied to the inverting input terminal (−) of the comparator CMP40 of the voltage comparison circuit 40 as the reference voltage V30. The reference voltage generation circuit 30 generates a reference voltage (V30) for operating a voltage comparison circuit 40 described later. Note that, as described above, considering that the voltage comparison circuit 40 to be described later is composed of a window comparator, for example, two reference voltages V30a and V30b (not shown) are generated instead of the reference voltage V30. Is preferred.

The voltage comparison circuit 40 includes a comparator CMP40. The comparator CMP40 is used to detect whether or not the magnitude of the quiescent current I20 flowing through the resistor R20aa in the sleep mode is within a predetermined range. The output terminal of the comparator CMP40 is connected to the notification terminal T1 of the semiconductor device 100aa. The comparator CMP40 compares the measured voltage V20 with the reference voltage V30, generates a notification signal S40 according to the comparison result, and outputs the notification signal S40 to the notification terminal T1. For example, the voltage comparison circuit 40 outputs a high-level notification signal when the measurement voltage V20 is higher than the reference voltage V30, and outputs a low-level notification signal when the measurement voltage V20 is lower than the reference voltage V30. Is output. The voltage comparison circuit 40 shown in FIG. 2A is composed of one-stage comparator CMP40, but a window comparator may be composed of two or more comparators (not shown).

The circuit to be diagnosed 10 is connected to the output terminal OUT of the semiconductor device 100aa. A load 90 is connected to the output terminal OUT. The load 90 is, for example, a motor, an LED, or the like. When the diagnosis result of the circuit under test 10 is normal, the sleep mode of the circuit under test 10 is released by the timer 11 after a lapse of a certain period from the start of supply of the power supply voltage Vdd. As a result, the circuit under test 10 transitions to the normal mode. In the normal mode, the circuit under test 10 does not output the sleep signal S10, so the PMOS transistor Q20aa of the current measuring circuit 20aa is turned on. As a result, the power supply voltage Vdd is supplied from the power supply terminal VDD to the circuit to be diagnosed 10 through the PMOS transistor Q20aa of the current measuring circuit 20aa. As a result, the circuit to be diagnosed 10 outputs the output signal S100 to the output terminal OUT and drives the load 90. The power supply voltage Vdd may be directly supplied to a sleep signal generation circuit (not shown) for generating the sleep signal S10 in the circuit to be diagnosed 10. That is, the sleep signal S10 may be a driver output generated by directly supplying the power supply voltage Vdd.

When the circuit to be diagnosed 10 is operating in the normal mode, the current flowing through the circuit to be diagnosed 10 fluctuates greatly, so that it is difficult to detect a structural defect inside the circuit to be diagnosed 10. However, in the semiconductor device 100a according to the first embodiment of FIG. 2A, when the circuit to be diagnosed 10 is in the sleep mode, the structural failure of the circuit elements inside the circuit to be diagnosed 10 may occur due to the magnitude of the quiescent current I20. It is detected and output to the notification terminal T1 as the notification signal S40. Therefore, the structural failure of the semiconductor integrated circuit can be detected with higher accuracy.

2B differs from FIG. 2A in the current measuring circuit 20ab. In FIG. 2B, a bipolar PNP transistor Q20ab is used for the current measuring circuit 20ab. This is different from FIG. 2A. A resistor R20ab is connected in parallel with the main conductive path of the PNP transistor Q20ab. The resistance value of the resistor R20ab is, for example, 1 kΩ to 500 kΩ. The main conductive path of the PNP transistor Q20ab is formed between the emitter E and the collector C. A sleep signal S10 for turning on / off the PNP transistor Q20ab is applied to the base B of the PNP transistor Q20ab from the circuit under diagnosis 10 via the signal line P10. When the circuit under test 10 is in the normal mode, the PNP transistor Q20ab is on, and a current flows through the circuit under test 10 through its main conductive path. In the sleep mode, the PNP transistor Q20ab is off, and the quiescent current I20 flows through the circuit to be diagnosed 10 through the resistor R20ab. The quiescent current I20 is converted into a voltage by the resistor R20ab. The converted measurement voltage V20 is compared with the reference voltage V30 by the voltage comparison circuit 40. In FIG. 2B, the configuration other than the current measuring circuit 20ab is the same as that in FIG.

2C differs from FIG. 2A and FIG. 2B in the current measuring circuit 20ac. In FIG. 2C, a MOS transistor is used for the current measuring circuit 20ac. This point is the same as FIG. 2A, except that the current measuring circuit 20ac is connected to the ground potential GND side. The main conductive path of the NMOS transistor Q20ac is formed between the drain D and the source S. Similarly to FIG. 2A, in FIG. 2C, the resistance is connected in parallel with the main conductive path of the MOS transistor. The resistance value of the resistor R20ac is, for example, 1 kΩ to 500 kΩ. A sleep signal S10 for turning on / off the NMOS transistor Q20ac is applied from the circuit under diagnosis 10 to the gate G of the NMOS transistor Q20ac via the signal line P10. When the circuit under test 10 is in the normal mode, the NMOS transistor Q20ac is on, and the current flows through the circuit under test 10 through the main conductive path of the NMOS transistor Q20ac. In the sleep mode, the NMOS transistor Q20ac is off, and the quiescent current I20 flows from the circuit under diagnosis 10 to the ground potential GND side via the resistor R20ac. The quiescent current I20 is converted into a voltage by the resistor R20ac. The converted measurement voltage V20 is compared with the reference voltage V30 by the voltage comparison circuit 40. 2C is the same as FIG. 2A except that the current measuring circuit 20ac is connected to the ground terminal side and the circuit to be diagnosed 10 is connected to the power supply terminal VDD side, and therefore the description thereof is omitted.

2D differs from FIG. 2A, FIG. 2B, and FIG. 2C in the current measuring circuit 20ad. In FIG. 2D, a bipolar NPN transistor Q20ad is used for the current measuring circuit 20ad. This is different from FIG. 2B. The resistor R20ad is connected in parallel with the main conductive path of the NPN transistor Q20ad. The resistance value of the resistor R20ad is, for example, 1 kΩ to 500 kΩ. The main conductive path of the NPN transistor Q20ad is formed between the collector C and the emitter E. The sleep signal S10 for turning on / off the NPN transistor Q20ad is applied from the circuit under diagnosis 10 to the base B of the NPN transistor Q20ad via the signal line P10. When the circuit under test 10 is in the normal mode, the NPN transistor Q20ad is on, and a current flows from the circuit under test 10 through the main conductive path of the NPN transistor Q20ad. In the sleep mode, the NPN transistor Q20ad is off, and the quiescent current I20 flows from the circuit under diagnosis 10 side through the resistor R20ad. The quiescent current I20 is converted into a voltage by the resistor R20ad. The converted measurement voltage V20 is compared with the reference voltage V30 by the voltage comparison circuit 40. In FIG. 2D, the configuration other than the current measurement circuit 20ad is the same as that in FIGS. 2A, 2B, and 2C, and thus the description thereof is omitted.

In the first embodiment, in order for the circuit to be diagnosed 10 to generate the sleep signal S10, the sleep signal generation circuit (not shown) in the circuit to be diagnosed 10 is supplied with sufficient power to generate the sleep signal S10. There is a need. In order to stably output the sleep signal S10, a sleep signal generation circuit (not shown) in the circuit to be diagnosed 10 may be directly connected to the power supply terminal VDD or the ground terminal GND. This configuration does not depart from the gist of the present invention.

(Second embodiment)
FIG. 3 is a block diagram showing the configuration of a semiconductor device 100b including the diagnostic circuit 1 according to the second embodiment of the present invention. Hereinafter, a semiconductor device 100b including the diagnostic circuit 1 of FIG. 3 will be described with reference to the drawings.

The semiconductor device 100b of FIG. 3 is different from the semiconductor device 100a of FIG. 1 in the following points.

The signal line P10 of the semiconductor device 100b of FIG. 3 is connected to the current measurement circuit 20, the reference voltage generation circuit 30, and the voltage comparison circuit 40. That is, the sleep signal S10 simultaneously controls the current measuring circuit 20, the reference voltage generating circuit 30, and the voltage comparing circuit 40. The signal line P10 of the semiconductor device 100a of FIG. 1 is connected to the current measuring circuit 20.

When the circuit to be diagnosed 10 enters the sleep mode, it outputs a sleep signal S10 to the current measuring circuit 20, the reference voltage generation circuit 30, and the voltage comparison circuit 40 of the diagnostic circuit 1 via the signal line P10. As a result, the current measurement circuit 20, the reference voltage generation circuit 30, and the voltage comparison circuit 40 operate.

On the other hand, the diagnosed circuit 10 does not output the sleep signal S10 to the current measurement circuit 20, the reference voltage generation circuit 30, and the voltage comparison circuit 40 in the normal mode. Therefore, the current measurement circuit 20, the reference voltage generation circuit 30, and the voltage comparison circuit 40 stop their operations. As a result, the power consumption of the semiconductor device 100b of the second embodiment shown in FIG. 3 is lower than that of the semiconductor device 100a of the first embodiment shown in FIG.

  FIG. 4 is a circuit diagram showing a detailed configuration of a semiconductor device 100b including the diagnostic circuit 1 according to the second embodiment of the present invention in FIG. Hereinafter, a semiconductor device 100b including the diagnostic circuit 1 of FIG. 4 will be described with reference to the drawings.

The semiconductor device 100b of FIG. 4 differs from the semiconductor device 100aa of FIG. 2A in the following points.

In the semiconductor device 100b of FIG. 4, a constant current source CC30 is used instead of the resistor R30 of the reference voltage generation circuit 30 of the semiconductor device 100aa of FIG. 2A. Further, the reference voltage generation circuit 30 includes a switch SW30. The switch SW30 is connected between the constant current source CC30 and the resistor R31. The common connection point between the switch SW30 and the resistor R31 is connected to the inverting input terminal (−) of the voltage comparison circuit CMP40. For the switch SW30, for example, a PMOS transistor (P-channel type metal oxide semiconductor field effect transistor), a bipolar PNP transistor, or the like may be used.

In the semiconductor device 100b of FIG. 4, the voltage comparison circuit 40 includes a switch SW40. The switch SW40 is connected to the power supply path between the power supply terminal VDD and the comparator CMP40. A MOS transistor, a bipolar transistor, or the like may be used as the switch SW40.

The signal line P10 of the diagnostic circuit 1 of the semiconductor device 100b of FIG. 4 controls the gate G of the PMOS transistor Q20 of the current measurement circuit 20, the control terminal of the switch SW30 of the reference voltage generation circuit 30, and the switch SW40 of the voltage comparison circuit 40. Connected to the terminal. The signal line P10 of the diagnostic circuit 1 of the semiconductor device 100aa shown in FIG. 2A is connected to the gate G of the PMOS transistor Q20aa of the current measuring circuit 20.

When the circuit to be diagnosed 10 enters the sleep mode, the gate G of the PMOS transistor Q20 of the current measurement circuit 20, the control terminal of the switch SW30 of the reference voltage generation circuit 30, and the switch SW40 of the voltage comparison circuit 40 are connected via the signal line P10. The sleep signal S10 is output to the control terminal. As a result, the PMOS transistor Q20 of the current measuring circuit 20 is turned off, the switch SW30 of the reference voltage generation circuit 30 is turned on, and the switch SW40 of the voltage comparison circuit 40 is turned on. That is, when the circuit under diagnosis 10 enters the sleep mode, the current measurement circuit 20, the reference voltage generation circuit 30, and the voltage comparison circuit 40 operate.

On the other hand, in the normal mode, the diagnosed circuit 10 sleeps on the gate G of the PMOS transistor Q20 of the current measuring circuit 20, the control terminal of the switch SW30 of the reference voltage generation circuit 30, and the control terminal of the switch SW40 of the voltage comparison circuit 40. The signal S10 is not output. As a result, the PMOS transistor Q20 of the current measuring circuit 20 is turned on, the switch SW30 of the reference voltage generation circuit 30 is turned off, and the switch SW40 of the voltage comparison circuit 40 is turned off. That is, the current measurement circuit 20, the reference voltage generation circuit 30, and the voltage comparison circuit 40 stop their operations.

As described above, the circuit to be diagnosed 10 stops the operations of the current measurement circuit 20, the reference voltage generation circuit 30, and the voltage comparison circuit 40 when in the normal mode. Therefore, the power consumption of the semiconductor device 100b of the second embodiment of FIG. 4 is lower than that of the semiconductor device 100aa of the first embodiment of FIG. 2A.

In the second embodiment, in order for the circuit to be diagnosed 10 to generate the sleep signal S10, the sleep signal generating circuit (not shown) in the circuit to be diagnosed 10 is supplied with sufficient power to generate the sleep signal S10. There is a need. In order to stably output the sleep signal S10, a sleep signal generation circuit (not shown) in the circuit to be diagnosed 10 may be directly connected to the power supply terminal VDD or the ground terminal GND. This configuration does not depart from the gist of the present invention.

(Third Embodiment)
FIG. 5 is a block diagram showing the configuration of a semiconductor device 100c including the diagnostic circuit 1 according to the third embodiment of the present invention. Hereinafter, a semiconductor device 100c including the diagnostic circuit 1 of FIG. 5 will be described with reference to the drawings.

The semiconductor device 100c of FIG. 5 is different from the semiconductor device 100b of FIG. 3 in the following points.

A sleep terminal T2 is provided in the semiconductor device 100c of FIG. 5, and an external switch SW1 is connected to the sleep terminal T2 from outside the semiconductor device 100c. The external switch SW1 makes it possible to switch the on / off state of the sleep mode function. Note that the circuit to be diagnosed 10 of the semiconductor device 100b in FIG. 3 enters the sleep mode by the sleep mode function for a certain period after the supply of the power supply voltage Vdd is started.

In the semiconductor device 100c of FIG. 5, an external circuit (not shown) controls the external switch SW1 to switch the sleep mode function of the circuit under diagnosis 10 between on and off at an arbitrary timing. Therefore, the circuit to be diagnosed 10 can be diagnosed at any timing. In addition, depending on the external circuit configuration, it becomes possible to adjust the frequency of diagnosis of the circuit to be diagnosed 10. Further, by turning off the sleep mode function of the circuit to be diagnosed 10, it is possible to control so that the circuit to be diagnosed 10 is not repeatedly diagnosed.

The sleep mode function and the diagnostic function are separated, and a sleep mode function sleep terminal and terminal switch (not shown) and a diagnostic function sleep terminal and terminal switch (not shown) are provided, and only the sleep mode function terminal switch is effective. The sleep signal S10 is supplied only to the current measuring circuit when the switch state becomes such that the diagnosis function terminal switch and the sleep mode function terminal switch are both activated when the switch state becomes effective. May be supplied to the reference voltage generation circuit 30 and the voltage comparison circuit 40. In this case, the power consumption in the sleep mode is further reduced.

In the third embodiment, in order for the circuit to be diagnosed 10 to generate the sleep signal S10, the sleep signal generation circuit (not shown) in the circuit to be diagnosed 10 is supplied with sufficient power to generate the sleep signal S10. There is a need. In order to stably output the sleep signal S10, a sleep signal generation circuit (not shown) in the circuit to be diagnosed 10 may be directly connected to the power supply terminal VDD or the ground terminal GND. This configuration does not depart from the gist of the present invention.

(Fourth Embodiment)
FIG. 6 is a block diagram showing the configuration of a semiconductor device 100d including the diagnostic circuit 1 according to the fourth embodiment of the present invention. Hereinafter, a semiconductor device 100d including the diagnostic circuit 1 of FIG. 6 will be described with reference to the drawings.

The semiconductor device 100d of FIG. 6 is different from the semiconductor device 100b of FIG. 3 in the following points. The semiconductor device 100d of FIG. 6 further includes a communication terminal T3, and the circuit to be diagnosed 10 further includes a communication circuit 12 and a register 13.

The communication circuit 12 of the circuit under test 10 of the semiconductor device 100d is connected to the register 13 of the circuit under test 10. In addition to the normal setting data of the circuit to be diagnosed 10, the register 13 stores setting data regarding the on / off state of the sleep function. The communication circuit 12 of the circuit to be diagnosed 10 is connected to the communication terminal T3 of the semiconductor device 100d. The notification terminal T1 and the communication terminal T3 of the semiconductor device 100d are connected to the respective terminals of the microcomputer 200 outside the semiconductor device 100d. The semiconductor device 100d diagnoses the circuit to be diagnosed 10 when the circuit to be diagnosed 10 enters the sleep mode, and outputs the diagnosis result to the microcomputer 200 as a notification signal S40.

The microcomputer 200, via the notification terminal T3 of the semiconductor device 100d, for example, SPI (Serial Peripheral Interface) communication, IIC (Inter Integrated Circuit) communication, SENT (Single-Edge Nibble Transmission) communication of the circuit to be diagnosed 10 of the diagnosis circuit 10 and the like. The setting data of ON / OFF of the mode function is stored in the register 13 of the circuit under diagnosis 10 via the communication circuit 12 of the circuit under diagnosis 10. SPI communication is one of synchronous serial communication. The microcomputer 200 controls the on / off state of the sleep mode function of the circuit to be diagnosed 10 according to the setting data stored in the register 13. Further, the microcomputer 200 is connected to the power supply IC 300 and controls the power supply IC 300.

The power supply IC 300 is connected to the power supply terminal VDD of the semiconductor device 100d and supplies power to the semiconductor device 100d.

When it is determined that the circuit element inside the circuit to be diagnosed 10 has a structural defect, the microcomputer 200 controls the power supply IC 300 to stop the supply of power to the semiconductor device 100d. On the other hand, when it is determined that the structure of the circuit element is normal, the microcomputer 200 controls the power supply IC 300 so that the semiconductor device 100d operates normally and supplies power.

As described above, when the circuit to be diagnosed 10 includes the communication circuit 12, the timing of diagnosis of the semiconductor device 100d can be controlled by the microcomputer 200. As a result, the sleep mode function of the circuit to be diagnosed 10 can be switched on and off at an arbitrary timing to diagnose the circuit to be diagnosed 10. Further, it becomes possible to adjust the frequency of diagnosis of the circuit to be diagnosed 10. Further, by turning off the sleep mode function of the circuit to be diagnosed 10, it is possible to control so that the circuit to be diagnosed 10 is not repeatedly diagnosed.

Note that the sleep mode function and the diagnostic function are separated, the sleep mode function bit and the diagnostic function bit are provided in the register 13, and when the sleep mode function bit has a predetermined value, the sleep signal S10 is a current. The signal for diagnosis is supplied only to the measurement circuit, and the signal for diagnosis is supplied to the reference voltage generation circuit 30 and the voltage comparison circuit 40 only when both the sleep mode function bit and the diagnosis function bit have predetermined values. You may do it. In this case, the power consumption in the sleep mode is further reduced.

The notification signal S40 of the voltage comparison circuit 40 may be input to the communication circuit 12 of the circuit to be diagnosed 10, and the communication circuit 12 may notify the microcomputer 200 of the diagnosis result of the circuit to be diagnosed 10. In this case, the notification terminal T1 becomes unnecessary. Further, when the diagnosis result of the circuit to be diagnosed 10 is notified to the microcomputer 200, the microcomputer 200 may stop the operation of the circuit to be diagnosed 10 via the communication terminal T3.

In the fourth embodiment, in order for the circuit to be diagnosed 10 to generate the sleep signal S10, the sleep signal generating circuit (not shown) in the circuit to be diagnosed 10 is supplied with sufficient power to generate the sleep signal S10. There is a need. In order to stably output the sleep signal S10, a sleep signal generation circuit (not shown) in the circuit to be diagnosed 10 may be directly connected to the power supply terminal VDD or the ground terminal GND. This configuration does not depart from the gist of the present invention.

(Fifth Embodiment)
FIG. 7 is a block diagram showing the configuration of a semiconductor device 100e including the diagnostic circuit 1 according to the fifth embodiment of the present invention. Hereinafter, a semiconductor device 100e including the diagnostic circuit 1 of FIG. 7 will be described with reference to the drawings.

  The semiconductor device 100e of FIG. 7 differs from the semiconductor device 100b of FIG. 3 in the following points.

The semiconductor device 100e of FIG. 7 includes a determination signal generation circuit 50. The circuit to be diagnosed 10 is composed of a normal function block 14 and a safety measure function block 15. The notification signal S40 of the voltage comparison circuit 40 of the diagnosis circuit 1 is output to the safety countermeasure function block 15 of the circuit to be diagnosed 10. The safety measure function block 15 operates according to the notification signal S40 from the voltage comparison circuit 40, and controls the normal function block 14. The safety measure function block 15 outputs the control result of the normal function block 14 to the determination signal generation circuit 50 as a control result signal S11. The determination signal generation circuit 50 outputs the determination result according to the control result signal S11 to the notification terminal T1 as the determination signal S50.

When the diagnosis result of the circuit to be diagnosed 10 is normal, the safety countermeasure function block 15 generates the control result signal S11 indicating that the circuit to be diagnosed 10 is normal, and outputs it to the determination signal generation circuit 50. The determination signal generation circuit 50 generates the determination signal S50 indicating that the circuit under diagnosis 10 is normal, and outputs it to the notification terminal T1.

When the diagnosis result of the circuit to be diagnosed 10 is abnormal, the safety measure function block 15 performs the safety measure process on the normal function block 14 of the circuit to be diagnosed 10. Specifically, the safety countermeasure process is to stop the operation of the normal function block 14, fix the logic level of the normal function block 14, stop the power supply to the normal function block 14, and the like. After that, when the safety measure function block 15 receives a signal indicating that the safety measure process is completed from the normal function block 14 or a notification signal S40 indicating that the circuit under diagnosis 10 is normal from the voltage comparison circuit 40, A control result signal S11 indicating that the safety measure processing has been performed on the normal function block 14 is generated and output to the determination signal generation circuit 50. The determination signal generation circuit 50 generates a determination signal S50 indicating that the normal function block 14 has been subjected to the safety countermeasure process, and outputs the determination signal S50 to the notification terminal T1.

When the diagnosis result of the circuit to be diagnosed 10 is abnormal and the safety measure processing of the normal function block 14 of the circuit to be diagnosed 10 by the safety measure function block 15 is impossible, the safety measure function block 15 The control result signal S11 indicating that the safety measure processing for the normal function block 14 cannot be performed is generated and output to the determination signal generation circuit 50. The determination signal generation circuit 50 generates a determination signal S50 indicating that the safety measure processing for the normal function block 14 is impossible, and outputs it to the notification terminal T1. Here, when the safety measure processing is impossible, for example, when the signal indicating that the safety measure processing is completed is not returned from the normal function block 14 to the safety measure function block 15, the power supply of the normal function block 14 is stopped. This is a case where the notification signal S40 indicating that the diagnosis result of the circuit to be diagnosed 10 is abnormal despite being stopped is output from the voltage comparison circuit 40 to the safety measure function block 15. In the latter case, there is a structural defect in the safety measure function block 15 itself, and the normal operation of the safety measure function block 15 is not ensured, so it is determined that the safety measure process is impossible.

When the diagnosis result of the circuit to be diagnosed 10 is abnormal, the safety countermeasure function block 15 may block the signal to the I / O circuit (not shown). Further, the safety countermeasure function block 15 may control signals to other circuits (not shown) connected to the circuit to be diagnosed 10 to be fixed to a safe logic level of high level or low level.

As described above, when the circuit to be diagnosed 10 has a structural defect, the safety measure functional block 15 can stop the operation of the peripheral circuits, and the safety measure function block 15 can stop the operation of other circuits connected to the semiconductor device 100e. It is possible to prevent abnormal operation. Moreover, since the operation of the circuit to be diagnosed 10 is stopped, heat generation or the like of the circuit to be diagnosed can be prevented.

FIG. 8 is a timing chart showing an example of the determination signal S50 of the semiconductor device 100e including the diagnostic circuit 1 of FIG. The determination signal generation circuit 50 is configured to output the determination signal S50 at a ternary level. One of the three levels is the low level L and is set to 0V, for example. The two levels of the ternary level are intermediate levels, and are set to, for example, half the power supply voltage vdd. The three levels of the ternary level are high levels, and are set to the same level as the power supply voltage vdd, for example. In the method of outputting three values from the determination signal generation circuit 50, one output terminal is sufficient, but a circuit unit for generating an intermediate level is required. Hereinafter, a semiconductor device 100e including the diagnostic circuit 1 of FIG. 8 will be described with reference to FIG.

In the timing chart of FIG. 8, the vertical axis represents the voltage V of the determination signal S50 and the horizontal axis represents the time T.

The low level L from time T0 to time T1 indicates that the diagnosis result of the circuit under diagnosis 10 is normal. In this case, the voltage of the determination signal S50 is 0V. The intermediate level M from the time T1 to the time T2 indicates that the diagnosis result of the circuit to be diagnosed 10 is abnormal and the normal function block 14 has been subjected to the safety measure process. When the safety measure process is performed, specifically, the operation of the normal function block 14 is stopped, the logic level of the normal function block 14 is fixed, the power supply to the normal function block 14 is stopped, and the like. When the signal indicating that the safety measure process is completed is returned from the normal function block 14 to the safety measure process block 15, the state of the notification signal S40 is normally changed because the power supply to the normal function block 14 is stopped. Refers to cases etc. In these cases, the voltage of the determination signal S50 is set to Vdd / 2 which is 1/2 of the power supply voltage vdd. The high level after the time T2 indicates that the diagnosis result of the circuit to be diagnosed 10 is abnormal and the safety countermeasure function block 15 cannot perform the safety countermeasure process of the normal function block 14. In this case, the voltage of the determination signal S50 is at the same level as the power supply voltage Vdd. Here, after time T2, both the normal function block 14 and the safety measure function block 15 are in an abnormal state.

As described above, in the example of the determination signal S50 of FIG. 8, the determination result is distinguished by the difference in the three levels of the determination signal S50. At this time, a circuit for generating the three levels shown in FIG. 8 is required, and a circuit for determining the three levels is required on the side receiving the determination signal.

FIG. 9 shows a timing chart for outputting the determination signal S50 of the semiconductor device 100e including the diagnostic circuit 1 of FIG. 7 in a signal form different from the three-value level of FIG. Hereinafter, a semiconductor device 100e including the diagnostic circuit 1 of FIG. 9 will be described with reference to FIG.

In the timing chart of FIG. 9, the vertical axis represents the voltage V of the determination signal S50 and the horizontal axis represents the time T.

The low level L from time T0 to time T1 indicates that the diagnosis result of the circuit under diagnosis 10 is normal. In this case, the voltage of the determination signal S50 is low level L. The pulse signal in which the high level H and the low level L are repeated from the time T1 to the time T2 indicates that the diagnosis result of the circuit to be diagnosed 10 is abnormal, and the safety measure processing from the safety measure function block 15 to the normal function block 14 is performed. Has been applied. When the safety measure process is performed, specifically, the operation of the normal function block 14 is stopped, the logic level of the normal function block 14 is fixed, the power supply to the normal function block 14 is stopped, and the like. When the signal indicating that the safety measure processing is completed is returned from the normal function block 14 to the safety measure processing block 15, the state of the notification signal S40 is normally changed because the power supply to the normal function block 14 is stopped. Refers to cases etc. In these cases, the determination signal S50 has a pulse shape. After time T2, the diagnosis result of the circuit to be diagnosed 10 is abnormal, and the safety measure processing from the safety measure function block 15 to the normal function block 14 is also impossible. In this case, the voltage of the determination signal S50 holds the high level H. Here, after time T2, both the normal function block 14 and the safety measure function block 15 are in an abnormal state.

As described above, in the example of the determination signal S50 of FIG. 9, the determination result is distinguished by the determination signal S50 having a constant level or a pulse shape. As a result, the circuit for generating the ternary level shown in FIG. 8 is unnecessary. However, a logic circuit that generates a pulse signal is required, and a circuit that measures the pulse signal width is required on the side that receives the determination signal.

In the fifth embodiment, in order for the circuit to be diagnosed 10 to generate the sleep signal S10, the sleep signal generating circuit (not shown) in the circuit to be diagnosed 10 is supplied with sufficient power to generate the sleep signal S10. There is a need. In order to stably output the sleep signal S10, a sleep signal generation circuit (not shown) in the circuit to be diagnosed 10 may be directly connected to the power supply terminal VDD or the ground terminal GND. This configuration does not depart from the gist of the present invention.

(Sixth Embodiment)
FIG. 10 is a block diagram showing the configuration of a semiconductor device 100f including the diagnostic circuit 1 according to the sixth embodiment of the present invention. A semiconductor device 100f including the diagnostic circuit 1 of FIG. 10 will be described below with reference to the drawings.

The semiconductor device 100f of FIG. 10 is different from the semiconductor device 100e of FIG. 7 in the following points.

In the semiconductor device 100f of FIG. 10, two terminals, a notification terminal T1a and a notification terminal T1b, are used instead of the notification terminal T1 of the semiconductor device 100e of FIG. The determination signal generation circuit 50 outputs the determination signal S50a to the notification terminal T1a and outputs the determination signal S50b to the notification terminal T1b. In the semiconductor device 100f of FIG. 10, the determination signal S50a and the determination signal S50b are output in a different form from the determination signals shown in FIGS. 8 and 9. That is, the determination signal S50a and the determination signal 50b are output at either a high level or a low level. The notification terminal T1a and the notification terminal T1b are notified of the three states of the circuit to be diagnosed 10 by using the two signals of the determination signal S50a and the determination signal S50b.

As described above, in the semiconductor device 100f of FIG. 10, since two states of the circuit to be diagnosed 10 are represented by using two determination signals of high level or low level, two notification terminals are provided, but the determination signal generation circuit is provided. The circuit configuration of 50 becomes easy. Further, as will be described later, since two determination signals are output at high level or low level, selection of various circuit means connected to the subsequent stage of the determination signal generation circuit 50 becomes relatively easy.

FIG. 11 shows an example of the determination signals S50a and S50b of the semiconductor device 100f including the diagnostic circuit 1 of FIG.

When the diagnosis result of the circuit to be diagnosed 10 is normal, the determination signal generation circuit 50 generates the determination signal S50a of low level L and the determination signal S50b of low level L, and notifies the notification terminal T1a and the notification terminal T1b. Output each.

When the diagnosis result of the circuit to be diagnosed 10 is abnormal and the safety measure function block 15 performs the safety measure process on the normal function block 14, the determination signal generation circuit 50 outputs the low level L signal. The determination signal S50a and the determination signal S50b of high level H are generated. The low-level L determination signal S50a is output to the notification terminal T1a, and the high-level H determination signal S50b is output to the notification terminal T1b. In addition, when the safety measure process is performed, specifically, the operation of the normal function block 14 is stopped, the logic level of the normal function block 14 is fixed, and the power supply to the normal function block 14 is stopped. When a signal indicating that the safety measure process is completed is returned from the normal function block 14 to the safety measure process block 15 due to the above reasons, the power supply of the normal function block 14 is stopped, and the state of the notification signal S40 becomes normal. When changing, etc.

When the diagnosis result of the circuit to be diagnosed 10 is abnormal and the safety measure function block 15 cannot perform the safety measure process on the normal function block 14, the determination signal generation circuit 50 outputs the high level H signal. The determination signal S50a and the low level L determination signal S50b are generated. The determination signal S50a of high level H is output to the notification terminal T1a, and the determination signal S50b of low level L is output to the notification terminal T1b. Such a state indicates that both the normal function block 14 and the safety measure function block 15 are abnormal.

In addition, when the diagnosis result of the circuit to be diagnosed 10 is abnormal and the safety measure process to the normal function block 14 is impossible, the determination signal generation circuit 50 outputs the determination signal S50a of high level H and The high-level H determination signal S50b may be generated, the high-level H determination signal S50a may be output to the notification terminal T1a, and the high-level H determination signal S50b may be output to the notification terminal T1b.

In the sixth embodiment, in order for the circuit to be diagnosed 10 to generate the sleep signal S10, the sleep signal generating circuit (not shown) in the circuit to be diagnosed 10 is supplied with sufficient power to generate the sleep signal S10. There is a need. In order to stably output the sleep signal S10, a sleep signal generation circuit (not shown) in the circuit to be diagnosed 10 may be directly connected to the power supply terminal VDD or the ground terminal GND. This configuration does not depart from the gist of the present invention.

(Seventh embodiment)
FIG. 12 is a block diagram showing the configuration of a semiconductor device 100g including the diagnostic circuit 1 according to the seventh embodiment of the present invention. In order to have versatility as a diagnostic circuit, the circuit to be diagnosed 10 is connected not to the inside of the semiconductor device 100g but to the outside thereof. Hereinafter, a semiconductor device 100g including the diagnostic circuit 1 of FIG. 12 will be described with reference to the drawings.

The semiconductor device 100g of FIG. 12 differs from the semiconductor device 100a of FIG. 1 in the following points.

The semiconductor device 100g of FIG. 12 is provided with a sleep notification terminal T4 and a measurement terminal T5 as external terminals. The sleep notification terminal T4a and the measurement terminal T5a of the circuit to be diagnosed 10 are connected to the sleep notification terminal T4 and the measurement terminal T5 of the semiconductor device 100g, respectively.

When the sleep signal S10 is input from the sleep notification terminal T4a to the sleep notification terminal T4 of the semiconductor device 100g by the external diagnosed circuit 10, the current measurement circuit 20, the measurement terminal T5, and the measurement from the power supply terminal VDD of the semiconductor device 100g. The quiescent current I20 flows through the circuit to be diagnosed 10 through the terminal T5a.

The quiescent current I20 is converted into a measurement voltage V20 by the current measuring circuit 20 of the semiconductor device 100g. The measured voltage V20 is compared by the voltage comparison circuit 40 with the reference voltage V30 generated by the reference voltage generation circuit 30. Based on the comparison result between the measured voltage V20 and the reference voltage V30, the voltage comparison circuit 40 outputs the notification signal S40 to the notification terminal T1. For example, the voltage comparison circuit 40 outputs a high-level notification signal S40 when the measurement voltage V20 is equal to or higher than the reference voltage V30 (V20 ≧ V30), and when the measurement voltage V20 is lower than the reference voltage V30 (V20 < A low-level notification signal S40 is output to V30). For example, when the notification signal S40 is at a low level, there is a structural defect in the circuit element inside the circuit to be diagnosed 10, and when the notification signal S40 is at a high level, the circuit inside the circuit to be diagnosed 10 is present. A normal / abnormal determination is made on the assumption that there is no structural defect in the element.

Further, when the window comparator is used for the voltage comparison circuit 40, two of the reference voltage V30a and the reference voltage V30b are used. For example, when the measured voltage V20 is V30b ≦ V20 ≦ V30a, the diagnosis target circuit 10 is It is determined to be normal, and when V20 <V30b or V20> V30a, it is determined to be abnormal.

As described above, in the semiconductor device 100g of FIG. 12, the circuit to be diagnosed 10 is connected from the outside, so that the circuit to be diagnosed 10 can be easily replaced. Further, by exchanging the circuits 10 to be diagnosed, it is possible to diagnose a plurality of circuits 10 to be diagnosed.

In the seventh embodiment, in order for the circuit to be diagnosed 10 to generate the sleep signal S10, the sleep signal generating circuit (not shown) in the circuit to be diagnosed 10 is supplied with sufficient power to generate the sleep signal S10. There is a need. In order to stably output the sleep signal S10, a sleep signal generation circuit (not shown) in the circuit to be diagnosed 10 may be directly connected to the power supply terminal VDD or the ground terminal GND. This configuration does not depart from the gist of the present invention.

(Specific example of the seventh embodiment)
FIG. 13 is a circuit diagram showing a detailed configuration of a semiconductor device 100g including the diagnostic circuit 1 according to the seventh embodiment of the present invention in FIG. Hereinafter, a semiconductor device 100g including the diagnostic circuit 1 of FIG. 13 will be described with reference to the drawings.

The semiconductor device 100g of FIG. 13 is different from the semiconductor device 100aa of FIG. 1 in the following points.

The semiconductor device 100g of FIG. 13 is provided with a sleep notification terminal T4 and a measurement terminal T5 as external terminals. The sleep notification terminal T4a and the measurement terminal T5a of the circuit to be diagnosed 10 are connected to the sleep notification terminal T4 and the measurement terminal T5 of the semiconductor device 100g, respectively.

  The semiconductor device 100g of FIG. 13 includes the diagnostic circuit 1. The diagnostic circuit 1 includes a current measurement circuit 20, a reference voltage generation circuit 30, and a voltage comparison circuit 40.

The circuit to be diagnosed 10 has a sleep mode function and a timer 11. The sleep notification terminal T4a and the measurement terminal T5a of the circuit to be diagnosed 10 are connected to the sleep notification terminal T4 and the measurement terminal T5 of the semiconductor device 100g, respectively. The current measuring circuit 20 of the diagnostic circuit 1 of the semiconductor device 100g includes a PMOS transistor Q20 and a resistor R20. The circuit to be diagnosed 10 is connected to the gate G of the PMOS transistor Q20 of the current measuring circuit 20 via the sleep notification terminal T4a and the signal line P10. The source S of the PMOS transistor Q20 of the current measuring circuit 20 is connected to the power supply terminal VDD. The drain D of the PMOS transistor of the current measuring circuit 20 is connected to the non-inverting input terminal (+) of the comparator CMP40 of the voltage comparing circuit 40. The resistor R20 of the current measurement circuit 20 is connected between the power supply terminal VDD and the measurement terminal T5. The power supply voltage Vdd is supplied from the power supply terminal VDD to the measurement terminal T5a which is the power supply terminal of the circuit to be diagnosed 10 through the PMOS transistor Q20 of the current measurement circuit 20 and the measurement terminal T5.

When the circuit to be diagnosed 10 enters the sleep mode by the sleep mode function, it outputs the sleep signal S10 to the gate G of the PMOS transistor Q20 of the current measuring circuit 20 of the diagnosis circuit 1 via the sleep terminals T4a and T4 and the signal line P10. As a result, the PMOS transistor Q20 of the current measuring circuit 20 is turned off. As a result, the quiescent current I20 flows from the power supply terminal VDD to the circuit to be diagnosed 10 through the resistor R20 of the current measuring circuit 20 and the measuring terminals T5 and T5a. Here, when there is a structural defect in the circuit element inside the circuit to be diagnosed 10, a quiescent current I20 having a magnitude different from that when the circuit element has a normal structure flows. The resistance R20 of the current measuring circuit 20 generates a measurement voltage V20 according to the magnitude of the quiescent current I20. The measurement voltage V20 is output to the non-inverting input terminal (+) of the comparator CMP40 of the voltage comparison circuit 40.

The reference voltage generation circuit 30 includes a resistor R30 and a resistor R31. The resistors R30 and R31 are connected in series between the power supply terminal VDD and the ground terminal GND. The common connection point of the resistors R30 and R31 of the reference voltage generation circuit 30 is connected to the inverting input terminal (−) of the comparator CMP40 of the voltage comparison circuit 40. The voltage at the common connection point between the resistor R30 and the resistor R31 of the reference voltage generation circuit 30 is supplied to the inverting input terminal (−) of the comparator CMP40 of the voltage comparison circuit 40 as the reference voltage V30. Although the reference voltage generation circuit 30 is shown to be configured by a resistor, it may be configured by a bandgap voltage circuit, a combination of a transistor, a diode, a resistor, a constant current source, or the like.

The voltage comparison circuit 40 includes a comparator CMP40. The comparator CMP40 is connected to the power supply terminal VDD. The output terminal of the comparator CMP40 is connected to the notification terminal T1 of the semiconductor device 100g. The comparator CMP40 compares the measured voltage V20 with the reference voltage V30, generates a notification signal S40 according to the comparison result, and outputs the notification signal S40 to the notification terminal T1. The voltage comparison circuit 40 outputs, for example, a high-level notification signal when the measurement voltage V20 is equal to or higher than the reference voltage V30, and outputs a low-level notification signal when the measurement voltage V20 is lower than the reference voltage V30. Output. Although the voltage comparison circuit 40 is configured by one stage of the comparator CMP40, a window comparator may be configured by using two stages of comparators (not shown).

As described above, in the specific example of the semiconductor device 100g according to the seventh embodiment of FIG. 13, when the circuit to be diagnosed 10 is in the sleep mode, the internal circuit of the circuit to be diagnosed 10 is affected by the magnitude of the quiescent current I20. A structural defect of the circuit element is detected and output as a notification signal S40 to the notification terminal T1. Therefore, it is possible to detect a structural defect existing in the semiconductor integrated circuit, which is relatively difficult to detect, with higher accuracy. Further, in the semiconductor device 100g of FIG. 13, since the circuit under diagnosis 10 is connected from the outside, the circuit under diagnosis 10 can be easily replaced. Further, by exchanging the circuits to be diagnosed 10, it is possible to diagnose a plurality of circuits 10 to be diagnosed.

Although the PMOS transistor Q20 is used in FIG. 13, a quiescent current I20 may be supplied to the circuit to be diagnosed 10 by using a bipolar PNP transistor instead.

Alternatively, instead of using the PMOS transistor Q20 or a PNP transistor (not shown), an NMOS transistor or an NPN transistor may be used, and the quiescent current I20 may flow from the circuit under test 10 side as shown in FIGS. 2C and 2D.

(Eighth Embodiment)
FIG. 14 is a block diagram showing the configuration of a semiconductor device 100h including the diagnostic circuit 1 according to the eighth embodiment of the present invention. The semiconductor device 100h includes a power supply regulator. Hereinafter, the semiconductor device 100h will be described with reference to the drawings.

  The semiconductor device 100h in FIG. 14 includes a diagnostic circuit 1, a control circuit 60, a power supply regulator DR, an inverter INV, a switch SW60, and a switch SW61. Therefore, the semiconductor device 100h is different from the semiconductor device of FIGS. 1 to 14 in that it has various circuit parts in addition to the diagnostic circuit 1. The diagnostic circuit 1 includes a current measurement circuit 20, a reference voltage generation circuit 30, and a voltage comparison circuit 40. The semiconductor device 100h is provided with terminals such as a power supply terminal VDD, a ground terminal GND, an output terminal OUT, and a sleep terminal T4. The power supply regulator DR is used to supply a power supply voltage to the power supply terminal VCC of the circuit to be diagnosed 10, that is, the power supply terminal corresponding to the measurement terminal T5a shown in FIG. The power regulator DR is composed of a linear regulator such as a series regulator and a shunt regulator. The power regulator also includes a switching regulator described later. The power supply voltage Vin is supplied to the power supply regulator DR. The power supply voltage Vin is supplied via a power supply path different from the power supply voltage Vdd supplied to the current measuring circuit Vdd. The power supply voltage Vin and the power supply voltage Vdd may be the same or different depending on the circuit function of the circuit to be diagnosed 10. The output voltage Vout is taken out from the output of the power supply voltage power supply regulator DR. When the power supply regulator DR is composed of a linear regulator, the output voltage Vout is smaller than the power supply voltage Vin and Vout <Vin.

  Like the switch SW60, the switch SW61 has a first contact a and a second contact b. The first contact a of the switch SW61 is connected to the output terminal OUT. The second contact b of the switch SW61 is connected to the output of the power regulator DR. When the circuit to be diagnosed 10 is in the sleep mode, the connection between the first contact a and the second contact b of the switch SW61 is electrically insulated (off). As a result, the output voltage Vout of the power supply regulator DR is not applied to the circuit to be diagnosed 10. When the circuit to be diagnosed 10 is in the normal mode, the connection between the first contact a and the second contact b of the switch SW61 is short-circuited (turned on). As a result, the output voltage Vout of the power supply regulator DR is applied to the circuit to be diagnosed 10.

  Like the switch SW61, the switch SW60 has a first contact a and a second contact b. The first contact a of the switch SW60 is connected to the output terminal OUT. The second contact b of the switch SW60 is connected to the current measuring circuit 20 of the diagnostic circuit 1. When the circuit to be diagnosed 10 is in the sleep mode, the connection between the first contact a and the second contact b of the switch SW60 is electrically short-circuited (turned on). Thereby, the power supply voltage Vdd is applied to the circuit to be diagnosed 10 via the current measuring circuit 20. When the circuit to be diagnosed 10 is in the normal mode, the connection between the first contact a and the second contact b of the switch SW60 is electrically insulated (off). As a result, the circuit connection between the current measuring circuit 20 and the circuit to be diagnosed 10 is cut off (OFF). Note that, as shown in FIG. 13, the specific circuit configuration of the current measurement circuit 20 may be a parallel connection body in which the transistor SW20 and the resistor 20 are connected in parallel, or may be configured by the resistor R20 alone.

  The switch SW60 is turned on when the control signal S60 is at a high level and turned off when it is at a low level, for example. The switch SW61 is turned off when the control signal S60 is at a high level, and turned on when the control signal S60 is at a low level, for example. The inverter INV inverts the control signal S60. The control signal S60 is given to the switch SW60, and the signal inverted by the inverter INV is given to the switch SW61. As a result, the switch SW60 and the switch SW61 are turned on and off complementarily to each other. That is, when the switch SW60 is on, the switch SW61 is off. On the other hand, when the switch SW61 is on, the switch SW60 is off. The first contacts a of the two switches SW60 and SW61 are commonly connected to the output terminal OUT. Therefore, instead of the switch SW60 and the switch SW61, one changeover switch having these contacts as a common contact may be used.

  The control circuit 60 is connected to the power supply regulator DR, the control terminals of the switches SW60 and SW61, and the current measuring circuit 20 of the diagnostic circuit 1. Here, the control terminal of the switch SW60 and the control terminal of the switch SW61 correspond to, for example, a gate or a base when these switches are configured by MOS transistors or bipolar transistors, respectively. The control circuit 60 switches between operating the circuit to be diagnosed 10 in the normal mode or setting the sleep mode to the sleep mode to diagnose the circuit to be diagnosed 10 and to determine whether the circuit is normal or abnormal according to the sleep signal S10 from the circuit to be diagnosed 10. .

When the circuit to be diagnosed 10 is in the normal mode, the switch SW60 is turned off by the control signal S60. As a result, the operation of the current measuring circuit 20 is stopped. At this time, the switch SW61 operates in a complementary manner to the switch SW60, and thus is turned on. Therefore, the output voltage Vout generated based on the power supply voltage Vin supplied to the power supply regulator DR is supplied to the circuit to be diagnosed 10.

On the other hand, when the circuit to be diagnosed 10 is in the sleep mode, the switch SW60 is turned on by the control signal S60. As a result, the quiescent current I20 flowing through the circuit to be diagnosed 10 is converted into the measurement voltage V20 by the current measuring circuit 20. At this time, the switch SW61 is turned off, and the output voltage Vout generated based on the power supply voltage Vin supplied to the power supply regulator DR is cut off and not supplied to the circuit to be diagnosed 10. In the voltage comparison circuit 40, the measurement voltage V20 is compared with the reference voltage V30 generated by the reference voltage generation circuit 30, and the notification signal S40 based on the comparison result is output to the control circuit 60. For example, the voltage comparison circuit 40 outputs a high-level notification signal S40 when the measurement voltage V20 is equal to or higher than the reference voltage V30 (V20 ≧ V30), and when the measurement voltage V20 is lower than the reference voltage V30 (V20 < A low-level notification signal S40 is output to V30). When the notification signal S40 is, for example, low level, there is a structural defect in the circuit element inside the circuit to be diagnosed 10. When the notification signal S40 is high level, the circuit element inside the circuit to be diagnosed 10 is present. It is determined that there is no structural failure in the normal / abnormal state.

  When the diagnosis result of the circuit under test 10 is normal and the sleep mode of the circuit under test 10 is released, the semiconductor device 100h shifts or transitions the circuit under test 10 to the normal mode. On the other hand, when the diagnosis result of the circuit to be diagnosed 10 is abnormal, the power supply to the circuit to be diagnosed 10 is stopped. As a result, it is possible to prevent heat generation and the like due to the structural failure of the circuit to be diagnosed 10.

In FIG. 14, a power supply regulator DR using a linear regulator is shown. However, the power supply regulator of the diagnostic circuit applied to the present invention is not limited to the linear regulator, and for example, a switching regulator may be applied.

  FIG. 15 is a modification of the semiconductor device 100h including the diagnostic circuit 1 according to the eighth embodiment of the present invention shown in FIG. Hereinafter, the semiconductor device 100h will be described with reference to the drawings.

  The semiconductor device 100h of FIG. 15 includes a diagnostic circuit 1a, a diagnostic circuit 1b, a control circuit 60, a switching driver DRa, a switching driver DRb, a switch SW60a, and a switch SW60b. The semiconductor device 100h of FIG. 15 includes two sets of diagnostic circuits 1a and 1b, switching drivers DRa and DRb, and switches SW60a and switch SW60b, but the semiconductor device 100h includes one set or three or more sets of diagnostic circuits, switching drivers, and switches. May be included. The diagnostic circuit 1a includes a current measuring circuit 20a, a reference voltage generating circuit 30a, and a voltage comparing circuit 40a. The diagnostic circuit 1b includes a current measuring circuit 20b, a reference voltage generating circuit 30b, and a voltage comparing circuit 40b. An inductor La, an inductor Lb, a capacitor Ca, a capacitor Cb, a circuit under test 10a, and a circuit under test 10b are connected to the outside of the semiconductor device 100h. The semiconductor device 100h is provided with terminals such as a power supply terminal VDD, a ground terminal GND, an output terminal OUTa, an output terminal OUTb, a sleep terminal T4a, and a sleep terminal T4b. A MOS transistor, a bipolar transistor, or the like is used for the switch SW60a and the switch SW60b.

  The control circuit 60 is connected to the switching driver DRa, the control terminal of the switch SW20a, and the switch SW20a of the current measuring circuit 20a of the diagnostic circuit 1a. Further, the control circuit 60 is connected to the switching driver DRb, the control terminal of the switch SW60b, and the switch SW20b of the current measuring circuit 20b of the diagnostic circuit 1b. The control circuit 60 switches between normal operation of the circuit under test 10a and diagnosis of the circuit under test 10a according to the sleep signal S10a from the circuit under test 10a. Further, the control circuit 60 switches between normal operation of the circuit to be diagnosed 10b and diagnosis of the circuit to be diagnosed 10b according to the sleep signal S10b from the circuit to be diagnosed 10b.

  When the circuit to be diagnosed 10a is in the normal mode, the control circuit 60 sets the switch SW20a of the current measurement circuit 20a to the off state and the switch SW60a to the on state by the control signal S60a to control the switching driver DRa. As a result, the circuit under test 10a operates normally. The switch SW20a and the switch SW60a are turned on / off in a complementary manner. When the circuit to be diagnosed 10a is in the sleep mode, the control circuit 60 turns off the switch SW60a by the control signal S60a to stop the operation of the switching driver DRa and turns off the switch SW20a of the current measuring circuit 20a. By doing so, the diagnosis of the circuit to be diagnosed 10a is performed.

  The switching driver DRa and the switch SW60a are connected in series between the control circuit 60 and the output terminal OUTa, and drive the diagnosis target circuit 10a connected to the output terminal OUTa of the semiconductor device 100h based on the signal from the control circuit 60. To do. The switching driver DRa in the semiconductor device 100h is a power supply voltage supply unit that forms a part of a switching regulator that is an example of a power supply regulator.

  An inductor La is connected between the output terminal OUTa of the semiconductor device 100h and the circuit to be diagnosed 10a. A capacitor Ca is connected between the inductor La and the ground terminal GND. The inductor La and the capacitor Ca form a smoothing circuit. A DC voltage is generated at the common connection point between the inductor La and the capacitor Ca. This DC voltage is supplied to the power supply terminal VCC1 of the circuit to be diagnosed 10a. The power supply terminal VCC1 corresponds to the measurement terminal T5a shown in FIG. A switching regulator is configured by the switching driver DRa in the semiconductor device 100h and a smoothing circuit connected to the outside of the semiconductor device 100h.

The circuit to be diagnosed 10a has a sleep mode function. When the circuit under test 10a enters the sleep mode by the sleep mode function, the circuit under test 10a outputs the sleep signal S10a to the control circuit 60 via the signal line P10a and the sleep notification terminal T4a of the semiconductor device 100h.

  The current measuring circuit 20a includes a resistor R20a and a switch SW20a. The resistor R20a and the switch SW20a are connected in series between the power supply terminal VDD and the output terminal OUTa of the semiconductor device 100h. The current measurement circuit 20a generates a measurement voltage V20a corresponding to the magnitude of the quiescent current I20a flowing from the power supply terminal VDD to the circuit under test 10a via the resistor R20a and the output terminal OUTa of the semiconductor device 100h, and the voltage comparison circuit 40a. Output to. The switch SW20a is composed of, for example, a MOS transistor, a bipolar transistor, or the like.

The reference voltage generation circuit 30a includes a reference voltage source VREFa and is connected between the voltage comparison circuit 40a and the ground terminal GND. The reference voltage generation circuit 30a generates a reference voltage V30a by the reference voltage source VREFa and outputs it to the voltage comparison circuit 40a.

The voltage comparison circuit 40a is composed of a comparator CMP40a. The non-inverting input terminal (+) of the comparator CMP40a is connected to the common connection point of the resistor R20a of the current measuring circuit 20a and the switch SW20a. The inverting input terminal (-) of the comparator CMP40a is connected to the reference voltage source VREFa of the reference voltage generation circuit 30a. The output terminal of the comparator CMP40a is connected to the control circuit 60. The voltage comparison circuit 40a compares the measurement voltage V20a with the reference voltage V30a, generates a notification signal S40a according to the comparison result, and outputs the notification signal S40a to the control circuit 60. The voltage comparison circuit 40a outputs, for example, a high-level notification signal S40a when the measurement voltage V20a is equal to or higher than the reference voltage V30a, and a low-level notification signal S40a when the measurement voltage V20a is lower than the reference voltage V30a. Outputs S40a.

  When the diagnosis result of the circuit under test 10a is normal and the sleep mode of the circuit under test 10a is released, the semiconductor device 100h causes the circuit under test 10a to operate in the normal mode. On the other hand, when it is determined that the diagnosis result of the circuit to be diagnosed 10a is abnormal, the power supply to the circuit to be diagnosed 10a is stopped. As a result, it is possible to prevent heat generation and the like due to the structural failure of the circuit to be diagnosed 10a.

  When the circuit under diagnosis 10b is not in the sleep mode, the control circuit 60 turns off the switch SW20b of the current measuring circuit 20b and turns on the switch SW60b by the control signal S60b to control the switching driver DRb. By doing so, the circuit to be diagnosed 10b is normally operated. The switch SW20b and the switch SW60b have an antithetical relationship with each other. On the other hand, when the circuit to be diagnosed 10b is in the sleep mode, the switch SW60b is turned off by the control signal S60b, the operation of the switching driver DRb is stopped, and the circuit to be diagnosed is controlled by controlling the current measuring circuit 20b. Diagnosis of 10b is performed.

  The switching driver DRb and the switch SW60b are connected in series between the control circuit 60 and the output terminal OUTb, and drive the diagnosis target circuit 10b connected to the output terminal OUTb of the semiconductor device 100h based on the signal from the control circuit 60. To do. The switching driver DRb in the semiconductor device 100h is a power supply voltage supply unit that forms part of a switching regulator that is an example of a power supply regulator.

  The inductor Lb is connected between the output terminal OUTb of the semiconductor device 100h and the circuit to be diagnosed 10b. The capacitor Cb is connected between the inductor Lb and the ground terminal GND. A smoothing circuit is configured by the inductor Lb and the capacitor Cb. A DC voltage is generated at the common connection point between the inductor Lb and the capacitor Cb. This DC voltage is supplied to the power supply terminal VCC2 of the circuit to be diagnosed 10b. The power supply terminal VCC2 corresponds to the measurement terminal T5a shown in FIG. A switching regulator is configured by the switching driver DRb in the semiconductor device 100h and a smoothing circuit connected to the outside of the semiconductor device 100h.

The circuit to be diagnosed 10b has a sleep mode function. When the circuit under test 10b enters the sleep mode by the sleep mode function, the circuit under test 10b outputs the sleep signal S10b to the control circuit 60 via the signal line P10b and the sleep notification terminal T4b of the semiconductor device 100h.

  The current measuring circuit 20b includes a resistor R20b and a switch SW20b. The resistor R20b and the switch SW20b are connected in series between the power supply terminal VDD and the output terminal OUTb of the semiconductor device 100h. The current measurement circuit 20b generates a measurement voltage V20b according to the magnitude of the quiescent current I20b flowing from the power supply terminal VDD to the circuit under test 10b via the resistor R20b and the output terminal OUTb of the semiconductor device 100h, and the voltage comparison circuit 40b. Output to. As the switch SW20b, for example, a MOS transistor, a bipolar transistor or the like may be used.

The reference voltage generation circuit 30b includes a reference voltage source VREFb and is connected between the voltage comparison circuit 40b and the ground terminal GND. The reference voltage generation circuit 30b generates the reference voltage V30b by the reference voltage source VREFb and outputs it to the voltage comparison circuit 40b.

The voltage comparison circuit 40b is composed of a comparator CMP40b. The non-inverting input terminal (+) of the comparator CMP40b is connected to a common connection point between the resistor R20b of the current measuring circuit 20b and the switch SW20b. The inverting input terminal (−) of the comparator CMP40b is connected to the reference voltage source VREFb of the reference voltage generation circuit 30b. The output terminal of the comparator CMP40b is connected to the control circuit 60. The voltage comparison circuit 40b compares the measured voltage V20b with the reference voltage V30b, generates a notification signal S40b according to the comparison result, and outputs the notification signal S40b to the control circuit 60. The voltage comparison circuit 40b outputs, for example, a low-level notification signal S40b when the measurement voltage V20b is equal to or higher than the reference voltage V30b, and a high-level notification signal S40b when the measurement voltage V20b is lower than the reference voltage V30b. Outputs S40b.

  When the diagnosis result of the circuit under test 10b is normal and the sleep mode of the circuit under test 10b is released, the semiconductor device 100h causes the circuit under test 10b to operate normally. On the other hand, when the diagnosis result of the circuit to be diagnosed 10b is abnormal, the power supply to the circuit to be diagnosed 10b is stopped. As a result, it is possible to prevent heat generation and the like due to the structural failure of the circuit to be diagnosed 10a.

As described above, the semiconductor device 100h can control and diagnose the plurality of circuits 10a and 10b to be diagnosed. The plurality of circuits to be diagnosed 10a and the circuit to be diagnosed 10b may be diagnosed simultaneously or separately.

  In addition, about the said 1st-8th embodiment, all the structures may be applied simultaneously and only a required structure may be applied independently. Further, various technical features disclosed in this specification can be modified in various ways other than the above-described embodiment without departing from the spirit of the technical creation.

  The present invention can be applied to all semiconductor integrated circuit devices. Therefore, the present invention has high industrial applicability.

1, 1a, 1b Diagnostic circuit 10, 10a, 10b Diagnostic circuit 11 Timer 12 Communication circuit 13 Register 14 Normal function block 15 Safety measure function block 20, 20a, 20b Current measuring circuit 30, 30a, 30b Reference voltage generation circuit 40, 40a, 40b Voltage comparison circuit 50 Judgment signal generation circuit 60 Control circuit 90 Load 100a, 100b, 100c, 100d, 100e, 100f, 100g, 100h Semiconductor device 200 Microcomputer 300 Power supply IC
C, Ca, Cb Capacitor CC30 Constant current source CMP40, CMP40a, CMP40b Comparator D Drain DR Power regulator DRa, DRb Switching driver G Gate GND Ground terminal I20 Quiescent current L, La, Lb Inductor OUT, OUTa, OUTb Output terminal Q20, Q20aa PMOS transistor Q20ab PNP transistor Q20ac NMOS transistor Q20ad NPN transistor P10, P10a, P10b Signal line R20, R20a, R20b, R30, R31 Resistance S source S10, S10a, S10b Sleep signal S11 Control result signal S40, S40a, S40b Notification signal S50, S50a, S50b Judgment signal S60, S60a, S60b Control signal S100 Output signal SW1, S W20a, SW20b, SW30, SW40, SW60, SW60a, SW60b Switches T1, T1a, T1b Notification terminal T2 Sleep terminal T3 Communication terminals T4, T4a, T4b Sleep notification terminal T5, T5a Measuring terminals V20, V20a, V20b Measuring voltage V30, V30a , V30b Reference voltage VDD Power supply terminal Vdd, Vin Power supply voltage Vout, Vouta, Voutb Output voltage VREFa, VREFb Reference voltage source

Claims (23)

A semiconductor device that can be connected to a circuit under diagnosis that can be switched between a normal mode and a sleep mode,
A current measurement circuit that converts the quiescent current of the circuit under test into a voltage and outputs the voltage when the circuit under test is in the sleep mode;
A voltage comparison circuit that compares the voltage output from the current measurement circuit with a predetermined reference voltage, and outputs the comparison result as a notification signal that selectively indicates normality and abnormality of the circuit to be diagnosed,
Output terminal,
A power supply voltage supply unit that constitutes a part or all of a power supply regulator and supplies a power supply voltage to the power supply terminal of the circuit to be diagnosed via the output terminal;
A semiconductor device having. The semiconductor device is
A first switch connected between the power supply voltage supply section and the output terminal;
A second switch connected between the current measuring circuit and the output terminal, the second switch operating complementarily to the first switch;
In the normal mode, the first switch is turned on to supply the power supply voltage to the circuit to be diagnosed, and in the sleep mode, the second switch is turned on to cause the current measuring circuit to perform the diagnosis. The semiconductor device according to claim 1 , wherein the quiescent current of the circuit is converted into a voltage and output. The semiconductor device receives a sleep signal indicating whether the circuit under test is in a normal mode or a sleep mode from the circuit under test, and turns on / off the first switch and the second switch based on the sleep signal. The semiconductor device according to claim 2 , further comprising a switching control circuit. The power voltage supply unit is a power supply regulator, the semiconductor device according to any one of claims 1 to 3. The power supply voltage supply unit includes a switching driver forming a part of a power supply regulator,
An inductor is connected between the output terminal of the semiconductor device and the power supply terminal of the circuit to be diagnosed, a capacitor is connected between the power supply terminal of the circuit to be diagnosed and a ground potential, and the inductor and the by a capacitor, a semiconductor device according to any one of the power regulator of the smoothing circuit is constituted claims 1-3. Wherein the diagnostic circuitry includes a timer for setting the sleep mode, the semiconductor device according to any one of claims 1-5. Further comprising a reference voltage generation circuit for generating the predetermined reference voltage,
The voltage comparator circuit and the reference voltage generating circuit turned off in the normal mode, the semiconductor device according to any one of claims 1-6. A diagnostic circuit that can switch between normal mode and sleep mode,
A current measurement circuit that converts the quiescent current of the circuit under test into a voltage and outputs the voltage when the circuit under test is in the sleep mode;
A voltage comparison circuit that compares the voltage output from the current measurement circuit with a predetermined reference voltage, and outputs the comparison result as a notification signal that selectively indicates normality and abnormality of the circuit to be diagnosed,
Have a,
The semiconductor device , wherein the circuit to be diagnosed includes a timer for setting the sleep mode . A diagnostic circuit that can switch between normal mode and sleep mode,
A current measurement circuit that converts the quiescent current of the circuit under test into a voltage and outputs the voltage when the circuit under test is in the sleep mode;
A voltage comparison circuit that compares the voltage output from the current measurement circuit with a predetermined reference voltage, and outputs the comparison result as a notification signal that selectively indicates normality and abnormality of the circuit to be diagnosed,
A reference voltage generation circuit for generating the predetermined reference voltage,
Have a,
The semiconductor device , wherein the voltage comparison circuit and the reference voltage generation circuit are turned off in the normal mode . Wherein the diagnostic circuit and the current measuring circuit is connected in series between the power supply terminal and a ground potential power supply voltage is supplied, the current measuring circuit is connected to the power supply terminal side, to claim 8 or 9 The semiconductor device described. Wherein the diagnostic circuit and the current measuring circuit is connected in series between the power supply terminal and a ground potential power supply voltage is supplied, the current measuring circuit is connected to the ground potential, to claim 8 or 9 The semiconductor device described. The current measuring circuit is
A transistor having a first main terminal, a second main terminal, and a control terminal in which a main conductive path is formed between the first main terminal and the second main terminal;
A resistor connected in parallel with the main conductive path,
The circuit to be diagnosed supplies a control signal to the control terminal of the transistor to turn on the transistor in the normal mode and to turn off the transistor in the sleep mode, and a voltage due to the quiescent current flowing through the resistor in the sleep mode. Output the drop as the voltage,
The transistor, wherein in the normal mode current to the diagnostic circuit and the main path is connected in series to flow, the semiconductor device according to any one of claims 8-11. The semiconductor device according to claim 12 , wherein the transistor is a P-channel MOS transistor or a PNP bipolar transistor. The semiconductor device according to claim 12 , wherein the transistor is an N-channel MOS transistor or an NPN bipolar transistor. The voltage comparator circuit includes a comparator or window comparator, the semiconductor device according to any one of claims 1-14. The voltage comparison circuit includes the window comparator,
The window comparator determines whether the voltage output from the current measuring circuit is out of a predetermined range, and when the voltage output from the current measuring circuit is out of the predetermined range, the circuit to be diagnosed is The semiconductor device according to claim 15 , which outputs the notification signal indicating an abnormality.   The circuit to be diagnosed has an external terminal for receiving an external signal for setting the normal mode and the sleep mode, and is switched to the normal mode or the sleep mode based on the external signal. The semiconductor device according to claim 1.   18. The semiconductor device according to claim 17, wherein the external terminal of the circuit to be diagnosed receives the external signal from an external microcomputer.   19. The semiconductor device according to claim 18, wherein the voltage comparison circuit notifies the microcomputer of the notification signal. The circuit to be diagnosed is
Normal function block that operates as main function circuit,
Having a safety measure function block for maintaining the normal function block in a safe circuit state,
The semiconductor device is
20. The semiconductor device according to claim 1, further comprising a determination signal generation circuit that is connected to the safety countermeasure function block and outputs a determination signal indicating a state of the safety countermeasure function block.   The semiconductor device according to claim 20, wherein the determination signal is a ternary signal.   The semiconductor device according to claim 20, wherein the determination signal is a pulse signal.   21. The determination signal according to claim 20, wherein the determination signal includes a first signal selectively indicating normality and abnormality of the normal function block and a second signal selectively indicating normality and abnormality of the safety measure function block. Semiconductor device.

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