JP2013195291A - Voltage change detecting circuit and voltage change detecting method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a voltage change detecting circuit capable of simply detecting a gate leak of an insulated gate transistor irrespective of whether the device is in operation or not.SOLUTION: A voltage change detecting circuit 1 includes: a driving circuit 1a which applies a voltage Vg exceeding a gate threshold voltage of an insulated gate transistor 3 to a gate of the insulated gate transistor 3; a current source 1b which applies an amount of current for a prescribed time so that the gate voltage Vg of the insulated gate transistor 3 is less than the threshold voltage, during a cutoff period when voltage application is not being executed from the driving circuit 1a to the gate of the insulated gate transistor 3; and comparing means 1d for comparing a gate voltage change amount at the time of current application from the current source 1b to the gate of the insulated gate transistor 3 with a reference voltage change amount that is a reference value for determining whether a gate leak is generated or not, and then outputting a comparison result.

Description

  The present invention relates to a circuit capable of detecting gate leakage of an insulated gate transistor.

  Power semiconductor elements such as MOS transistors such as DMOS (Double-Diffused MOSFET) and LDMOS (Laterally Double-Diffused MOSFET), IGBT (Insulated Gate Bipolar Transistor), and so on are subjected to high current and high current flows. For this reason, it is important to detect element failures and element failures. The defective characteristics of the manufactured element may not cause sufficient performance of the element, and may further cause deterioration of characteristics during use, causing a short circuit failure or a disconnection failure. During use, if a short circuit failure occurs among the plurality of elements connected in series, a large voltage is applied to the remaining healthy elements, and disconnection occurs in the plurality of elements connected in parallel. If something that causes a failure occurs, current concentrates on the remaining healthy elements, which is dangerous and can cause many elements to be destroyed at once.

  Therefore, for such power semiconductor elements, especially insulated gate type semiconductor elements, element defect and element failure detection methods have been proposed.

  Patent Document 1 discloses a method for measuring gate leakage currents of MOSFETs 24A, 24B, 26A, and 26B used in a motor drive circuit as shown in FIG. This is because the positive and negative power terminals 28 and 30 of the inverter circuit 16 are connected to the ammeter 38 before the inverter circuit 16 of the motor drive circuit is connected to the power source, and the reverse flow from the gate is detected from the inspection pad 42. A test voltage is applied to the gates of the MOSFETs 24A, 24B, 26A, and 26B through the forward direction of the diodes 22A to 22D connected in the blocking direction. If there is a leak between the gate and the source, the leak current flows from the source to the ammeter 38 via the power supply terminals 28 and 30 and is measured.

  Patent Document 2 discloses a method for detecting a short-circuit failure and a disconnection failure of an insulated gate transistor. This is to detect the on-gate current flowing from the gate drive circuit to the gate capacitance when the device is ON and the off-gate current flowing from the gate capacitance to the gate drive circuit when the device is OFF, and the magnitude of the normal on-gate current and off-gate current. By performing the comparison, it is detected whether the failure in the active region is a short-circuit failure or a disconnection failure (not shown).

  Patent Document 3 discloses a method of measuring a leakage current at a PN junction for a general semiconductor element having a PN junction. As a result, the leakage current of the PN junction included in the MOS transistor can also be measured (not shown).

JP 2010-75025 A JP 2007-202238 A JP 2008-58313 A

  However, in the technique of Patent Document 1, the gate leak is detected only at the time of product shipment inspection. Therefore, the gate leak cannot be detected during the circuit operation, and the functional safety requirement cannot be met. Further, in order to detect gate leakage, an inspection apparatus must be used, and a dedicated pad for inspection is required on the product side.

  In the technique of Patent Document 2, short-circuit faults and disconnection faults can be detected during the operation of the element. However, since these faults are detected using normal characteristics of the gate capacitance, the principle Therefore, gate leak cannot be detected. Further, when the element is held in the ON state or the OFF state, failure detection cannot be performed. Furthermore, since the gate leak is very small compared to the gate current, to detect the gate leak from the measurement of the gate current based on the technique of Patent Document 2 requires a very high-precision detection circuit. So it's not realistic.

  In the technique of Patent Document 3, it is possible to detect a PN junction leak, but it is not possible to detect a gate leak.

  The present invention solves the above-described problem, and by detecting a change in the gate voltage of an insulated gate transistor, it is possible to easily detect a gate leak regardless of whether the element is operating. An object of the present invention is to provide a voltage change detection circuit and a voltage change detection method that can be performed.

  A first aspect of the present invention is a voltage change detection circuit for detecting a change in gate voltage of an insulated gate transistor, and a voltage exceeding a gate threshold voltage of the insulated gate transistor is applied to a gate of the insulated gate transistor. A drive circuit to be applied, and a current of an amount that causes the gate voltage of the insulated gate transistor to be less than a threshold voltage during a cut-off period in which no voltage is applied from the drive circuit to the gate of the insulated gate transistor for a predetermined time. And a reference voltage change amount serving as a reference value for determining whether or not a gate leak occurs when a current is applied from the current source to the gate of the insulated gate transistor. And a comparison means for comparing and outputting a comparison result.

  According to a second aspect of the present invention, there is provided a blocking period determination circuit that determines whether or not the blocking period is equal to or longer than the predetermined time in the first aspect, wherein the comparison unit includes the blocking period determination circuit. When it is determined that the cutoff period is equal to or longer than the predetermined time, the comparison result is output.

  According to a third aspect of the present invention, in the second aspect, the gate voltage is a waveform in which a sum of a preceding conduction period and a subsequent cutoff period has a certain length, and the cutoff period is The determination circuit is a duty determination circuit that determines whether the interruption period immediately after the conduction period in which the length is detected is equal to or longer than the predetermined time by detecting the length of the conduction period.

  According to a fourth aspect of the present invention, there is provided the power supply switching circuit according to the third aspect, wherein the power source output from the drive circuit to the gate is shut off and the current source is connected to the gate in each of the shut-off periods. Yes.

  According to a fifth aspect of the present invention, in the first aspect, the device includes a voltage determination circuit that determines whether the gate voltage is a voltage for the cutoff period, and the voltage determination circuit includes the gate voltage When it is determined that the voltage is for the cutoff period, the current source is connected to the gate.

  In a sixth aspect of the present invention based on the fifth aspect, the voltage determination circuit periodically determines whether or not the gate voltage is a voltage for the cutoff period.

  According to a seventh aspect of the present invention, in the fifth aspect or the sixth aspect, when the voltage determination circuit determines that the gate voltage is not the voltage for the cutoff period, Without outputting the comparison result, after waiting until the gate voltage becomes the voltage for the cutoff period, it is determined again whether the gate voltage is the voltage for the cutoff period by the voltage determination circuit. judge.

  According to an eighth aspect of the present invention, in any one of the fifth to seventh aspects, the current source is separated from the gate after the comparison unit outputs the comparison result. Connect the power supply output of the drive circuit to the gate

  A ninth aspect of the present invention is a voltage change detection method for detecting a change in the gate voltage of an insulated gate transistor, wherein the voltage is not applied to the gate of the insulated gate transistor during the cutoff period. Whether or not a gate voltage change amount and a gate leak occur when an amount of current that causes the gate voltage of the insulated gate transistor to be less than the threshold voltage is applied for a predetermined time and the current is applied to the gate for the predetermined time. A comparison result is output by comparing a reference voltage change amount as a reference value for determining whether or not.

  According to the first aspect and the ninth aspect, the gate from the current source in a state where the drive power supply output is cut off during a cut-off period in which voltage application from the drive circuit to the gate of the insulated gate transistor is not performed. Current is passed through. Then, the change in the gate voltage changed by charging the gate capacitance is compared with the reference voltage change amount. If the change in the gate voltage is smaller than the reference voltage change amount, it can be determined that a gate leak has occurred.

  As described above, according to the voltage change detection circuit or method, the gate leakage of the insulated gate transistor is performed in the cutoff period with little influence on the element operation, so whether the circuit is operating or not, It can be easily detected without using a measuring device. In addition, since the comparison between the change in the gate voltage and the reference voltage change amount is performed in the cutoff period, the gate leak can be detected even if the insulated gate transistor is held in the cutoff state.

  According to the second aspect, when it is determined that the cutoff period is equal to or longer than the predetermined time, a comparison result between the change in the gate voltage and the reference voltage change amount is output, so that an accurate leak determination can be performed and the comparison process is performed. It is possible to avoid affecting the conduction and cutoff operations of the insulated gate transistor.

  According to the third aspect, since the length of the cutoff period is determined in the conduction period before the current flows from the current source to the gate, the length of the cutoff period is determined by the gate voltage of the conduction period in which gate leakage is less likely to affect. Can be accurately detected. Further, since the length of the cutoff period is detected during the conduction period and the comparison process is performed during the cutoff period, there is a margin in the signal processing timing.

  According to the fourth aspect, current is supplied from the current source to the gate in each cutoff period, and the leak determination is performed in the cutoff period having a length suitable for leak determination, so that the connection control of the current source is simplified. .

  According to the fifth aspect, since the comparison process is performed by detecting that the gate voltage is in the cutoff period, it is possible to detect a gate leak with respect to a gate voltage that has no period or a period that is not constant. it can.

  According to the sixth aspect, since it is periodically determined whether or not the gate voltage is a voltage for the cut-off period, the cut-off period can be easily found and the comparison process can be performed any number of times. .

  According to the seventh aspect, when it is determined that the gate voltage is not the voltage for the cutoff period, the comparison process can be efficiently obtained because the process waits until the cutoff period without performing the comparison process.

  According to the eighth aspect, by disconnecting the current source from the gate after the comparison process, it is possible to prevent the gate voltage from reaching a value corresponding to the threshold voltage during the cutoff period.

The circuit block diagram which shows embodiment of this invention and shows the structure of a failure detection circuit 1 is a circuit block diagram illustrating configurations of a duty determination circuit and a leak determination circuit included in the failure detection circuit of FIG. FIG. 2 is a waveform diagram showing a change in gate voltage when leak detection is performed on an N-channel transistor by the failure detection circuit of FIG. 1, (a) is a waveform diagram when it can be considered that there is no gate leak, (b) Waveform diagram when it can be considered that there is a gate leak It is a wave form diagram which shows execution and non-execution of leak judgment according to the length of the cut-off period of gate voltage, (a) is a wave form chart showing a cut-off period which can perform leak judgment, and (b) is a cut-off which cannot perform leak judgment Waveform diagram showing period FIG. 2 is a waveform diagram showing a change in gate voltage when leak detection is performed on a P-channel transistor by the failure detection circuit of FIG. 1, (a) is a waveform diagram when it can be considered that there is no gate leak, (b) Waveform diagram when it can be considered that there is a gate leak The circuit block diagram which shows other embodiment of this invention and shows the structure of a failure detection circuit 6 is a circuit block diagram illustrating configurations of an on / off determination circuit and a leak determination circuit included in the failure detection circuit of FIG. FIG. 7 is a waveform diagram showing a change in gate voltage when leak detection is performed by the failure detection circuit of FIG. The circuit block diagram which shows a prior art and shows the structure of the failure detection circuit of a semiconductor device

[First Embodiment]
The embodiment of the present invention will be described with reference to FIGS. 1 to 5 as follows.

(Failure detection circuit configuration)
FIG. 1 shows a configuration of a failure detection circuit (voltage change detection circuit) 1 according to the present embodiment.
The failure detection circuit 1 is a circuit that detects a gate leak of the transistor 3 in a system in which the transistor 3 is driven by the drive circuit 2. The failure detection circuit 1 includes a power supply switching circuit 1a, a current source 1b, a duty determination circuit 1c, and a leak determination circuit (comparison means) 1d. The transistor 3 is an insulated gate transistor such as DMOS, LDMOS, or IGBT. The drive circuit 2, the power supply switching circuit 1a, and the current source 1b constitute a gate drive circuit 11.

  For example, the transistor 3 is provided as each arm transistor of the inverter. Here, a case where the transistor 3 is an N-channel type will be described first. The drive circuit 2 applies a drive voltage having a certain period and a change in each pulse width in the high potential period and the low potential period in accordance with a control signal sp1 such as a PWM control signal supplied from a control unit (not shown). It has the function to output to. The voltage in the state output to the gate is called a gate voltage Vg, and the gate voltage Vg has a waveform in which the sum period T of the preceding conduction period Ton and the subsequent cutoff period Toff has a certain length. In this specification, the gate voltage is synonymous with the gate potential.

  The control signal sp1 is input to the power supply switching circuit 1a. The power supply switching circuit 1a outputs the input control signal sp1 to the drive circuit 2 by the internal switch SW1 during a period in which the control signal sp1 instructs to output the high potential gate voltage Vgh. Further, the power supply switching circuit 1a outputs the input control signal sp1 to the current source 1b by the switch SW1 during a period in which the control signal sp1 instructs to output the low-potential gate voltage Vgl.

  When the control signal sp1 instructing to output the high potential gate voltage Vgh is input from the power supply switching circuit 1a via the switch SW1, the drive circuit 2 uses the high potential side drive power supply to generate the gate voltage Vgh. And output from the output transistor for the gate voltage Vgh. The gate voltage Vgh is a voltage exceeding the gate threshold voltage Vth, that is, a voltage for the conduction period Ton of the transistor 3. Thereby, the transistor 3 becomes conductive. Then, when the high potential period of the gate voltage Vg ends, the drive circuit 2 once outputs the gate voltage Vgl from the output transistor for the gate voltage Vgl using the low-potential side drive power supply to shut off the transistor 3. . The gate voltage Vgl is a voltage for the cutoff period Toff of the transistor 3. At this time, the control signal sp1 input to the power supply switching circuit 1a is output to the current source 1b by the switch SW1, and the input of the control signal sp1 to the drive circuit 2 is cut off. When the control signal sp1 is no longer input, the drive circuit 2 sets the outputs of both the output transistor for the gate voltage Vgh and the output transistor for the gate voltage Vgl as high impedance, and outputs the respective drive power supplies on the high potential side and the low potential side. Shut off. As a result, no voltage is applied to the gate during the cutoff period Toff of the transistor 3 after the current source 1b is connected.

  The current source 1b is connected to the gate of the transistor 3 when the control signal sp1 is input from the power supply switching circuit 1a via the switch SW1 during the period of the control signal sp1 instructing to output the low potential gate voltage Vgl. Then, a current is passed so as to change the gate voltage Vg so as to approach the value corresponding to the threshold voltage Vth of the transistor 3. The power supply switching circuit 1a disconnects the current source 1b from the gate when the low potential period of the gate voltage Vg ends. Here, the threshold voltage Vt is a value defined for the gate-source voltage when the transistor 3 is a MOS transistor as a unipolar transistor, and the gate-emitter voltage when the transistor 3 is an IGBT. It is a defined value.

  FIG. 2 shows the configuration concept of the duty determination circuit 1c and the leak determination circuit 1d.

  The duty determination circuit (cut-off period determination circuit) 1 c includes resistors R 1 and R 2, a counter 21, a set reset flip-flop 22, and an AND gate 23.

  The resistor R1 and the resistor R2 are connected in series between the gate of the transistor 3 and GND, and both have large resistance values that limit the current to be sufficiently smaller than the gate current. . A divided voltage V1 of the gate voltage Vg is generated at a connection point between the resistor R1 and the resistor R2, and the divided voltage V1 is stepped down to a logic level range. When it is desired to configure the duty determination circuit 1c so as to be isolated from the gate circuit, information on the gate voltage Vg may be transmitted to the duty determination circuit 1c using a photocoupler or the like.

  The counter 21 counts clock pulses of the input clock signal CK1 using the divided voltage V1 corresponding to the high potential gate voltage Vgh output to the gate of the transistor 3 as an active enable input. The gate voltage Vg becomes Vgh during the conduction period Ton, and becomes a value obtained by adding a voltage increase due to the current of the current source 1b to Vgl during the cutoff period Toff. The voltage V1 has a waveform similar to that of the gate voltage Vg.

  In the conduction period Ton, the counter 21 starts counting clock pulses with the output X = 0 in response to the input of the active voltage V1. When the number of clock pulses counted during the conduction period Ton reaches the first predetermined value, the output X changes to 1. The output X = 1 is held until the enable input of the divided voltage V1 becomes inactive, that is, until the end of the conduction period Ton. The fact that X = 0 at the end of the conduction period Ton means that the length of the cutoff period Toff expressed by the length of the sum period T−the length of the conduction period Ton is equal to or longer than a predetermined time (time Tc described later). Means. Conversely, X = 1 at the end of the conduction period Ton means that the length of the cutoff period Toff represented by the length of the sum period T−the length of the conduction period Ton is less than a predetermined time (time Tc). It means that there is.

  The set-reset flip-flop 22 uses the divided voltage V1 as a set input and the output X of the counter 21 as a reset input. The Q output of the set / reset flip-flop 22 becomes one input of the AND gate 23. The Q output is 1 when the high partial pressure V1 is set and input at the start of the conduction period Ton. When the output X changes from 0 to 1 during the conduction period Ton, the set-reset flip-flop 22 is reset and the Q output becomes 0. In the immediately subsequent cutoff period Toff, since there is no set input due to a new rising edge, the Q output at the end of the conduction period Ton is held.

  The AND gate 23 is a two-input AND gate, and calculates the logical product of the output Q of the set-reset flip-flop 22 and the inverted input of the voltage V1 to obtain an output A. In the conduction period Ton, since the inverting input of the voltage V1 is 1, the output A = 0 regardless of whether the output X = 0 or the output X = 1. In the cutoff period Toff, since the inverting input of the voltage V1 is 0, the output A = 1 only when the output X = 1, that is, only when the count of the counter 21 does not reach the first predetermined value. It becomes.

  The leak determination circuit 1d includes a comparator 31, a reference voltage source 32, a counter 33, and an AND gate 34.

  The comparator 31 compares the gate voltage Vg as an inverting input and the reference voltage Vref1 generated by the reference voltage source 32 as a non-inverting input. The reference voltage Vref1 is set to a value equal to or lower than the value corresponding to the threshold voltage of the transistor 3, and serves as a threshold value for determining whether or not a gate leak has occurred. The comparator 31 outputs an output Z = 0 as a comparison result if the gate voltage Vg is equal to or higher than the reference voltage Vref1, and outputs an output Z = 1 as a comparison result if the gate voltage Vg is smaller than the reference voltage Vref1. .

  The counter 33 uses the output A = 1 of the AND gate 23 as an active enable input and counts clock pulses of the input clock signal CK1. When the output A = 1 is input, the clock pulse counting is started in the state where the output Y = 0. The clock pulse to be counted may be other than the clock signal CK1. The counter 33 outputs Y = 1 when the counted number of clock pulses reaches the second predetermined value. The timing at which the number of clock pulses reaches the second predetermined value refers to a point in time when the time Tc has elapsed from the start of the cutoff period Toff to the end of the cutoff period Toff. The output Y = 1 is held only during the period when the output A is active, that is, until the end of the cutoff period Toff.

The AND gate 34 is a two-input AND gate having the output Y of the counter 33 and the output Z of the comparator 31 as inputs. Since the comparator 31 always compares the gate voltage Vg and the reference voltage Vref1, the AND gate 34 outputs the output W = 1 only when the output Z = 1 when the output Y = 1. . The output W = 1 indicates that the gate voltage Vg did not rise to the reference voltage Vref1 when the gate capacitance was charged by the current source 1b, that is, whether or not a change in the gate voltage Vg caused a gate leak. Is used as a signal indicating that a gate leak has occurred, since the comparison result means that the reference voltage change amount (Vref1−Vgl), which is a reference value for determining the difference, is smaller.
(Determination of gate voltage change and gate leak)
Next, changes in the gate voltage Vg when the failure detection circuit 1 having the above-described configuration determines whether or not there is a gate leak will be described with reference to FIGS.

  FIG. 3A shows a change in the gate voltage Vg when no gate leak exists or when the gate leak is extremely small.

  At time t0, when the drive power supply output of the drive circuit 2 is connected to the gate and the drive circuit 2 outputs the gate voltage Vgh, the conduction period Ton is started. At this time, output X = 0, Q output = 1, and output A = 0. Assume that the duty determination circuit 1c detects the length of the conduction period Ton by counting the clock pulses of the clock signal CK1 by the counter 21, and determines that the length of the cutoff period Toff is equal to or longer than the time Tc. The output X of the counter 21 remains 0 at the end of the conduction period Ton.

  When the transition to the cutoff period Toff occurs at time t1, the current source 1b is connected to the gate instead of the drive power supply of the drive circuit 2. As a result, the gate voltage Vg increases from the initial gate voltage Vgl in proportion to the passage of time. The current of the current source 1b is set to such a magnitude that the gate voltage Vg does not reach a value corresponding to the threshold voltage Vth during the possible length of the cutoff period Toff. That is, the current source 1b applies an amount of current that makes the gate voltage Vg less than the threshold voltage Vth in a predetermined time.

  The leak determination circuit 1d starts counting the clock pulses of the clock signal CK1 by the counter 33 because the output A = 1 at time t1. Since it can be assumed that there is no gate leak, the gate voltage Vg becomes greater than or equal to the reference voltage Vref1 at time t2, which is the time when the counter 33 counts the clock pulses for the time Tc from time t1. As a result, at time t2 when the output Y = 1, the output Z = 0 of the comparator 31 indicating that the gate voltage Vg is equal to or higher than the reference voltage Vref1, that is, it can be regarded that there is no gate leak, is the AND gate 34. Is output as W = 0. When the cutoff period Toff ends at time t3, the drive power supply output of the drive circuit 2 is connected to the gate instead of the current source 1b. The output Y of the counter 33 is reset to 0 when the output A of the enable input becomes inactive at time t3.

  FIG. 3B shows a change in the gate voltage Vg when the gate leak is significantly present. It is assumed that the change in the gate voltage Vg during the conduction period Ton is the same as that in FIG.

  When the transition to the cutoff period Toff occurs at time t1, the current source 1b is connected to the gate instead of the drive power supply output of the drive circuit 2. As a result, the gate voltage Vg rises with time due to the current obtained by subtracting the leakage current from the current supplied from the current source 1b from the initial gate voltage Vgl.

  The leak determination circuit 1d starts counting the clock pulses of the clock signal CK1 by the counter 33 because the output A = 1 at time t1. Since it can be considered that there is a gate leak, the gate voltage Vg becomes lower than the reference voltage Vref1 at time t2, which is the time point when the counter 33 counts the clock pulses for the elapsed time Tc from time t1. Thus, at time t2 when the output Y = 1, the output Z = 1 of the comparator 31 indicating that the gate voltage Vg is smaller than the reference voltage Vref1 is output from the AND gate 34 as the output W = 1. When the cutoff period Toff ends at time t3, the drive power supply of the drive circuit 2 is connected to the gate instead of the current source 1b. The output Y of the counter 33 is reset to 0 when the output A of the enable input becomes inactive at time t3.

  As shown in FIG. 4A, when the duty determination circuit 1c determines that the length of the cutoff period Toff is equal to or longer than the time Tc, the leak determination circuit 1d correctly determines whether or not there is a gate leak at time t2. can do. However, as shown in FIG. 4 (b), when the duty determination circuit 1c determines that the length of the cutoff period Toff is less than the time Tc, the time Tc elapses from the time t1 Since it is not within the period Toff, the leak determination circuit 1d cannot determine the presence or absence of gate leak from the gate voltage Vg on the same basis. In the case shown in FIG. 4B, the duty determination circuit 1c outputs the output X = 1 by the counter 21, thereby forcibly setting the Q output to 0 and holding the output A at 0. . In this way, the counter 33 of the leak determination circuit 1d does not start counting the clock pulses, so the output Y = 0 remains. As a result, the output W can always be 0 regardless of the value of the output Z of the comparator 31, so that the leak determination can be invalidated.

  In the gate voltage Vg in which the length of the conduction period Ton and the length of the cutoff period Toff change in time series even if there is a cycle of the gate voltage Vg in which the leak determination is invalid as shown in FIG. As shown in FIG. 4A, leak determination can be performed in a cycle in which the length of the cutoff period Toff is equal to or longer than the time Tc.

  Next, FIG. 5 shows a change in the gate voltage Vg when the transistor 3 is a P-channel insulated gate transistor. The current source 1b passes a current in a direction in which the gate voltage Vg decreases.

  FIG. 5A shows the change of the gate voltage Vg when no gate leak exists or the gate leak is extremely small, and corresponds to the level inversion of the waveform of FIG. FIG. 5B shows a change in the gate voltage Vg when the gate leak is significantly present, and corresponds to a level inversion of the waveform of FIG. When the transistor 3 is a P-channel type, the failure detection circuit 1 is configured such that the operation logic is inverted with respect to that of FIG. 2, and the principle of leak determination is the same as that of the N-channel type.

  As described above, according to the present embodiment, since the gate leak of the transistor 3 is performed during the cutoff period Toff that has little influence on the element operation, the measurement apparatus is used regardless of whether the circuit is operating or not. And can be easily detected. Further, since the leak determination is performed during the cutoff period Toff, the gate leak can be detected even when the transistor 3 is held in the cutoff state.

  Only when it is determined that the cutoff period Toff is equal to or longer than the time Tc, it is determined whether or not a gate leak has occurred. Therefore, an accurate leak determination can be performed, and the leak determination process can be used to turn on and off the transistor 3. It is possible to avoid affecting the operation.

  Further, since the length of the cutoff period Toff is determined in the conduction period Ton before the current flows from the current source 1b to the gate, the length of the cutoff period Toff is determined by the gate voltage Vg of the conduction period Ton where the gate leakage is less likely to be affected. It can be detected accurately. Further, since the length of the cutoff period Toff is detected in the conduction period Ton and the leak determination is performed in the cutoff period Toff, there is a margin in the signal processing timing.

  In addition, since current is always supplied from the current source 1b to the gate in each cutoff period Toff and leakage determination is performed only in the cutoff period Toff having a length suitable for leak determination, connection control of the current source 1b is simplified. .

  In the above example, the duty determination circuit 1c determines the length of the cutoff period Toff immediately after the conduction period Ton. However, the count of the cutoff period Toff is used as the length of the cutoff period Toff with the start of the cutoff period Toff. As long as the gate voltage Vg does not reach a value corresponding to the threshold voltage, the leak determination may be performed when the time Tc has elapsed. In this case, the leak determination can be performed even if the waveform of the gate voltage Vg does not have a period.

  In the above example, the current source 1b is connected to the gate in the entire cutoff period Toff, but the cutoff voltage Tg is too long and the gate voltage Vg reaches a value corresponding to the threshold voltage Vth. The current source 1b may be disconnected from the gate immediately after the leak determination.

[Second Embodiment]
The embodiment of the present invention will be described with reference to FIGS. In addition, about the member which attached | subjected the same code | symbol as 1st Embodiment, it shall have the same function unless there is particular notice.

(Failure detection circuit configuration)
FIG. 6 shows a configuration of the failure detection circuit 41 according to the present embodiment.
The failure detection circuit 41 is a circuit that detects a gate leak of the transistor 3 in a system in which the transistor 3 is driven by the drive circuit 2. The failure detection circuit (voltage change detection circuit) 41 includes a power supply switching circuit 41a, a current source 1b, an on / off determination circuit 41c, and a leak determination circuit (comparison means) 41d. The drive circuit 2, the power supply switching circuit 41a, and the current source 1b constitute a gate drive circuit 51.

  The drive circuit 2 has a function of outputting a drive voltage as a pulse signal having a high potential period and a low potential period to the gate of the transistor 3 in accordance with a control signal sp2 supplied from a control unit (not shown). Here, the gate voltage Vg is assumed to have no period or a period that is not constant.

  The control signal sp2 is input to the power supply switching circuit 41a. The power supply switching circuit 41a normally outputs an input control signal sp2 to the drive circuit 2 by an internal switch SW1. Further, the power supply switching circuit 1a outputs the input control signal sp2 to the current source 1b by the switch SW1 during the period for determining the gate leak. The switch SW1 is switched according to the output B input from the on / off determination circuit 41c.

  When the control signal sp2 is input from the power supply switching circuit 41a via the switch SW1, the drive circuit 2 generates the gate voltage Vgh using the high-potential side drive power supply and uses the low-potential side drive power supply. A gate voltage Vgl is generated and alternately output to the gate. When the input of the control signal sp2 is lost, the drive circuit 2 sets the outputs of both the output transistor for the gate voltage Vgh and the output transistor for the gate voltage Vgl as high impedance, and outputs the respective drive power supplies on the high potential side and the low potential side. Shut off.

  When the control signal sp2 is input from the power supply switching circuit 41a via the switch SW1, the current source 1b flows a current so as to change the gate voltage in a direction approaching a value corresponding to the threshold voltage Vth of the transistor 3.

  FIG. 7 shows the configuration concept of the on / off determination circuit 41c and the leak determination circuit 41d.

  The on / off determination circuit 41c includes a comparator 61, a reference voltage source 62, a switch SW2, a counter 63, and an AND gate 64.

  The comparator 61 uses the gate voltage Vg as an inverting input and the reference voltage Vref2 generated by the reference voltage source 62 as a non-inverting input. The reference voltage Vref2 is a threshold value for determining whether the gate voltage Vg is a voltage for the conduction period Ton or a voltage for the cutoff period Toff. The value of the reference voltage Vref is set to a value corresponding to the threshold voltage Vth of the transistor 3, for example. If there is a concern that the gate voltage Vg increases by a non-negligible voltage during the cutoff period Toff due to various leaks including the gate leak, the reference voltage Vref2 is set to a value higher than the value corresponding to the threshold voltage Vth. Only a case where the gate voltage Vg is relatively low may be regarded as a voltage for the cutoff period Toff by setting it to a low value. The comparator 61 compares the gate voltage Vg with the reference voltage Vref2, and outputs 1 if the gate voltage Vg is smaller than the reference voltage Vref2, and outputs 0 if the gate voltage Vg is equal to or higher than the reference voltage Vref2.

  The counter 63 counts the clock pulses of the input clock signal CK2, outputs 1 when counting to the third predetermined value, resets the count to the initial value, and repeats the same counting.

  The switch SW2 is provided so as to switch whether one input of an AND gate 64 described later is connected to the output of the comparator 61 or to the GND according to the output of the counter 63. When the output of the counter 63 is 0, the switch SW2 connects one input of the AND gate 64 to GND. When the output of the counter 63 is 1, the switch SW2 connects one input of the AND gate 64 to the output of the comparator 61. The output C of the switch SW2 is input to the leak determination circuit 41d.

  The AND gate 64 is a two-input AND gate, and the one input is connected to the output C of the switch SW2, and the other input is connected to the output of the counter 63. The output B of the AND gate 64 is input to the power supply switching circuit 41a. The output B = 1 is a trigger signal for switching the switch SW2 of the power supply switching circuit 41a so that the control signal sp2 is input to the current source 1b.

  The leak determination circuit 41d includes a set / reset flip-flop 71, a counter 72, a comparator 73, a reference voltage source 74, and a switch SW3.

  The set-reset flip-flop 71 uses the output C output from the on / off determination circuit 41c as a set input and the output of a counter 72 described later as a reset input. The Q output of the set / reset flip-flop 71 is input to the counter 72.

  The counter 72 counts clock pulses of the clock signal CK2 input when the Q output is active, with the Q output of the set-reset flip-flop 71 as an enable input. The output D of the counter 72 serves as a switching instruction signal for a switch SW3, which will be described later, and whether or not the switch SW2 of the power supply switching circuit 41a is switched so that the input destination of the control signal sp2 is changed from the current source 1b to the driving circuit 2. Is a signal for instructing. Note that the counter 72 may count clock pulses other than the clock signal CK2.

  The comparator 73 uses the gate voltage Vg as an inverting input and the reference voltage Vref3 generated by the reference voltage source 73 as a non-inverting input. The reference voltage Vref3 is set to a value equal to or lower than the value corresponding to the threshold voltage of the transistor 3, and serves as a threshold value for determining whether or not a gate leak has occurred. The comparator 73 compares the gate voltage Vg with the reference voltage Vref3, outputs 1 as a comparison result if the gate voltage Vg is smaller than the reference voltage Vref3, and compares the result if the gate voltage Vg is equal to or higher than the reference voltage Vref3. Is output as 0.

The switch SW3 is provided so as to switch according to the output D of the counter 72 whether or not to connect the output of the comparator 73 to an external circuit that receives the leak determination result. When the output D = 0, the switch SW3 does not output the output of the comparator 73 to the external circuit, and sets the GND potential to the output W2. When the output D = 1, the switch SW3 connects the output of the comparator 73 as an output W2 to an external circuit. The output D = 1 is a comparison result that the change in the gate voltage Vg is smaller than the reference voltage change amount (Vref3−Vgl) which is a reference value for determining whether or not the gate leak has occurred, that is, the gate leak is Indicates that it has occurred.
(Determination of gate voltage change and gate leak)
Next, a change in the gate voltage Vg when the failure detection circuit 41 having the above configuration determines whether or not there is a gate leak will be described with reference to FIG.

  The counter 63 of the on / off determination circuit 41c always counts and outputs 1 if the count value reaches the third predetermined value at time t0. As a result, the switch SW2 is closed. The comparator 61 determines that the gate voltage Vg is lower than the reference voltage Vref2, that is, the gate voltage Vg is in the cutoff period Toff because the gate voltage Vg is the low potential gate voltage Vgl for the cutoff period Toff. C = 1 is output. The output C = 1 and the counter output = 1 are input to the AND gate 64, and the AND gate 64 outputs the output B = 1. The output B = 1 is input to the power supply switching circuit 41a, and the switch SW1 of the power supply switching circuit 41a connects the current source 1b to the gate at the same time or with a certain time using the output B = 1 as a trigger signal. The counter 63 is reset to the initial state by its own count output, and starts counting again.

  If the current source 1b is connected to the gate at time t1, the gate voltage Vg increases linearly from the initial value Vgl. In the leak determination circuit 41d, when the output C = 1 is input to the set-reset flip-flop 71 at time t0, the Q output = 1 becomes the active enable input of the counter 72. Thereby, it is assumed that the counter 72 starts counting from time t1, and the counted value reaches the fourth predetermined value at time t2. Since the counter 72 outputs the output D = 1 at time t2, the switch SW3 connects the output of the comparator 73 to an external circuit. The comparator 73 outputs 0 if the gate voltage Vg at time t2 is equal to or higher than the reference voltage Vref3, and outputs 1 if the gate voltage Vg is smaller than the reference voltage Vref3. When the gate voltage Vg is smaller than the reference voltage Vref3, it is determined that there is a gate leak, and the leak determination circuit 41d outputs the output W2 = 1.

  Further, when the output D = 1 at time t2, the set / reset flip-flop 71 is reset. As a result, the enable input of the counter 72 becomes inactive, and the counter 72 is reset. Further, the output D = 1 is input to the power supply switching circuit 41a as a trigger, and the switch SW1 switches the connection so that the current source 1b is disconnected from the gate and the control signal sp2 is input to the drive circuit 2. The switching of the connection may be performed at time t2, or may be performed at time t3 when a certain time has elapsed from time t2, as shown in FIG. By disconnecting the current source 1b in this manner, the gate voltage Vg can be prevented from reaching a value corresponding to the threshold voltage Vth during the cutoff period Toff. After disconnecting the current source 1b, the drive power supply output of the drive circuit 2 is connected to the gate, so that the gate voltage Vg becomes the low potential gate voltage Vgl.

  The external circuit uses the received output W2 = 1 for processing for the occurrence of the gate leak. If necessary, a configuration for latching the output W2 = 1 for a predetermined time may be added.

  The counter 63 of the voltage determination circuit 41c repeatedly counts up to the third predetermined value. When the gate voltage Vg is the voltage for the conduction period Ton at time t0 (1), the comparator 61 outputs the output C = 0 is output. As a result, since the output B = 0, the switch SW1 of the power supply switching circuit 41a does not connect the current source 1b to the gate. In the leak determination circuit 41d, the Q output of the set / reset flip-flop 71 remains 0, and the counter 72 does not start counting. As a result, the output W2 remains at the GND potential, that is, the leak determination is not performed.

  Thereafter, it is assumed that the counter 63 of the voltage determination circuit 41c repeats counting and counts the third predetermined value at time t0 (2). At this time, since the gate voltage Vg = Vgl, the leak determination is performed as described above.

  As described above, when the on / off determination circuit 41c determines that the gate voltage Vg is not the voltage for the cutoff period Toff, the gate voltage Vg is not determined by the leak determination circuit 41d without determining the gate leak. After waiting until the voltage for Toff is reached, it is determined again whether the gate voltage Vg is a voltage for the cutoff period Toff.

  Next, FIG. 8B shows a change in the gate voltage Vg when the transistor 3 is a P-channel insulated gate transistor. The current source 1b passes a current in a direction in which the gate voltage Vg decreases. The waveform of the gate voltage Vg in FIG. 8B corresponds to the level inversion of the waveform in FIG. When the transistor 3 is a P-channel type, the failure detection circuit 41 is configured such that the operation logic is inverted with respect to that of FIG. 7, and the principle of leak determination is the same as that of the N-channel type.

  As described above, according to the present embodiment, the leakage determination is performed by detecting that the gate voltage Vg is in the cutoff period Toff without detecting the length of the cutoff period Toff. This is particularly suitable for leak determination at the gate voltage Vg having a waveform in which the current flowing time is shorter than the length of an arbitrary cutoff period Toff.

  Further, since it is periodically determined whether or not the gate voltage Vg is a voltage for the cutoff period Toff, the cutoff period Toff can be easily found, and the leak determination can be performed an arbitrary number of times.

  Further, when it is determined that the gate voltage Vg is not the voltage for the cutoff period Toff, the standby state is waited until the cutoff period Toff is reached without performing the leak determination, so that the leak determination result can be obtained efficiently.

  Note that the failure detection circuit of each of the embodiments described above can also be applied to detection of gate leakage for an insulated gate transistor (for example, a MOS transistor) other than the power semiconductor.

  The present invention is particularly effective for in-vehicle circuits and power circuits in which power elements are used.

1, 41 Failure judgment circuit (voltage change detection circuit)
1a, 41a Power supply switching circuit 1b Current source 1c Duty determination circuit (cut-off period determination circuit)
1d, 41d Leak determination circuit (comparison means)
2 Drive circuit 41c ON / OFF determination circuit (voltage determination circuit)
3 Transistors (insulated gate type transistors)
Ton conduction period Toff cut-off period T sum period Vg gate voltage Vgl gate voltage (voltage for cut-off period)
Vth threshold voltage Tc time (predetermined time)

Claims (9)

A voltage change detection circuit for detecting a change in gate voltage of an insulated gate transistor,
A drive circuit for applying a voltage exceeding a gate threshold voltage of the insulated gate transistor to the gate of the insulated gate transistor;
A current source for applying, for a predetermined time, an amount of current that makes the gate voltage of the insulated gate transistor less than a threshold voltage during a shut-off period in which no voltage is applied from the drive circuit to the gate of the insulated gate transistor; ,
A comparison result comparing a gate voltage change amount when a current is applied from the current source to the gate of the insulated gate transistor and a reference voltage change amount serving as a reference value for determining whether or not a gate leak occurs. A voltage change detection circuit comprising: a comparison means for outputting A cutoff period determination circuit for determining whether the cutoff period is equal to or longer than the predetermined time;
The voltage change detection circuit according to claim 1, wherein the comparison unit outputs the comparison result when the cutoff period determination circuit determines that the cutoff period is equal to or longer than the predetermined time. The gate voltage is a waveform in which the sum of the preceding conduction period and the subsequent interruption period has a certain length,
The interruption period determination circuit is a duty determination circuit that determines whether the interruption period immediately after the conduction period in which the length is detected is longer than the predetermined time by detecting the length of the conduction period. The voltage change detection circuit according to claim 2.   4. The voltage change detection circuit according to claim 3, further comprising a power supply switching circuit that cuts off a power supply output from the drive circuit to the gate during each shutoff period and connects the current source to the gate. . A voltage determination circuit for determining whether the gate voltage is a voltage for the cutoff period;
2. The voltage change detection circuit according to claim 1, wherein when the voltage determination circuit determines that the gate voltage is a voltage for the cutoff period, the current source is connected to the gate.   6. The voltage change detection circuit according to claim 5, wherein the voltage determination circuit periodically determines whether or not the gate voltage is a voltage for the cutoff period.   When the voltage determination circuit determines that the gate voltage is not the voltage for the cutoff period, the comparison unit does not output the comparison result until the gate voltage becomes the voltage for the cutoff period. 7. The voltage change detection circuit according to claim 5, wherein after waiting, the voltage determination circuit determines again whether or not the gate voltage is a voltage for the cutoff period. 8.   8. The device according to claim 5, wherein after the comparison unit outputs the comparison result, the current source is disconnected from the gate and a power supply output of the drive circuit is connected to the gate. The voltage change detection circuit described. A voltage change detection method for detecting a change in gate voltage of an insulated gate transistor,
Applying an amount of current for a predetermined time so that the gate voltage of the insulated gate transistor is less than a threshold voltage during a shut-off period in which voltage application to the gate of the insulated gate transistor is not performed,
A voltage for comparing a gate voltage change amount when the current is applied to the gate for the predetermined time and a reference voltage change amount serving as a reference value for determining whether or not a gate leak occurs and outputting a comparison result Change detection method.

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