JP2007139955A - Electrooptical apparatus and electronic apparatus with the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform an inspection by which satisfactory measurement accuracy can be obtained without the need for being brought into contact with a probe from the outside in an electrooptical apparatus, such as a liquid crystal apparatus. <P>SOLUTION: The electrooptical apparatus includes a plurality of scanning lines and a plurality of signal lines, and a plurality of pixel sections, on a substrate. A plurality of circuits for amplification which: include a plurality of transistors, respectively; are provided correspondingly to each set of the predetermined number of signal lines; to which a first potential signal is supplied through one signal line among the predetermined number of the signal lines, and a second potential signal is supplied through another signal line; and which output a low potential signal or high potential signal according to the result obtained by comparing the potential of the first potential signal with the second potential signal. Further, the apparatus includes a body-contact means which is arranged on the extension part of an active layer in at least one transistor among the plurality of the transistors, and which performs a body-contact to the one transistor. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a technical field of an electro-optical device such as a liquid crystal device, and an electronic apparatus such as a liquid crystal projector including the electro-optical device.

  Conventionally, display devices such as liquid crystal devices are widely used in devices such as mobile phones and projectors. 2. Description of the Related Art A liquid crystal display device using a TFT (Thin Film Transistor) or the like is configured by adhering a TFT substrate and a counter substrate and sealing liquid crystal between the substrates. In general, an inspection of whether a manufactured liquid crystal device operates normally is performed on a finished product. For example, a predetermined image signal is input to the liquid crystal device as display data, and is projected, displayed, or the like to check whether the data is correctly displayed or whether there is a defective pixel.

  However, the method of inspecting a finished product is not preferable from the viewpoint of manufacturing process management. The reason is that a defective product is found after the substrate manufacturing process, so that the detection of the defective product is delayed.

  For this reason, the time until failure detection for process management is fed back becomes longer. As a result, the yield reduction period becomes longer and the manufacturing cost increases. Also, in the case of a prototype, since the period of time from the evaluation of the prototype to the feedback to the design is prolonged, the development period is prolonged and the development cost is increased. Furthermore, after the product is completed, so-called repair, that is, repair of a defective portion is difficult.

  Therefore, it is desired to find a defect, particularly a defective pixel of a display device, in the manufacturing process of the substrate.

  As one of such inspection methods, a technique for inspecting a liquid crystal display device by bringing a test probe into contact with an electrode pad of the liquid crystal display device and supplying a predetermined current has been proposed (for example, Patent Document 1). Similarly, a technique has been proposed in which a predetermined voltage is applied to each pixel of the TFT based on the capacitor capacitance characteristics of the pixel, and the function of the TFT is inspected based on the waveforms of the discharge current and the discharge voltage (for example, Patent Documents). 2).

  In addition, a technique for inspecting the operation of each pixel electrode by detecting the amount of change in the potential of the pixel electrode using an inspection counter electrode corresponding to the pixel electrode of the TFT substrate has been proposed (for example, patents). Reference 3).

Japanese Patent Laid-Open No. 5-341302 JP-A-7-333278 JP-A-10-104563

  However, in the case of the techniques described in Patent Document 1 and Patent Document 3 described above, in the inspection apparatus, mechanical position accuracy is required to bring a predetermined probe or the like into contact with or close to an electrode pad or the like from the outside of the substrate. . As a result, there is a technical problem that the inspection time becomes long in order to ensure mechanical alignment accuracy. Furthermore, in the case of a high-definition liquid crystal display device, a thin probe or the like must be brought into contact with many electrode pads by performing mechanical control, and these methods may not be applied.

  Further, in the method described in Patent Document 2 described above, various capacitance components between the liquid crystal display device and the measuring device, for example, the capacitance in the data line, the video line, the electrode pad terminal, etc. are affected, so that the capacitance of the pixel itself is relatively If it is small, there is a technical problem that sufficient measurement accuracy cannot be obtained.

  The present invention has been made in view of the above-described conventional problems, and does not require contact with an external probe and the like, and an electro-optical device capable of realizing inspection with sufficient measurement accuracy and the electric An object is to provide an electronic device including an optical device.

  In order to solve the above problems, an electro-optical device according to an aspect of the invention corresponds to a plurality of scanning lines and a plurality of signal lines intersecting each other on the substrate, and the intersection of the plurality of scanning lines and the plurality of signal lines. Each of the plurality of pixel portions and the plurality of transistors, and provided corresponding to each of a predetermined number of signal lines among the plurality of signal lines, and the predetermined number of signals. A first potential signal is supplied through one signal line of the lines, and a second potential signal as a reference potential is supplied through another signal line, and the potential of the first potential signal and the second potential are supplied. Compared with the potential of the signal, (i) when the potential of the first potential signal is lower than the potential of the second potential signal, a low potential signal having a potential lower than the potential of the first potential signal, (Ii) The potential of the first potential signal is the second potential signal. A plurality of amplifying circuits for outputting a high potential signal having a potential higher than the potential of the first potential signal, and an extension portion of an active layer in at least one of the plurality of transistors. And a body contact means for taking a body contact in the one transistor.

  According to the electro-optical device of the present invention, during the operation, an image signal is supplied to each pixel unit via the data line, for example, by an X driver circuit. At the same time, a scanning signal is supplied to each pixel portion via the scanning line by the Y driver circuit. For example, a thin film transistor for pixel switching provided for each pixel portion has a gate connected to a scanning line, and selectively supplies an image signal to a pixel electrode in accordance with the scanning signal. Accordingly, for example, by driving an electro-optical material such as liquid crystal sandwiched between the pixel electrode and the counter electrode in each pixel portion, active matrix driving is possible. At this time, the storage capacitor improves the potential holding characteristic in the pixel portion, and the display can have high contrast.

  In particular, the present invention includes an amplification circuit. For example, the amplifying circuit transmits a high-potential signal or a low-potential signal through, for example, one signal line among a predetermined number of signal lines constituting a set at the time of inspection performed prior to the operation of the electro-optical device. Is output to determination means for determining whether or not the quality is good. Here, the “set of a predetermined number of signal lines” is typically a set made up of two signal lines, and the plurality of signal lines are made up of two signal lines. Configure a set of signal lines. Such inspection is preferably performed before the electro-optical device is bonded to the pair of substrates, for example, when a substrate called an element array substrate, an element substrate, or a TFT array substrate is completed. Is done.

  More specifically, at the time of this inspection, for example, when the first potential signal output from the pixel portion has a slightly higher potential than the second potential signal as the reference potential, the potential of the second potential signal The amplifying circuit has a higher potential compared to the first potential signal so that the high potential of the first potential signal with respect to is not obscured by noise applied to the first signal line and the second signal line. For example, the potential signal is output to, for example, the determination unit via one signal line. When the first potential signal has a slightly lower potential than the second potential signal, the first signal line and the second signal line indicate that the potential of the first potential signal is lower than the potential of the second potential signal. In order not to be obscured by the applied noise, the amplifying circuit lowers the potential of the first potential signal, and then outputs a low potential signal whose potential is kept low, for example, to a determination means via one signal line, for example. To do. Here, the “first potential signal” is a signal reflecting the quality of the pixel portion, and more specifically, for example, is a signal output according to the quality of the pixel portion. For example, an inspection signal is supplied to the pixel portion in advance prior to the inspection, and a signal having a potential that varies from the potential of the inspection signal according to the quality of the pixel portion is output as the first potential signal. “Possibility of the pixel portion” means whether or not the pixel portion has a defect, and the level relationship between the potentials of the first potential signal and the second potential signal varies depending on the defect occurring in the pixel portion. . The “second potential signal” has a reference potential that serves as a reference for increasing or decreasing the potential of the first potential signal.

  The determination unit is, for example, an external circuit provided outside the substrate included in the electro-optical device of the present invention. For example, the potential of the inspection signal that is supplied in advance to the pixel portion and is the basis of the first potential signal is the first. The potential of the high potential signal or the potential of the low potential signal is higher than the information of whether the potential is higher or lower than the potential of the two potential signal and the potential of the signal output from the amplification circuit based on the second potential signal. Whether the pixel portion is good or bad is determined based on voltage logic that compares the low or low information.

  According to such a determination method, when the potential of the inspection signal that is the basis of the first potential signal is higher than the potential of the second potential signal, if a high potential signal is output from the amplifier circuit, the signal line becomes one signal line. It is determined that no defect has occurred in the electrically connected pixel portion, that is, the pixel portion to which the inspection signal that is the basis of the first potential signal is supplied. On the other hand, if the low potential signal is output from the amplification circuit when the potential of the inspection signal that is the basis of the first potential signal is higher than the potential of the second potential signal, the pixel portion that is electrically connected to one signal line It is determined that some sort of malfunction has occurred. When the potential of the inspection signal that is the source of the first potential signal is lower than the potential of the second potential signal, if a low potential signal is output from the amplifier circuit, the pixel portion electrically connected to one signal line It means that no defect has occurred. If the high potential signal is output from the amplification circuit when the potential of the inspection signal that is the basis of the first potential signal is lower than the potential of the second potential signal, that is, the pixel portion that is electrically connected to one signal line, It is determined that some defect has occurred in the pixel portion to which the inspection signal that is the basis of the first potential signal is supplied.

  Further, the present invention particularly includes body contact means. The body contact means is provided in the extending portion of the active layer in at least one transistor among the plurality of transistors constituting the amplifier circuit, and takes a body contact in the one transistor. The body contact means includes, for example, a contact portion that contacts the extension portion of the active layer of one transistor and a wiring portion that is electrically connected to the contact portion. “Taking body contact” or “taking body contact” means removing excess carriers accumulated in an active layer in which a channel in a transistor is formed. The “body contact means” according to the present invention refers to various parts such as a part of a semiconductor film, a part of a conductive film, an electrode, a wiring part, a connection part or the like for making such a body contact. Or parts. For this reason, the “body contact means” is a “potential fixing means” or “potential fixing electrode” that fixes the potential of the active layer constituting the transistor, or “carrier removal means that removes excess carriers in the active layer of the transistor. Or “carrier-removing electrode” or the like. By such body contact means, the potential in the active layer of one transistor is fixed to a predetermined potential. As the predetermined potential, for example, when one transistor is an Nch type transistor, a potential lower than the source potential and the drain potential is set. On the other hand, when one transistor is a Pch type transistor, the source potential is set. A potential higher than the potential and the drain potential is set. For this reason, when one transistor is switched from the on state to the off state, excess carriers (that is, holes or electrons) accumulated in the active layer where the channel is formed are removed by the body contact means. Can be removed. That is, it is possible to prevent the potential of the first potential signal and the potential of the second potential signal from changing due to electrical noise during switching, for example. Therefore, when the potential of the first potential signal and the potential of the second potential signal change, the level relationship between the potential of the first potential signal and the potential of the second potential signal does not generate electrical noise. Can prevent the opposite relationship. Thereby, it is possible to prevent the amplification circuit from malfunctioning and to obtain an accurate comparison result.

  In one aspect of the electro-optical device according to the aspect of the invention, the body contact unit includes a contact portion that contacts the extending portion and a wiring portion that is electrically connected to the contact portion.

  According to this aspect, when one transistor is switched from the on-state to the off-state (that is, at the time of switching), the excess carriers accumulated in the active layer have the contact portion that contacts the extension portion. Through the wiring section. Therefore, generation of electrical noise during switching in one transistor can be surely reduced.

  In another aspect of the electro-optical device of the present invention, the plurality of amplification circuits are provided one for each pair of the two signal lines, and electrical connection between the two signal lines is performed. The body contact means has at least the body contact of the first transistor as the one transistor.

  According to this aspect, the body contact in the first transistor constituting the equalizing circuit is taken by the body contact means. Therefore, the electrical potential that may occur when the first transistor is switched from the on state to the off state (ie, during switching) in order to control the electrical connection between the two signal lines that constitute the set. Generation of noise can be reduced. Therefore, the amplification circuit can be prevented from malfunctioning, and an accurate comparison result can be obtained. In particular, the equalizing circuit electrically connects (that is, shorts or shorts) two signal lines before the first potential signal is output from the pixel portion in the inspection, and connects the two signal lines. Since it is only necessary to have the function of setting the same potential to each other, the first transistor constituting the equalize circuit is typically formed relatively small. For this reason, electrical noise due to switching is likely to occur in the first transistor. Therefore, taking at least the body contact in the first transistor ensures that the amplifying circuit malfunctions as compared with the case in which the body contact in other relatively large transistors constituting the amplifying circuit is taken. It can be prevented efficiently. For this reason, little or no increase in the substrate size by providing the body contact means is required.

  In another aspect of the electro-optical device according to the aspect of the invention, the plurality of amplification circuits each include a differential amplification circuit including a plurality of second transistors, and the body contact unit is configured as the one transistor. And at least a body contact in the second transistor.

  According to this aspect, the body contact is made in the second transistor constituting the differential amplifier circuit by the body contact means. Therefore, generation of electrical noise that can occur when the second transistor is switched on and off can be reduced. Therefore, the differential amplifier circuit can be prevented from malfunctioning, and an accurate comparison result can be obtained. In particular, in the differential amplifier circuit, the second transistor is switched when the first potential signal and the second potential signal are compared. Therefore, electrical noise caused by switching in the second transistor has a greater effect on the comparison result than other transistors that are switched on and off before and after the comparison of the first potential signal and the second potential signal. give. Therefore, at least taking the body contact in the second transistor reliably or efficiently prevents the amplification circuit from malfunctioning as compared to taking the body contact in the other transistors constituting the amplification circuit. can do.

  In another aspect of the electro-optical device according to the aspect of the invention, each of the plurality of amplification circuits may include a drive circuit including at least one third transistor for supplying power for driving the plurality of amplification circuits. The body contact means takes a body contact in at least the third transistor as the one transistor.

  According to this aspect, the body contact in the third transistor constituting the drive circuit is taken by the body contact means. Therefore, generation of electrical noise that may occur when the third transistor is switched on and off can be reduced. Therefore, the amplification circuit can be prevented from malfunctioning, and an accurate comparison result can be obtained. In particular, in the driver circuit, the third transistor is switched when the first potential signal and the second potential signal are compared in the amplifier circuit. Therefore, electrical noise caused by switching in the third transistor has a large influence on the comparison result compared to other transistors that are switched on and off before and after the comparison of the first potential signal and the second potential signal. give. Therefore, taking a body contact in at least the third transistor reliably or efficiently prevents malfunctioning of the amplifying circuit compared to taking a body contact in other transistors constituting the amplifying circuit. can do.

  An electronic apparatus of the present invention comprises the above-described electro-optical device of the present invention in order to solve the above problems.

  According to the electronic apparatus of the present invention, since it includes the electro-optical device of the present invention described above, a projection display device, a mobile phone, an electronic notebook, a word processor, a viewfinder type, or a monitor capable of high-quality display. Various electronic devices such as a direct-view video tape recorder, a workstation, a videophone, a POS terminal, and a touch panel can be realized. Further, as the electronic apparatus of the present invention, for example, an electrophoretic device such as electronic paper can be realized.

  The operation and other advantages of the present invention will become apparent from the best mode for carrying out the invention described below.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, a driving circuit built-in type TFT active matrix driving type liquid crystal device, which is an example of the electro-optical device of the present invention, is taken as an example.
<First Embodiment>
The liquid crystal device according to the first embodiment will be described with reference to FIGS.

  First, the overall configuration of the liquid crystal device according to the present embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view showing the overall configuration of the liquid crystal device according to the present embodiment, and FIG. 2 is a cross-sectional view taken along the line HH ′ of FIG.

  1 and 2, in the liquid crystal device according to the present embodiment, a TFT array substrate 10 and a counter substrate 20 are arranged to face each other. A liquid crystal layer 50 is sealed between the TFT array substrate 10 and the counter substrate 20, and the TFT array substrate 10 and the counter substrate 20 are provided with a sealing material 52 provided in a seal region positioned around the image display region 10a. Are bonded to each other.

  In FIG. 1, a light-shielding frame light-shielding film 53 that defines the frame area of the image display region 10a is provided on the counter substrate 20 side in parallel with the inside of the seal region where the sealing material 52 is disposed. An X driver circuit 101 and an external circuit connection terminal 102 are provided along one side of the TFT array substrate 10 in a region located outside the seal region where the seal material 52 is disposed in the peripheral region. The sampling circuit 110 is provided so as to be covered with the frame light shielding film 53 on the inner side of the seal region along the one side. The Y driver circuit 104 is provided so as to be covered with the frame light shielding film 53 inside the seal region along two sides adjacent to the one side. On the TFT array substrate 10, vertical conduction terminals 106 for connecting the two substrates with the vertical conduction material 107 are arranged in regions facing the four corner portions of the counter substrate 20. Thus, electrical conduction can be established between the TFT array substrate 10 and the counter substrate 20.

  On the TFT array substrate 10, lead wirings 90 are formed for electrically connecting the external connection terminals 102 to the X driver circuit 101, the Y driver circuit 104, the vertical conduction terminal 106, and the like.

  In FIG. 2, on the TFT array substrate 10, a laminated structure in which pixel switching TFTs as drive elements, wiring lines such as scanning lines and data lines are formed is formed. In the image display area 10a, a pixel electrode 9a is provided in an upper layer of wiring such as a pixel switching TFT, a scanning line, and a data line. An alignment film is formed on the pixel electrode 9a. On the other hand, on the counter substrate 20, in addition to the counter electrode 210, a lattice-shaped or striped light-shielding film 230 and an alignment film are formed on the uppermost layer portion. The liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several types of nematic liquid crystals are mixed, and takes a predetermined alignment state between the pair of alignment films.

  Although not shown here, on the TFT array substrate 10, in addition to the X driver circuit 101 and the Y driver circuit 104, as will be described later, a differential constituting an example of an “amplifying circuit” according to the present invention. An amplifier circuit, an equalize circuit, a precharge circuit, a transmission gate, and the like are formed.

  Next, the circuit configuration of the liquid crystal device according to the present embodiment will be described with reference to FIGS. FIG. 3 is a block diagram showing the main circuit configuration of the liquid crystal device according to this embodiment. FIG. 4 is a circuit diagram showing an electrical configuration of the pixel portion. FIG. 5 is a circuit diagram showing an electrical configuration of the pull-down circuit. FIG. 6 is a conceptual diagram showing a state of a pixel portion to which a signal is supplied in advance at the time of inspection. FIG. 7 is a circuit diagram showing an electrical configuration of the pull-up circuit. FIG. 8 is a circuit diagram showing an electrical configuration of the differential amplifier circuit. In the following, for the sake of simplicity, the odd number (ie, 1) is assumed along the direction in which the scanning line Gj (j = 1, 2,..., N; an integer of 2 or more) extends as viewed from the left side in FIG. Signal lines Soi (i = 1, 2,..., M; m is a natural number of 2 or more) arranged in the third, third, fifth,. The signal lines Sei (i = 1, 2,..., M; m is a natural number) arranged at even-numbered (0th, second, fourth,...) The description will be made on the assumption that the “other signal line” is selected.

  In FIG. 3, the liquid crystal device of this embodiment includes a Y driver circuit 104, an X driver circuit 101, a sampling circuit 110, and a pixel unit 70 on the TFT array substrate 10.

  The Y driver circuit 104 sequentially supplies switching signals for each scanning line Gj when the pixel unit 70 is inspected. Here, the switching signal is a signal different from the scanning signal for image display supplied to the pixel unit 70 when displaying an image, and an inspection signal described later supplied in advance to the pixel unit 70 is used as the pixel signal. This is a signal for switching the switching element included in the pixel unit 70 to the on state.

  The X driver circuit 101 supplies a sampling signal to the sampling switch 111 that constitutes the sampling circuit 110, and switches the sampling switch 111 to an on state. Here, the “sampling signal” is different from a signal supplied from the X driver circuit 101 to the sampling circuit 110 when displaying an image, and is a high potential signal or a low potential output from the differential amplifier circuit 15 described later. It is a signal for individually outputting a signal to an external test apparatus to be described later for each of the signal lines Soi and Sei.

  When inspecting the pixel unit 70, the sampling circuit 110 outputs the first and second potential signals in correspondence with the signal lines Soi and Sei to which the pixel unit 70 to be inspected is electrically connected, A high potential signal or a low potential signal is output to an external test apparatus via the image signal supply lines 112o and 112e.

  The pixel unit 70 is provided in the image display region 10a corresponding to the intersection of the signal lines Soi and Sei and the scanning line Gj.

  As shown in FIG. 4, the pixel unit 70 includes a TFT 71, a liquid crystal element 72, and a storage capacitor 73.

  The TFT 71 has a source electrically connected to the signal line Soi or Sei, and a gate electrically connected to the scanning line Gj. The TFT 71 is turned on and off by a switching signal supplied from the Y driver circuit 104. The pixel unit 70 outputs the first potential signal to the signal line Soi and outputs the second potential signal to the signal line Sei. The liquid crystal element 72 has a liquid crystal injected between the TFT array substrate 10 and a counter substrate disposed so as to correspond to the TFT array substrate 10 and a pair of electrodes that sandwich the liquid crystal. The storage capacitor 73 temporarily holds an image signal supplied to the pixel unit 70 when image display is performed, and enables active matrix driving of the plurality of pixel units 70.

  Referring again to FIG. 3, the liquid crystal device of this embodiment further includes an inspection circuit 4 on the TFT array substrate 10.

  The inspection circuit 4 includes a plurality of differential amplifier circuits 15, a first drive signal supply circuit 21, a second drive signal supply circuit 22, an equalize circuit 23, a voltage, which constitute an example of “a plurality of amplification circuits” of the present invention. An application wiring 24, a precharge circuit 25, a connection circuit 26, a transmission gate 6, a plurality of signal lines Soi, and a plurality of signal lines Sei are provided.

  A plurality of signal lines Soi and Sei extend from the image display region 10 a to the differential amplifier circuit 15, and are electrically connected to connection points so and se of the differential amplifier circuit 15, respectively. The signal lines Soi and Sei intersect the plurality of scanning lines Gj (j = 1, 2,..., N; n is an integer of 2 or more) provided in the image display area 10a. It extends in the image display area. The pixel portion 70 provided in the image display region 10a is arranged in accordance with the intersection of the signal lines Soi and Sei and the plurality of scanning lines Gj, and is electrically connected to the signal lines Soi and Sei.

  The connection circuit 26 includes a test signal supply line 45 electrically connected to the test apparatus via the test apparatus connection gate terminal 45s, and a pull-down circuit 35. The test signal supply line 45 supplies a series of test signals supplied from the test apparatus to the transmission gate 6 when the pixel unit 70 is inspected. The pull-down circuit 35 stabilizes the potential of the test signal supply line 45 so that the test signal supplied to the transmission gate 6 via the test signal supply line 45 does not fluctuate.

  As shown in FIG. 5, the pull-down circuit 35 includes a TFT 135 having a gate electrically connected to the power supply VDD, a grounded source, and a drain electrically connected to the test signal supply line 45. This reduces the fluctuation of the potential of the test signal supply line 45 when the test signal is supplied. Note that the pull-down circuits 32, 33 and 34 also have the same circuit configuration as the pull-down circuit 35.

  In FIG. 3 again, the transmission gate 6 is provided in the middle of each of the signal lines Soi and Sei. The transmission gate 6 is provided on the side close to the differential amplifier circuit 15 when viewed from the pixel portion 70, and includes a plurality of TFTs 14 electrically connected in the middle of each of the signal lines Soi and Sei. The plurality of TFTs 14 are collectively switched on according to a test signal supplied from the test apparatus via the test signal supply line 45 when the pixel unit 70 is inspected. As a result, it is possible to secure supply paths for the first and second potential signals supplied to the differential amplifier circuit 15 via the signal lines Soi and Sei, respectively, which are provided in the pixel portion 70 described above with reference to FIG. If the TFT 71 is switched to the ON state, the first potential signal and the second potential signal can be collectively supplied from each pixel unit 70 to each differential amplifier circuit 15 via each of the signal lines Soi and Sei.

  Here, at the time of inspection, an inspection signal and a reference signal having a predetermined potential are supplied to the plurality of pixel units 70 in advance. In the present embodiment, as shown in FIG. 6, the pixel portion 70 provided corresponding to the signal line Soi has a potential higher than an intermediate potential (indicated as “M” in FIG. 6) as a reference potential. (Hereinafter referred to as “HIGH potential” as appropriate; indicated as “H” in FIG. 6), an intermediate potential reference signal is supplied to the pixel portion 70 provided corresponding to the signal line Sei. Is done. In the present embodiment, the intermediate potential is half of the power supply voltage Vdd of the power supply VDD, that is, Vdd / 2. Therefore, in the image display area 10a, the columns of the pixel portions 70 supplied with the intermediate potential signal and the columns of the pixel portions 70 supplied with the HIGH potential signal are alternately arranged.

  The first potential signal is a signal obtained by reading the inspection signal that has been supplied to the pixel unit 70 in advance from the pixel unit 70, and is different from the potential of the inspection signal, that is, the HIGH potential, depending on the malfunction that has occurred in the pixel unit 70. Output with potential. The second potential signal is a signal in which the reference signal previously supplied to the pixel unit 70 is read from the pixel unit 70, and is supplied to the differential amplifier circuit 15 through the signal line Sei simultaneously with the first potential signal. The The second potential signal, that is, the potential of the reference signal is output as an intermediate potential. The intermediate potential is a reference potential to be compared when the differential amplifier circuit 15 determines the level of the potential of the first potential signal. The first potential signal may be a signal supplied to all or a part of the plurality of pixel units 70, and the second potential signal may be a signal supplied from the outside. In this case, since the second signal as the reference signal can be stably supplied from the outside, it is possible to more reliably determine whether the pixel unit 70 is good or bad.

  In FIG. 3 again, the precharge circuit 25 includes a precharge signal supply line 44 electrically connected to the gates of the TFTs 12a and 12b, and a pull-down circuit 34 electrically connected to the precharge signal supply line 44. ing. The precharge signal supply line 44 supplies a precharge signal supplied from the outside via the precharge terminal 44s to the gates of the TFTs 12a and 12b in order to switch the TFTs 12a and 12b on and off. The pull-down circuit 34 reduces fluctuations in the potential of the precharge signal supply line 44.

  The voltage application wiring 24 is electrically connected to the source of the TFT 12a and the drain of the 12b, and applies a precharge voltage to the TFTs 12a and 12b. The precharge voltage is set to an intermediate potential in advance and is supplied to the TFTs 12a and 12b. The precharge voltage is supplied to the TFTs 12a and 12b before the first and second potential signals are supplied to the differential amplifier circuit 15 through the signal lines Soi and Sei, respectively. More specifically, the drain of the TFT 12a and the source of the TFT 12b are electrically connected to the signal lines Soi and Sei, respectively, and after the precharge signal is supplied to the gates of the TFTs 12a and 12b, the precharge voltage is changed to the TFT 12a. And 12b between the respective sources and drains. As a result, current flows between the sources and drains of the TFTs 12a and 12b so as to reduce the potential difference between the signal lines Soi and Sei, and the potentials of the signal lines Soi and Sei become equal to the intermediate potential.

  The equalize circuit 23 includes TFTs 11n and 11p, an equalize signal supply line 43, an inverter 23i, and a pull-down circuit 33. The equalize signal supply line 43 is branched into two equalize signal supply lines 43a and 43b. The equalize signal supply line 43a is electrically extended from the equalize signal supply line 43 as it is, whereas an inverter 43i is provided between the equalize signal supply lines 43b and 43. The source and drain of the TFT 11n are electrically connected to the signal lines Sei and Soi, respectively, and the gate of the TFT 11n is electrically connected to the equalize signal supply line 43a. On the other hand, the source and drain of the TFT 11p are also electrically connected to the signal lines Sei and Soi, respectively, similarly to the TFT 11n, and the gate of the TFT 11p is electrically connected to the equalize signal supply line 43b. An equalize signal for switching on and off the TFTs 11n and 11p is supplied to the gates of the TFTs 11n and 11p via the equalize signal supply line 43, respectively. That is, the equalize signal is supplied to the gate of the TFT 11n via the equalize signal supply line 43a, and the equalize signal having the opposite polarity to the equalize signal supplied to the equalize signal supply line 43 is supplied to the gate of the TFT 11p. It is supplied via a supply line 43b. Since the equalize circuit 23 includes such TFTs 11n and 11p, even if the potential of the equalize signal supply line 43 fluctuates, the electrical connection between the signal lines Sei and Soi is reliably switched according to the equalize signal. be able to. Further, the pull-down circuit 33 reduces the fluctuation of the potential of the equalize signal supply line 43. The TFTs 11n and 11p are electrically connected to body contact wires 61 and 62 as an example of “body contact means” according to the present invention, as will be described later.

  Before the first and second potential signals are supplied to the signal lines Soi and Sei, the TFTs 11n and 11p are turned on by the equalize signal, and the signal lines Soi and Sei are electrically connected to each other. Thereby, the potentials of the signal lines Soi and Sei are made uniform. That is, on the premise that the differential amplifier circuit 15 compares the first and second potential signals, the potentials of the signal lines Soi and Sei that supply these signals to the differential amplifier circuit 15 can be made uniform.

  When the first and second potential signals are supplied to the differential amplifier circuit 15 through the signal lines Soi and Sei having the same potential, the potentials of the first and second potential signals output from the pixel unit 70 are supplied. The first and second potential signals are supplied to the differential amplifier circuit 15 while maintaining the height relationship. Accordingly, it is possible to reduce the fluctuation of the potential relationship between the potential of the first potential signal and the potential of the second potential signal due to the potential difference between the signal lines Soi and Sei, and the potentials of the first potential signal and the second potential signal can be reduced. Reversal of the elevation relationship can be reduced.

  The first drive signal supply circuit 21 includes a first drive signal supply line 41 and a pull-up circuit 31. The first drive signal supply line 41 is electrically connected to the gate of the TFT 13p electrically connected to the differential amplifier circuit 15, and supplies the first drive signal SApE supplied from the outside to the gate of the TFT 13p. . The first drive signal SApE is a drive signal for driving the differential amplifier circuit 15. As will be described later, the differential amplifier circuit 15 has a high potential among the signals input to the connection points so and se. It functions as a sense amplifier that raises the potential of a signal it has and lowers the potential of a low signal. The TFT 13p is a p-channel TFT, and the TFT 13p is turned on when the first drive signal SApE is supplied to the gate, and supplies the power supply VDD to the connection point sp of the differential amplifier circuit 15. As will be described later, the TFT 13p is electrically connected to a body contact wiring 63 as an example of the “body contact means” according to the present invention.

  As shown in FIG. 7, the pull-up circuit 31 includes a p-channel TFT 131 whose gate is grounded. The TFT 131 supplies the power VDD to the first drive signal supply line 41.

  In FIG. 3 again, the second drive signal supply circuit 22 includes a second drive signal supply line 42 and a pull-down circuit 32. The second drive signal supply line 42 is electrically connected to the gate of the TFT 13n electrically connected to the differential amplifier circuit 15, and supplies the second drive signal SAnE supplied from the outside to the gate of the TFT 13n. . The TFT 13n is an n-channel TFT and is turned on when the second drive signal SAnE is supplied to the gate, and supplies the power supply VDD to the differential amplifier circuit 15. The pull-down circuit 32 maintains the potential of the second drive signal supply line 42. As will be described later, the TFT 13p is electrically connected to a body contact wiring 64 as an example of the “body contact means” according to the present invention.

  One differential amplifier circuit 15 is provided for each set of signal lines, each including the signal lines Soi and Sei. When the transmission gate 6 is turned on, the first and second potential signals are supplied from the signal lines Soi and Sei to the connection points so and se of the differential amplifier circuit 15, respectively. The differential amplifier circuit 15 compares the first and second potential signals, and outputs a high potential signal or a low potential signal to the test device, which is a determination unit, through each of the signal lines Soi and Sei.

  In FIG. 8, the differential amplifier circuit 15 is a cross-coupled differential amplifier circuit including p-channel TFTs 51 and 52 and n-channel TFTs 53 and 54. More specifically, a series circuit in which the TFTs 51 and 52 are electrically connected in series and a series circuit in which the TFTs 53 and 54 are electrically connected in series are electrically connected in parallel. The gate of the TFT 51 is electrically connected to the connection point so of the TFTs 52 and 54. The gate of the TFT 52 is electrically connected to the connection point se between the TFTs 51 and 53. The gate of the TFT 53 is electrically connected to the connection point so of the TFTs 52 and 54. The gate of the TFT 54 is electrically connected to the connection point se between the TFTs 51 and 53. The connection point so is electrically connected to the signal line Soi, and the connection point se is electrically connected to the signal line Sei. The connection point sp of the TFTs 51 and 52 is electrically connected to the drain of the TFT 13p. A connection point sn between the TFTs 53 and 54 is electrically connected to the drain of the TFT 13n.

  When the first potential signal has a slightly higher potential than the second potential signal, the differential amplifier circuit 15 applies a high potential signal whose potential is higher than that of the first potential signal to the signal line Soi. Output to an external test device. Thus, according to the high potential signal whose potential is increased, it is possible to clarify that the potential of the first potential signal is higher than the potential of the second potential signal. When the first potential signal has a slightly lower potential than the second potential signal, the differential amplifier circuit 15 applies a low potential signal whose potential is lower than that of the first potential signal to the signal line Soi. Output via. According to such a low potential signal, it is possible to clarify that the potential of the first potential signal is lower than the potential of the second potential signal.

  The second potential signal supplied to the differential amplifier circuit 15 via the signal line Sei is a reference potential that serves as a reference when the potential of the first potential signal is increased or decreased. The first potential signal is a signal that reflects whether or not the pixel portion 70 electrically connected to the signal line Soi has a defect, that is, the quality of the pixel portion 70, and the second potential signal and the first potential signal. Is slightly smaller than the potential that fluctuates depending on the wiring capacitance of these signal lines. The differential amplifier circuit 15 outputs a high potential signal or a low potential signal so that the level relationship between the potential of the first potential signal and the second potential signal can be clearly determined.

  Next, the inspection principle of the liquid crystal device according to this embodiment will be described with reference to FIGS. FIG. 9 is a block diagram of the inspection system.

  As shown in FIG. 9, at the time of inspection, the liquid crystal device 1 (that is, the TFT array substrate 10 in which the plurality of pixel portions 70 and the various circuits described above are formed before being bonded to the counter substrate 20) is inspected. It is electrically connected via a connection cable 160 to a test apparatus 150 capable of writing a signal and a reference signal, reading a high potential signal and a low potential signal, and the like. The connection cable 160 electrically connects the image signal supply lines 112o and 112e, the equalize signal supply line 43, the voltage application line 24, the precharge signal supply line 44, and the like of the liquid crystal device 1 to the test apparatus 150 via connection terminals. Connect (see FIG. 3).

  The test apparatus 150 determines whether or not a defect has occurred in the pixel unit 70 electrically connected to the signal line Soi based on the voltage logic. That is, the test apparatus determines whether the potential of the inspection signal that is the source of the first potential signal supplied to the pixel unit 70 in advance is higher or lower than the potential of the second potential signal, and the potential of the intermediate potential and the high potential signal. It is determined whether or not a defect has occurred in the pixel portion 70 by comparing the potential level information of the potential signal. More specifically, if the high-potential signal is output from the differential amplifier circuit 15 when the potential of the inspection signal that is the source of the first potential signal is higher than the intermediate potential, it is electrically connected to the signal line Soi. The test apparatus 150 determines that there is no malfunction in the pixel unit 70, that is, the pixel unit 70 to which the inspection signal that is the basis of the first potential signal is supplied. Similarly, if the low potential signal is output from the differential amplifier circuit 15 when the potential of the inspection signal that is the source of the first potential signal is lower than the potential of the second potential signal, it is electrically connected to the signal line Soi. The test apparatus 150 determines that there is no malfunction in the pixel unit 70, that is, the pixel unit 70 to which the inspection signal that is the basis of the first potential signal is supplied.

  If the low potential signal is output from the first differential amplifier circuit 15 when the potential of the inspection signal that is the basis of the first potential signal is higher than the potential of the second potential signal, the signal is connected to the signal line Soi. The test apparatus determines that some defect has occurred in the pixel unit 70, that is, the pixel unit 70 to which the inspection signal that is the basis of the first potential signal is supplied. If the high potential signal is output from the differential amplifier circuit 15 when the potential of the inspection signal that is the basis of the first potential signal is lower than the potential of the second potential signal, the pixel unit 70 that is electrically connected to the signal line Soi. That is, the test apparatus determines that some defect has occurred in the pixel unit 70 to which the inspection signal that is the basis of the first potential signal is supplied.

  Next, a procedure in which the differential amplifier circuit outputs a high potential signal or a low potential signal will be described with reference to FIGS. Here, a case where a first potential signal having a higher potential than the potential of the second potential signal having an intermediate potential is supplied to the differential amplifier circuit 15 will be described as an example.

  3 and 8, when the second drive signal supply circuit 22 supplies the second drive signal SAnE to the TFT 13n, the TFT 13n is turned on, and the potential at the connection point sn approaches the ground potential via the TFT 13n. . Since the source potential of the TFT 53 is set to an intermediate potential, a current flows between the source and drain of the TFT 53, and the potential of the connection point se decreases. At this time, since the gate of the p-channel TFT 52 is electrically connected to the connection point se, the TFT 52 is switched to the on state when the potential at the connection point se is lowered. When the first drive signal SApE is supplied from the first drive signal supply circuit 21 to the TFT 13p, the TFT 13p is switched on, and the power supply VDD is supplied to the connection point sp via the TFT 13p. Thereby, the power supply VDD is supplied to the connection point so via the TFTs 13p and 52, and the potential of the connection point so is increased.

  In this way, the differential amplifier circuit 15 increases the potential of the first potential signal and decreases the potential of the second potential signal. According to the differential amplifier circuit 15, when the potential of the first potential signal is higher than the intermediate potential (that is, the potential of the second potential signal), the first potential signal is converted into a high potential signal having a higher potential. 150 can be output. Therefore, the test device 150 serving as a determination unit can clearly determine the level relationship between the reference signal having a potential lower than the intermediate potential and the high potential signal, and can determine the quality of the pixel unit 70 based on the voltage logic.

  When the potential of the first potential signal is lower than the intermediate potential (that is, the potential of the second potential signal), the TFTs 51 and 54 operate in the differential amplifier circuit 15 similarly to the TFTs 52 and 53 described above, and the first potential is reached. A low potential signal is output based on the signal. In this case, the second potential signal set to the intermediate potential is output as a reference signal with an increased potential, and the first potential signal is output as a low potential signal having a potential lower than that of the reference signal. . Therefore, the test apparatus 150 can clearly determine the level relationship between the reference signal having a potential higher than the intermediate potential and the low potential signal, and can determine the quality of the pixel unit 70 based on the voltage logic.

  As described above, according to the liquid crystal device of the present embodiment, it is not necessary to contact an external probe, and inspection can be performed.

  Next, timing of various signals when the differential amplifier circuit 15 outputs a high potential signal or a low potential signal will be described with reference to FIGS. FIG. 10 is a timing chart showing the timing of various signals at the time of inspection. In FIG. 10, the pixel unit 70 corresponding to the signal line Soi is an inspection target, and the pixel unit 70 corresponding to the signal line Sei is used as a reference. That is, as described above with reference to FIG. 6, in the image display region 10a, the columns of the pixel portions 70 to which the intermediate potential signal is supplied and the columns of the pixel portions 70 to which the HIGH potential signal is supplied are alternately arranged. Take the case where it becomes a state.

  3 and 10, the inspection signal and the reference signal are supplied to the pixel unit 70 by the timing t1. That is, as described above with reference to FIG. 6, in the image display region 10a, the columns of the pixel portions 70 to which the intermediate potential signal is supplied and the columns of the pixel portions 70 to which the HIGH potential signal is supplied are alternately arranged. It is in the state. The precharge circuit 25 supplies the precharge signal PCG to the gates of the TFTs 12a and 12b via the precharge signal supply line 44 at timing t1. The TFTs 12 a and 12 b are turned on, and a precharge voltage is applied to the signal lines Soi and Sei via the voltage application wiring 24. The equalize circuit 23 supplies the equalize signal EQ to the TFTs 11p and 11n through the equalize signal supply line 43 at the same time as the timing t1 or at a timing that is in the vicinity of the timing t1. The TFTs 11p and 11n are turned on, and the signal lines Soi and Sei are electrically connected. By these operations of the precharge circuit 25 and the equalize circuit 23, the potentials of the signal lines Soi and Sei are set to an intermediate potential. Thereafter, the precharge circuit 25 ends the supply of the precharge signal PCG at the timing t2. Subsequently, the equalize circuit 23 ends the supply of the equalize signal EQ at the timing t3. It should be noted that the timing t3 when the equalizing circuit 23 finishes supplying the equalizing signal EQ is preferably after the timing t2 when the precharging circuit 25 finishes supplying the precharge signal PCG. In this way, when the TFTs 12a and 12b are switched from the on state to the off state, for example, the pushdown amount in the TFTs 12a and 12b can be reduced. Alternatively, it is possible to prevent the signal lines Soi and Sei from having different potentials due to electrical noise due to switching. That is, even if electrical noise is generated in the TFTs 12a and 12b, the signal lines Soi and Sei are electrically connected by the equalizing circuit 23, so that the potentials of the signal lines Soi and Sei are set to the same potential. Is done.

  After the transmission gate 6 is switched to the ON state, the scanning line G1 supplies a switching signal to the pixel unit 70 at timing t4, and the first and second potential signals are differentially transmitted via the signal lines Soi and Sei, respectively. This is supplied to the amplifier circuit 15. Note that the scanning line G1 supplies a switching signal to all the pixel portions 70 electrically connected to the scanning line G1, and the TFT 71 included in the pixel portion 70 electrically connected to the scanning line G1 is switched on. It is done. The first and second potential signals are supplied from each of the plurality of pixel portions 70 electrically connected to the scanning line G1 to the differential amplifier circuit 15 corresponding to these pixel portions 70.

  Here, when there is no malfunction in the pixel portion 70, the first potential signal having a potential higher than the intermediate potential, that is, the HIGH potential, is applied to the signal line in the same manner as the potential of the inspection signal previously supplied to the pixel portion 70. The signal is supplied to the differential amplifier circuit 15 via Soi. At this time, the first potential signal has a potential slightly higher than the intermediate potential. The potential of the signal line Sei that outputs the second potential signal is a preset intermediate potential, which is slightly lower than the potential of the first potential signal. As described above, when there is no problem in the pixel unit 70, the level relationship between the potential of the inspection signal and the intermediate potential supplied in advance to the pixel unit 70 is the potential of the first potential signal and the second potential. The signal potential level is maintained as it is.

  When the second drive signal SAnE is supplied from the second drive signal supply circuit 22 to the TFT 13n at the timing t5, the differential amplifier circuit 15 has a potential lower than the potential of the connection point so to which the first potential signal is supplied. The potential of the connection point se is lowered to a potential lower than that at the time when the second potential signal is supplied. As a result, the potential of the signal line Sei decreases (see the solid line portion of Sei in FIG. 10).

  When the first drive signal SApE is supplied from the first drive signal supply circuit 21 to the TFT 13p at the timing t6, the differential amplifier circuit 15 uses the potential of the connection point so to which the first potential signal is supplied as the second potential signal. Is higher than the potential at the time when is supplied. This increases the potential of the signal line Soi (see the solid line portion of Soi in FIG. 10).

  That is, at each of the timings t5 and t6, the potential of the connection point se to which the second potential signal having a low potential is supplied among the signals supplied to the differential amplifier circuit 15 is lowered to a lower level. The potential at the connection point so to which the one-potential signal is supplied is raised higher. Thereby, the level relationship of the potentials of the connection points so and Se becomes clear. The differential amplifier circuit 15 outputs a first high potential signal having the potential of the connection point so to the test apparatus 150 (see FIG. 9) via the signal line Soi. At the same time, the differential amplifier circuit 15 outputs a reference signal having the potential of the connection point se to the test apparatus 150 via the signal line Sei.

  The test apparatus 150 compares the high potential signal and the reference signal. Since the potential of the high potential signal is higher than that of the first potential signal and the potential of the reference signal is lower than that of the intermediate potential, the test apparatus can detect the second potential signal and a potential slightly higher than this second potential signal. It can be clearly determined that the potential of the high potential signal is higher than the potential of the reference signal as compared with the case of comparing the first potential signals having. Here, since the level relationship between the potential of the inspection signal and the intermediate potential matches the level relationship between the potential of the high potential signal and the potential of the reference signal, the test apparatus 150 has a problem with the pixel unit 70 to be inspected. It is determined that it has not occurred.

  Next, in order to determine the quality of the pixel portion electrically connected to the scanning line G2, a precharge voltage is supplied to the signal lines Soi and Sei between timings t7 and t8, and between timings t7 and t9. By electrically connecting the signal lines Soi and Sei, the signal lines Soi and Sei are set to the intermediate potential again. Note that the timing t9 is later than the timing t8.

  At timing t10, the scanning line G2 outputs a switching signal, and the switching signal is supplied to the pixel portion 70 that is electrically connected to the scanning line G2. The pixel unit 70 supplied with the switching signal outputs the first potential signal to the differential amplifier circuit 15 through the signal line Soi, similarly to the pixel unit 70 electrically connected to the scanning line G1. At this time, the signal line Sei supplies the second potential signal to the differential amplifier circuit 15. Accordingly, the high potential signal or the low potential signal corresponding to the pixel portion 70 electrically connected to the scanning line G2 among the pixel portions 70 electrically connected to the signal line Soi in the same manner as the scanning line G1, and A reference signal is output from the differential amplifier circuit 15 to the test apparatus 150 via each signal line, and the quality of the pixel unit 70 electrically connected to the scanning line G2 can be determined. In this way, it is possible to sequentially determine the quality of the pixel portion electrically connected to each of the scanning lines G3, G4,..., Gn. In addition, as described above, the high potential signal or the low potential signal output from each differential amplifier circuit 15 and the reference signal can be output to the test apparatus 150 for each differential amplifier circuit 15 via the sampling circuit 110. Therefore, it is possible to determine pass / fail for each pixel unit 70, and it can be confirmed that no defect occurs in each of the plurality of pixel units 70 arranged in the image display region 10a.

  Next, a case where a defect occurs in the pixel portion will be described with reference to FIGS.

  As described above with reference to FIG. 6, the pixel unit 70 includes, in the image display region 10 a, a column of pixel units 70 to which an intermediate potential signal is supplied and a pixel to which a HIGH potential signal (that is, an inspection signal) is supplied. The rows of the sections 70 are arranged alternately. At timing t <b> 4 when the switching signal is supplied from the scanning line G <b> 1 to the pixel unit 70, the pixel unit 70 supplies the first potential signal having a potential slightly lower than the intermediate potential to the differential amplifier circuit 15. Note that the potential of the signal line Soi to which the first potential signal having a potential lower than the intermediate potential is supplied (that is, the potential of the connection point so) is L0 indicated by a dotted line in FIG. Here, the first potential signal has a potential lower than the intermediate potential when, for example, the pixel portion 70 includes a TFT in which current leakage occurs or a storage capacitor 73 in which current leakage occurs. Equivalent to.

  When the second drive signal SAnE is supplied from the second drive signal supply circuit 22 to the TFT 13n at the timing t5, the differential amplifier circuit 15 connects the connection point so to which the first potential signal having a potential lower than the intermediate potential is supplied. Is further lowered to a lower potential. More specifically, the potential of the first potential signal supplied to the connection point so of the differential amplifier circuit 15 is slightly lower than the potential of the second potential signal supplied to the connection point se of the differential amplifier circuit 15. Therefore, the differential amplifier circuit 15 compares the potentials of the first potential signal and the second potential signal, and outputs a low potential signal via the connection point so. As a result, the potential of the signal line Soi decreases (indicated by a dotted line L1 in FIG. 10).

  At timing t6, when the first drive signal SApE is supplied from the first drive signal supply circuit 21 to the TFT 13p, the differential amplifier circuit 15 increases the potential of the second potential signal. More specifically, since the potential at the connection point se is higher than the potential at the connection point so reduced by the differential amplifier circuit 15, the differential amplifier circuit 15 sets the potential at the connection point se to an intermediate potential. Increase to higher potential. The differential amplifier circuit 15 outputs a reference signal having a potential equal to the potential of the connection point se whose potential is higher than the intermediate potential. Thereby, the potential of the signal line Sei is thereby increased (see the dotted line portion of Soi in FIG. 10).

  As a result, the test apparatus 150 detects the low potential signal and the reference signal while maintaining the level relationship between the first potential signal and the second potential signal supplied to the signal lines Soi and Sei. The test apparatus 150 can clearly detect that the potential of the first potential signal is lower than the intermediate potential by detecting the low potential signal whose potential is lower than that of the first potential signal. The level relationship between the low potential signal and the intermediate potential is opposite to the level relationship between the potential of the inspection signal and the potential of the intermediate potential. In such a case, the test apparatus 150 has a problem in the pixel unit 70. judge.

  As described above, according to the liquid crystal device of the present embodiment, the level relationship between the potential of the inspection signal and the intermediate potential supplied in advance to the pixel unit 70 and the high potential signal or the low potential signal whose potential is compared by the test device. By determining whether the potential relationship between the potential and the potential of the reference signal matches, it is possible to determine whether or not a defect has occurred in the pixel portion 70. Accordingly, the yield of electro-optical devices such as liquid crystal devices can be increased, and the manufacturing cost can be reduced.

  Next, malfunction of the differential amplifier circuit will be described with reference to FIGS. FIG. 11 is a timing chart for explaining a malfunction of the differential amplifier circuit. Hereinafter, an example of a malfunction that determines that the pixel unit 70 is not defective even though the pixel unit 70 is defective will be described. Note that a malfunction that determines that the pixel unit 70 is defective even though the pixel unit 70 is not defective also occurs for the same reason.

  In FIG. 11, as described above, the signal lines Soi and Sei are aligned to the intermediate potential by the timing t3. At the timing t3, the equalizing circuit 23 ends the supply of the equalizing signal EQ at the timing t3. That is, the TFTs 11n and 11p are switched from the on state to the off state. At this time, in the TFTs 11n and 11p, electrical noise may occur due to extra carriers accumulated in the active layer where the channel is formed. For this reason, as shown in FIG. 11, due to electrical noise, the potentials of the signal lines Soi and Sei may change, and the potentials of the signal lines Soi and Sei may shift from each other. That is, the potential of the signal line Soi may be higher than the potential of the signal line Sei.

At the timing t4 when the switching signal is supplied from the scanning line G1 to the pixel unit 70, if a malfunction occurs in the pixel unit 70, for example, a current leak occurs in the TFT 71 or the storage capacitor 73 in the pixel unit 70. The potential of the signal line Soi is slightly lowered.
At this time, as described above, since the potential of the signal line Soi is higher than the potential of the signal line Sei due to electrical noise, the potential of the signal line Sei is reduced even if it is slightly lowered to reflect current leakage. May remain higher. That is, since the potentials of the signal lines Sei and Soi are shifted from each other, the level relationship between the first potential signal that reflects the quality of the pixel unit 70 output from the pixel unit 70 and the reference second potential signal. May not be maintained as a potential relationship between the signal lines Sei and Soi.

  When the second drive signal SAnE is supplied from the second drive signal supply circuit 22 to the TFT 13n at the timing t5, the differential amplifier circuit 15 sets a potential lower than the potential of the connection point so (that is, the potential of the signal line Soi). The potential of the connection point se (that is, the potential of the signal line Sei) is lowered to a potential lower than that at the time when the potential of the signal line Sei is supplied.

  When the first drive signal SApE is supplied from the first drive signal supply circuit 21 to the TFT 13p at the timing t6, the differential amplifier circuit 15 uses the potential at the connection point so (that is, the potential of the signal line Soi) as the signal line Soi. Higher than the potential at the time of supply.

  In this way, at each of timings t5 and t6, the differential amplifier circuit 15 lowers the potential of the signal line Sei and raises the potential of the signal line Soi higher. That is, the signal is output as a signal having a reverse relationship to the height relationship between the signal lines Sei and Soi that should be output when a defect occurs in the pixel unit 70. As a result, the test apparatus 150 determines that a defect has not occurred even though a defect has occurred in the pixel unit 70.

  Note that the potential difference between the first potential signal and the second potential signal is often the same as or smaller than the electrical noise described above, and thus the above-described malfunction may occur. Furthermore, the malfunction of the differential amplifier circuit 15 due to electrical noise due to switching as described above can occur in all TFTs constituting the inspection circuit.

  Next, the body contact wiring of the liquid crystal device according to the present embodiment will be described with reference to FIG. 3 again.

  As shown in FIG. 3, in the present embodiment, the equalize circuit 23 includes body contact wires 61 and 62. The body contact wirings 61 and 62 are electrically connected to the extending portions of the active layers in the TFTs 11n and 11p, respectively. The body contact wiring 61 is supplied with a ground potential, and the body contact wiring 62 is supplied with a power supply potential VDD. In other words, the potentials in the active layers of the TFTs 11n and 11p are fixed to the ground potential and the power supply potential VDD by the body contact wirings 61 and 62, respectively. That is, the TFTs 11n and 11p are in body contact with the body contact wires 61 and 62, respectively. That is, it is configured to remove excess carriers accumulated in the active layer in which the channels in the TFTs 11n and 11p are formed. Therefore, when the TFTs 11n and 11p are switched from the on state to the off state (that is, timing t3 in FIGS. 10 and 11), excess carriers accumulated in the active layer where the channel is formed are transferred to the body contact wiring. 61 and 62 can be pulled through the extension. That is, it is possible to suppress an increase in push-down or push-up in the TFTs 11n and 11p due to the extra carriers accumulated in the active layer, or to reduce the generation of electrical noise. Therefore, due to electrical noise due to switching in the TFTs 11n and 11p constituting the equalize circuit 23, for example, the potential of the first potential signal (that is, the potential of the signal line Soi) (see Soi in FIG. 11) and the first It is possible to prevent the potential of the two-potential signal (that is, the potential of the signal line Sei) (see Sei in FIG. 11) from changing. Therefore, when the potential of the first potential signal and the potential of the second potential signal change, the level relationship between the potential of the first potential signal and the potential of the second potential signal is caused by an increase in pushdown or pushup or switching. It is possible to prevent the opposite relationship from the case where no electrical noise is generated. Thereby, it is possible to prevent the differential amplifier circuit 15 from malfunctioning and to obtain an accurate comparison result.

  In the inspection, the equalizer circuit 23 electrically connects the signal lines Soi and Sei (that is, shorts or shorts) before the first potential signal is output from the pixel unit 70, and the signal lines Soi and Sei are connected. The TFTs 11n and 11p constituting the equalize circuit 23 are formed to be relatively small, as long as they have a function of setting the same potential to each other. For this reason, electrical noise due to switching is likely to occur in the TFTs 11n and 11p. Therefore, taking the body contact in the TFTs 11n and 11p ensures that the differential amplifier circuit 15 malfunctions as compared with the case of taking the body contact in other relatively large TFTs constituting the inspection circuit 4. It can be prevented efficiently. For this reason, little or preferably no increase in the size of the TFT array substrate 10 by providing body contacts in the TFTs 11n and 11p is required.

  Further, as shown in FIG. 8, in the present embodiment, the differential amplifier circuit 15 includes body contact wirings 65 and 66, in particular. The body contact wiring 65 is electrically connected to the extending portion of the active layer in the TFTs 51 and 52, respectively. The body contact wiring 66 is electrically connected to the extending portion of the active layer in the TFTs 53 and 54, respectively. Yes. The body contact wiring 65 is supplied with a power supply potential VDD, and the body contact wiring 66 is supplied with a ground potential. That is, the TFTs 51 and 52 are in body contact with the body contact wiring 65, and the TFTs 53 and 54 are in body contact with the body contact wiring 66. That is, it is configured such that excess carriers accumulated in the active layer in which the channels in the TFTs 51, 52, 53 and 54 are formed can be removed. For this reason, when the TFTs 51, 52, 53, and 54 are switched from the on state to the off state (that is, at timing t5 or t6 in FIGS. 10 and 11), extra storage accumulated in the active layer in which the channel is formed. The carrier can be pulled out through the extension by the body contact wirings 65 and 66. That is, it is possible to reduce the occurrence of push-down or push-up in the TFTs 51, 52, 53 and 54 and electrical noise due to the extra carriers accumulated in the active layer. Therefore, for example, the potential of the first potential signal and the potential of the second potential signal change due to electrical noise due to switching in the TFTs 51, 52, 53, and 54 constituting the differential amplifier circuit 15, respectively. Can be prevented. Thereby, it is possible to further prevent the differential amplifier circuit 15 from malfunctioning and obtain an accurate comparison result.

  In the differential amplifier circuit 15, the TFTs 51, 52, 53, and 54 are switched when comparing the first potential signal (that is, the potential of the signal line Soi) and the second potential signal (that is, the potential of the signal line Sei). Done. Therefore, electrical noise caused by switching in the TFTs 51, 52, 53, and 54 is switched to ON / OFF before and after the comparison of the first potential signal and the second potential signal. Compared to the above, the comparison result is greatly affected. Therefore, taking the body contact in the TFTs 51, 52, 53 and 54 ensures that the differential amplifier circuit 15 malfunctions as compared with the case of taking the body contact in the other TFTs constituting the inspection circuit 4. It can be prevented efficiently.

  In addition, as shown in FIG. 3 again, in this embodiment, the TFT 13p and the TFT 13n are provided with body contact wirings 63 and 64, respectively. The body contact wirings 63 and 64 are electrically connected to the extended portions of the active layers in the TFTs 13p and 13n, respectively. The body contact wiring 63 is supplied with a power supply potential VDD, and the body contact wiring 64 is supplied with a ground potential. That is, the body contacts of the TFTs 13p and 13n are made by the body contact wirings 63 and 64, respectively. That is, it is configured to remove excess carriers accumulated in the active layer in which the channels in the TFTs 13p and 13n are formed. Therefore, when the TFTs 13p and 13n are switched from the on state to the off state (that is, timing t5 or t6 in FIGS. 10 and 11), excess carriers accumulated in the active layer in which the channel is formed are removed from the body. The contact wirings 63 and 64 can be removed through the extending portion. That is, it is possible to reduce the occurrence of push-down or push-up in the TFTs 13p and 13n and electrical noise due to the extra carriers accumulated in the active layer. Therefore, for example, the potential of the first potential signal and the potential of the second potential signal are caused by electrical noise due to switching in the TFTs 13p and 13n for supplying power for driving the differential amplifier circuit 15, respectively. It can be prevented from changing. Thereby, it is possible to further prevent the differential amplifier circuit 15 from malfunctioning and obtain an accurate comparison result.

  When the differential amplifier circuit 15 compares the first potential signal and the second potential signal, the TFTs 13p and 13n are switched. Therefore, electrical noise caused by switching in the TFTs 13p and 13n is compared with other TFTs constituting the inspection circuit 4 in which on / off switching is performed before and after the comparison of the first potential signal and the second potential signal. The comparison result is greatly affected. Therefore, taking the body contact in the TFTs 13p and 13n reliably or efficiently prevents the differential amplifier circuit 15 from malfunctioning as compared with the case of taking the body contact in the other TFTs constituting the inspection circuit 4. can do.

  Next, a specific configuration of the equalizing circuit of the liquid crystal device according to the present embodiment and the body contact wiring electrically connected thereto will be described with reference to FIGS. FIG. 12 is a plan view showing the equalizing circuit and the body contact wiring. FIG. 13 is an explanatory view showing an impurity doped region of a semiconductor layer. 14 is a cross-sectional view taken along line AA ′ of FIG. Note that body contact wirings 65 and 66 electrically connected to the TFTs 51, 52, 53, and 54 constituting the differential amplifier circuit 15, and body contact wirings 63 and 64 electrically connected to the TFTs 13p and 13n, respectively. The configuration is almost the same as body contact wiring 60A and 60B described below.

  In FIG. 12, the equalize circuit 23 includes TFTs 11n and 11p, and body contact portions 60A and 60B. Here, the body contact portions 60A and 60B are examples of the “extending portion” according to the present invention.

  In FIG. 14, a base insulating film 120 and interlayer insulating films 410, 420, and 430 are sequentially stacked on the TFT array substrate 10. The base insulating film 120 is made of, for example, a silicon oxide film, and the interlayer insulating films 410, 420, and 430 are made of, for example, NSG (non-silicate glass).

  12 and 14, the TFT 11 n includes a gate electrode 3 n, a semiconductor layer 111, and an insulating film 2 including a gate insulating film that insulates the gate electrode 3 n and the semiconductor layer 111. The gate electrode 3n is made of, for example, conductive polysilicon. The semiconductor layer 111 is made of, for example, polysilicon, and includes a channel region 11nc, a source region 11ns, and a drain region 11nd as shown in FIG. The TFT 11n has a self-aligned structure in which a source region 11sn and a drain region 11nd are formed by implanting N-type impurities at a high concentration using the gate electrode 3n as a mask. The TFT 11n may have an LDD (Lightly Doped Drain) structure. As shown in FIGS. 12 and 14, the source region 11 ns is electrically connected to the branch wiring Xei (i = 1,..., M; m is a natural number) through a contact hole 81 opened in the interlayer insulating film 430. The drain region 11nd is electrically connected to the branch wiring Xoi (i = 1,..., M; m is a natural number) through a contact hole 82 opened in the interlayer insulating film 430. ing. The branch wirings Xoi and Xei are made of a conductive film such as aluminum. The branch wiring Xei is branched from the signal line Sei, and the branch wiring Xoi is branched from the signal line Soi. The gate electrode 3n is electrically connected to a relay layer 630 made of the same film as the branch wirings Xoi and Xei through a contact hole 86 opened in the interlayer insulating film 410. Note that the relay layer 630 is formed in an island shape, for example, separately from other components made of the same film such as the branch wirings Xoi and Xei. The relay layer 630 is electrically connected to the equalize signal supply line 43a through a contact hole 87 opened in the interlayer insulating film 420. That is, the gate electrode 3n is electrically connected to the equalize signal supply line 43a through the relay layer 630.

  The TFT 11p includes an insulating film 2 including a gate electrode 3p, a semiconductor layer 112, and a gate insulating film that insulates the gate electrode 3p from the semiconductor layer 112. The gate electrode 3p is formed of the same film as the gate electrode 3n, that is, for example, conductive polysilicon. The semiconductor layer 112 is made of the same film as the semiconductor layer 111, that is, polysilicon, for example, and as shown in FIG. 13, is made up of a channel region 11pc, a source region 11ps, and a drain region 11pd. The TFT 11p has a self-aligned structure in which a source region 11ps and a drain region 11pd are formed by implanting P-type impurities at a high concentration using the gate electrode 3p as a mask. The TFT 11n may have an LDD structure. As shown in FIGS. 12 and 14, the source region 11ps is electrically connected to the branch wiring Xei through the contact hole 91 opened in the interlayer insulating film 430, and the drain region 11pd is connected to the interlayer insulating film. It is electrically connected to the branch wiring Xoi through a contact hole 92 opened at 430. The gate electrode 3p is electrically connected to a relay layer 640 made of the same film as the branch wirings Xoi and Xei through a contact hole 96 opened in the interlayer insulating film 410. The relay layer 640 is formed in an island shape, for example, like the relay layer 630. The relay layer 640 is electrically connected to the equalize signal supply line 43b through a contact hole 97 opened in the interlayer insulating film 420. That is, the gate electrode 3p is electrically connected to the equalize signal supply line 43b through the relay layer 640.

  As shown in FIG. 13, in this embodiment, the TFTs 11n and 11p have body contact portions 60A and 60B, respectively.

  The body contact portion 60A is composed of the semiconductor layer 111 constituting the active layer of the TFT 11n, and is formed in the extending portion of the active layer of the TFT 11n. Body contact portion 60A is doped with a P-type impurity having the same polarity as channel region 11nc.

  As shown in FIGS. 12 and 14, the body contact portion 60A is electrically connected to the relay layer 610 made of the same film as the branch lines Xoi and Xei through the contact holes 83 and 85 opened in the interlayer insulating film 410. Connected. The relay layer 610 is formed in an island shape, for example, like the relay layer 630 and the like. The relay layer 610 is electrically connected to the body contact wiring 61 through a contact hole 84 opened in the interlayer insulating film 420. That is, the body contact portion 60A is electrically connected to the body contact wiring 61 via the relay layer 610 and is fixed to the ground potential. Therefore, excess carriers (that is, electrons) accumulated in the channel region 11nc when the TFT 11n is switched from the on state to the off state can be extracted via the body contact portion 60A. That is, it is possible to reduce the occurrence of push-down in the TFT 11n due to excess carriers accumulated in the channel region 11nc. Furthermore, it is possible to prevent the differential amplifier circuit 15 from malfunctioning due to electrical noise due to switching.

  As shown in FIG. 13, the body contact portion 60B is composed of the semiconductor layer 112 that constitutes the active layer of the TFT 11p, and is formed in the extending portion of the active layer of the TFT 11p. Body contact portion 60B is doped with an N-type impurity having the same polarity as channel region 11pc.

  As shown in FIG. 12, the body contact portion 60B is electrically connected to the relay layer 620 made of the same film as the branch wirings Xoi and Xei through the contact holes 93 and 95 opened in the interlayer insulating film 410. Has been. The relay layer 620 is formed in an island shape, for example, like the relay layer 610 and the like. The relay layer 620 is electrically connected to the body contact wiring 62 through a contact hole 94 opened in the interlayer insulating film 420. That is, the body contact portion 60B is electrically connected to the body contact wiring 62 via the relay layer 620 and is fixed to the power supply potential VDD. Therefore, excess carriers (that is, holes) accumulated in the channel region 11pc when the TFT 11p is switched from the on state to the off state can be extracted through the body contact portion 60B. That is, push-up and electrical noise in the TFT 11p due to extra carriers accumulated in the channel region 11pc can be reduced. Therefore, it is possible to prevent the differential amplifier circuit 15 from malfunctioning due to electrical noise.

  As shown in FIG. 13, in the present embodiment, the body contact portion 60A is impurity-doped to P-type having the same polarity as the channel region 11nc, that is, has carriers (that is, holes) having the same polarity. . Therefore, excess carriers accumulated in the active layer where the channel is formed when switched from the on state to the off state are reliably extracted from the channel region 11nc to the body contact wiring 61 connected to the body contact portion 60A. be able to. Furthermore, since the body contact portion 60A has a conductivity type opposite to that of the source region 11ns and the drain region 11nd, it is possible to prevent carriers from moving from the source region 11ns and the drain region 11nd to the body contact portion 60A.

As shown in FIG. 13, in this embodiment, the body contact portion 60B is doped with an N-type impurity having the same polarity as that of the channel region 11pc, that is, has carriers (that is, electrons) having the same polarity. Therefore, excess carriers accumulated in the active layer where the channel is formed when switched from the on state to the off state are surely extracted from the channel region 11pc to the body contact wiring 62 connected to the body contact portion 60B. be able to. Furthermore, since the body contact portion 60B has a conductivity type opposite to that of the source region 11ps and the drain region 11pd, carrier movement from the source region 11ps and the drain region 11pd to the body contact portion 60B can be prevented.
Second Embodiment
Next, a liquid crystal device according to a second embodiment will be described with reference to FIG. FIG. 15 is a block diagram having the same concept as in FIG. 3 in the second embodiment. In FIG. 15, the same reference numerals are given to the same components as the components according to the first embodiment shown in FIGS. 1 to 14, and description thereof will be omitted as appropriate. In FIG. 15, the X driver circuit 101, the Y driver circuit 104, the sampling circuit 110, and the like that drive the plurality of pixel units 70 are not shown for the sake of simplification.

  15, the liquid crystal device according to the present embodiment includes a plurality of pixel units 70, an X driver circuit 101, a Y driver circuit 104, a sampling circuit 110, image signal supply lines 112o and 112e, a differential amplifier circuit 15, and a first drive. The configurations of the signal supply circuit 21, the second drive signal supply circuit 22, the equalize circuit 23, the voltage application wiring 24, and the precharge circuit 25 are the same as those of the liquid crystal device according to the first embodiment described above.

  The present embodiment is different from the liquid crystal device according to the first embodiment described above in that a transmission gate 6 ′ is employed instead of the transmission gate 6. That is, four signal lines S correspond to one differential amplifier circuit 15, and two of them can be selected and electrically connected as a set. Therefore, one differential amplifier circuit 15 can be formed for every interval at which the four signal lines S are arranged, the area of the differential amplifier circuit 15 is increased, the driving capability is improved, and the differential amplification is performed. Inspection accuracy can be improved by reducing variations in the circuit 15. The pull-down circuit 36 is configured similarly to the pull-down circuit 35 described above with reference to FIG.

  In FIG. 15, the transmission gate 6 ′ selectively electrically connects the connection point se of the differential amplifier circuit 15 to one of the two signal lines S, and also connects the connection point so of the differential amplifier circuit 15. It is selectively electrically connected to one of the two signal lines S. That is, the differential amplifier circuit 15 is provided for each of the four signal lines S. The connection point se of the differential amplifier circuit 15 is electrically connected to the signal line S of the (4u + 1) -th column or the (4u + 2) -th column (where u is an integer of 0 or more) via the TFT 14'd or 14'c, respectively. Connected to. The connection point so of the differential amplifier circuit 15 is electrically connected to the signal line S in the (4u + 3) th column or the (4u + 4) th column via the TFT 14'b or 14'a, respectively.

  Terminals te1 to te4 are electrically connected to the gates of the TFTs 14'a to 14'd, respectively. For example, an external circuit such as a TE gate decode circuit is electrically connected to the terminals te1 to te4 and supplied with connection control signals TE1 to TE4, respectively. The connection control signals TE1 to TE4 are signals for determining which signal line S the connection points so and se of the differential amplifier circuit 15 are electrically connected to. The TFTs 14'a to 14'd to which the LOW connection control signals TE1 to TE4 are applied to the gates are turned off, and the electrical connection between the connection points so and se of the differential amplifier circuit 15 and the signal line S is cut off. . Conversely, 14'a to 14'd to which the HIGH connection control signals TE1 to TE4 are applied to the gates are turned on, and the connection points so and se of the differential amplifier circuit 15 and the signal line S are electrically connected. . The connection control signals TE1 and TE2 are not simultaneously set to HIGH, and the connection control signals TE3 and TE4 are not simultaneously set to HIGH. That is, at the connection points se and so of the differential amplifier circuit 15, a signal line S in the (4u + 1) th column and the (4u + 3) th column, or a signal in the (4u + 2) th column and the (4u + 4) th column. Each pair of lines S is electrically connected. It should be noted that the signal lines S in the (4u + 1) th column and the (4u + 4) th column or the signal lines in the (4u + 2) th column and the (4u + 3) th column are connected to the connection points se and so of the differential amplifier circuit 15. You may comprise so that the connection control signals TE1-TE4 may be output so that it may be electrically connected by the group of S, respectively.

Thus, for example, when the connection control signal TE4 is supplied to the terminal te4, the TFT 14'd is turned on, and the signal line S in the (4u + 1) th column is connected to the connection point of the differential amplifier circuit 15. electrically connected to se. At the same time or before and after this, when the connection control signal TE2 is supplied to the terminal te2, the TFT 14'b is turned on, and the signal line S in the (4u + 3) th column is connected to the connection point so of the differential amplifier circuit 15. Electrically connected. Therefore, a reference signal is supplied in advance to the pixel portions 70 electrically connected to the signal lines S1, S5, S9,..., And the signal lines S3, S7, S11,. By supplying the inspection signal to the connected pixel unit 70, the quality of the pixel unit 70 electrically connected to the signal lines S3, S7, S11,. Inspection can be done. Similarly, when the connection control signal TE4 is supplied to the terminal te3, the TFT 14'c is turned on, and the (4u + 2) -th column signal line S is electrically connected to the connection point se of the differential amplifier circuit 15. . At the same time or before and after this, when the connection control signal TE1 is supplied to the terminal te1, the TFT 14'a is turned on, and the signal line S in the (4u + 4) th column is connected to the connection point so of the differential amplifier circuit 15. Electrically connected. Therefore, a reference signal is supplied in advance to the pixel portions 70 electrically connected to the signal lines S2, S6, S10,..., And the signal lines S4, S8, S12,. By supplying the inspection signal to the connected pixel unit 70, the quality of the pixel unit 70 electrically connected to the signal lines S4, S8, S12,. Inspection can be done.
<Electronic equipment>
Next, the case where the liquid crystal device which is the above-described electro-optical device is applied to various electronic devices will be described.

  First, a projector using this liquid crystal device as a light valve will be described. FIG. 16 is a plan view showing a configuration example of the projector. As shown in FIG. 16, a projector 1100 includes a lamp unit 1102 made of a white light source such as a halogen lamp. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by four mirrors 1106 and two dichroic mirrors 1108 arranged in the light guide 1104, and serves as a light valve corresponding to each primary color. The light enters the liquid crystal panels 1110R, 1110B, and 1110G.

  The configurations of the liquid crystal panels 1110R, 1110B, and 1110G are the same as those of the liquid crystal device described above, and are driven by R, G, and B primary color signals supplied from the image signal processing circuit. The light modulated by these liquid crystal panels enters the dichroic prism 1112 from three directions. In this dichroic prism 1112, R and B light is refracted at 90 degrees, while G light travels straight. Therefore, as a result of the synthesis of the images of the respective colors, a color image is projected onto the screen or the like via the projection lens 1114.

  Here, paying attention to the display images by the liquid crystal panels 1110R, 1110B, and 1110G, the display image by the liquid crystal panel 1110G needs to be horizontally reversed with respect to the display images by the liquid crystal panels 1110R, 1110B.

  Since light corresponding to the primary colors R, G, and B is incident on the liquid crystal panels 1110R, 1110B, and 1110G by the dichroic mirror 1108, it is not necessary to provide a color filter.

  Next, an example in which the liquid crystal device is applied to a mobile personal computer will be described. FIG. 17 is a perspective view showing the configuration of this personal computer. In FIG. 17, a computer 1200 includes a main body 1204 provided with a keyboard 1202 and a liquid crystal display unit 1206. The liquid crystal display unit 1206 is configured by adding a backlight to the back surface of the liquid crystal device 1005 described above.

  Further, an example in which the liquid crystal device is applied to a mobile phone will be described. FIG. 18 is a perspective view showing the configuration of this mobile phone. In FIG. 18, a mobile phone 1300 includes a reflective liquid crystal device 1005 together with a plurality of operation buttons 1302. In the reflective liquid crystal device 1005, a front light is provided on the front surface thereof as necessary.

  In addition to the electronic devices described with reference to FIGS. 16 to 18, a liquid crystal television, a viewfinder type, a monitor direct view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, a word processor, a work Examples include a station, a videophone, a POS terminal, a device equipped with a touch panel, and the like. Needless to say, the present invention can be applied to these various electronic devices.

  In addition to the liquid crystal device described in the above embodiment, the present invention also includes a reflective liquid crystal device (LCOS) in which elements are formed on a silicon substrate, a plasma display (PDP), a field emission display (FED, SED), The present invention can also be applied to an organic EL display, a digital micromirror device (DMD), an electrophoresis apparatus, and the like.

  The present invention is not limited to the above-described embodiments, and can be appropriately changed without departing from the spirit or concept of the invention that can be read from the claims and the entire specification. An electronic apparatus including the electro-optical device is also included in the technical scope of the present invention.

It is a top view which shows the whole structure of the liquid crystal device which concerns on 1st Embodiment. It is sectional drawing in the HH 'line of FIG. 1 is a block diagram illustrating a main circuit configuration of a liquid crystal device according to a first embodiment. It is a circuit diagram which shows the electrical structure of a pixel part. It is a circuit diagram which shows the electric constitution of a pull-down circuit. It is a conceptual diagram which shows the state of the pixel part to which the signal was supplied previously at the time of a test | inspection. It is a circuit diagram which shows the electrical structure of a pull-up circuit. It is a circuit diagram which shows the electric constitution of a differential amplifier circuit. It is a block diagram of an inspection system. It is a timing chart which showed the timing of various signals at the time of inspection. 5 is a timing chart for explaining a malfunction of the differential amplifier circuit. It is a top view which shows an equalize circuit and body contact wiring. It is explanatory drawing which shows the area | region of impurity doping of a semiconductor layer. It is sectional drawing in the AA 'line of FIG. It is a block diagram with the same meaning as FIG. 3 in 2nd Embodiment. It is a top view which shows the structure of the projector which is an example of the electronic device to which the electro-optical apparatus is applied. 1 is a perspective view showing a configuration of a personal computer as an example of an electronic apparatus to which an electro-optical device is applied. It is a perspective view which shows the structure of the mobile telephone which is an example of the electronic device to which the electro-optical apparatus is applied.

Explanation of symbols

  6, 6 '... transmission gate, 10 ... TFT array substrate, 10a ... image display area, 11n, 11p, 13n, 13p ... TFT, 15 ... differential amplifier circuit, 20 ... counter substrate, 23 ... equalize circuit, 25 ... pre Charge circuit, 50 ... liquid crystal layer, 60A, 60B ... body contact part, 61, 62, 63, 64, 65, 66 ... body contact wiring, 70 ... pixel part, 110 ... sampling circuit, 101 ... X driver circuit, 104 ... Y driver circuit, Gj ... scanning line, Soi, Sei ... signal line,

Claims (6)

On the board
A plurality of scanning lines and a plurality of signal lines intersecting each other;
A plurality of pixel portions arranged corresponding to intersections of the plurality of scanning lines and the plurality of signal lines;
Each of the plurality of transistors includes a plurality of transistors, and is provided corresponding to each of a predetermined number of signal lines among the plurality of signal lines, and is provided via one signal line of the predetermined number of signal lines. A first potential signal is supplied and a second potential signal as a reference potential is supplied via another signal line, and the potential of the first potential signal is compared with the potential of the second potential signal. i) When the potential of the first potential signal is lower than the potential of the second potential signal, a low potential signal having a potential lower than the potential of the first potential signal is obtained. (ii) The potential of the first potential signal A plurality of amplifying circuits for outputting a high potential signal having a potential higher than the potential of the first potential signal when the potential is higher than the potential of the second potential signal;
An electro-optical device, comprising: a body contact unit that is provided in an extension portion of an active layer in at least one transistor of the plurality of transistors and takes a body contact in the one transistor.   The electro-optical device according to claim 1, wherein the body contact unit includes a contact portion that contacts the extension portion and a wiring portion that is electrically connected to the contact portion. The plurality of amplifying circuits are provided for each set of the two signal lines, and are equalized including a first transistor for controlling electrical connection between the two signal lines. Each has its own circuit
The electro-optical device according to claim 1, wherein the body contact unit takes a body contact in at least the first transistor as the one transistor. Each of the plurality of amplifier circuits has a differential amplifier circuit including a plurality of second transistors,
4. The electro-optical device according to claim 1, wherein the body contact unit takes a body contact in at least the second transistor as the one transistor. 5. Each of the plurality of amplification circuits has a drive circuit including at least one third transistor for supplying power for driving the plurality of amplification circuits.
4. The electro-optical device according to claim 1, wherein the body contact unit makes a body contact in at least the third transistor as the one transistor. 5.   An electronic apparatus comprising the electro-optical device according to claim 1.

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