JP2007133060A - Electrooptical apparatus and electronic equipment with the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To judge the quality of a pixel one by one, regarding an electrooptical apparatus such as a liquid crystal apparatus. <P>SOLUTION: The electrooptical apparatus includes: a plurality of scanning lines; a plurality of data lines; a plurality of pixel parts; and an amplifier arranged on a substrate; and the amplifier has first and second terminals and compares the potential of a potential signal supplied to the first terminal with the potential of the potential signal supplied to the second terminal, and outputs the potential signal while making the potential of the first terminal lower when the potential signal supplied to the first terminal is lower than that of the second terminal, and outputs the potential while making the potential of the first terminal higher when the potential signal supplied to the first terminal is higher than that of the second terminal. The apparatus also includes a supply means that supplies a reference potential to one of the first and second terminal, reads the potential signal inputted to the pixel part and supplies the potential signal to the other, and a capacitance electrically connected to at least one of the first and second terminals, and also, constituted by layering a first electrode composed of a first metal film and a second electrode composed of a first dielectric film and a second metal film in this order. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a technical field of an electro-optical device such as a liquid crystal device, and an electronic apparatus such as a liquid crystal projector including the electro-optical device.

  An electro-optical device such as a liquid crystal device includes a step of inspecting a substrate for an electro-optical device such as a TFT array substrate on which a thin film transistor (hereinafter referred to as “TFT”) is formed, a TFT array substrate, and a liquid crystal And a step of enclosing a liquid crystal between opposing substrates on which an opposing electrode for driving an electro-optical element is formed. The inspection of whether or not the finished liquid crystal device operates normally is performed based on whether or not the image displayed by the completed liquid crystal device is correctly displayed. In such an electro-optical device, if a defect of the TFT formed on the TFT array substrate is not detected in the process of inspecting the TFT array substrate, the defect is detected by the inspection performed on the liquid crystal device which is the finished product. Will be.

  As countermeasures when a defect is detected in the finished liquid crystal device, measures such as exchanging the TFT array substrate after repairing the liquid crystal from the liquid crystal device or repairing the defective part can be considered. These measures are practically difficult to adopt in view of a decrease in yield and an increase in cost when manufacturing the product. In addition, the process after forming the TFT array substrate becomes a useless process, and there is a problem in that the yield is reduced and the cost is increased when manufacturing an electro-optical device such as a liquid crystal device.

  As one means for solving such a problem, for example, in Patent Document 1, a pixel is associated with all intersections of two signal lines and scanning lines electrically connected to a comparator in a pixel array. Disclosed is a technique for inspecting whether a pixel has a defect by comparing potential information supplied to two pixels when the electro-optical device substrate is formed.

JP 2004-226551 A

  However, according to the technique disclosed in Patent Document 1, when a pixel arranged in a region where one signal line and a scanning line intersect between two signal lines electrically connected to a comparator is inspected The potentials of the signals supplied to the pixels arranged in the region where the other signal line and the scanning line intersect with each other become the reference potential, and the reference potential fluctuates due to a defect in the pixel on the reference potential side. As a result, it is determined that there is a defect in a normal pixel to be inspected, and there is a technical problem that a defect of one pixel is detected as a defect of two pixels. In addition, there is a technical problem that it is difficult to electrically detect what kind of trouble occurs in which part of a semiconductor element such as a TFT or a capacitor included in one pixel.

  SUMMARY An advantage of some aspects of the invention is that it provides an electro-optical device that can determine whether each pixel is good or bad, and an electronic apparatus including the electro-optical device. To do.

  In order to solve the above problems, the electro-optical device of the present invention corresponds to a plurality of scanning lines and a plurality of data lines intersecting each other on the substrate, and the intersection of the plurality of scanning lines and the plurality of data lines. A plurality of pixel portions arranged in a matrix and first and second terminals, and a potential of a potential signal supplied to the first terminal and a potential signal supplied to the second terminal When the potential signal supplied to the first terminal is low, the potential of the first terminal is lowered, and when the potential signal supplied to the first terminal is high, the potential is An amplifier that outputs the first terminal with a higher potential and a supply that supplies a reference potential to one of the first and second terminals and reads and supplies a potential signal input to the pixel portion to the other And at least one terminal of the first and second terminals It is electrically connected, comprising a first electrode made of the first metal film, a second electrode made of the first dielectric film and the second metal film and a capacitor which are laminated in this order.

  According to the electro-optical device of the present invention, during the operation, an image signal is supplied to each pixel unit via the data line by, for example, an X-driver circuit. At the same time, a scanning signal is supplied to each pixel unit via the scanning line by the Y-driver circuit. For example, a pixel switching thin film transistor provided for each pixel portion has a gate connected to a scanning line, and selectively supplies an image signal to a pixel electrode in accordance with the scanning signal. Accordingly, for example, by driving an electro-optical material such as liquid crystal sandwiched between the pixel electrode and the counter electrode in each pixel portion, active matrix driving is possible. At this time, the storage capacitor improves the potential holding characteristic in the pixel portion, and the display can have high contrast.

  In particular, the invention comprises a supply means and an amplifier.

  The supply means supplies a reference potential to one of the first and second terminals of the amplifier during an inspection performed prior to the operation of the electro-optical device, and is input (or written) to, for example, a pixel electrode in the pixel portion. Read out and supply the potential signal. Such inspection is preferably performed before the electro-optical device is bonded to the pair of substrates, for example, when a substrate called an element array substrate, an element substrate, or a TFT array substrate is completed. Is done. Here, the potential signal read from the pixel portion is a signal reflecting the quality of the pixel portion. More specifically, for example, an inspection signal is supplied to the pixel portion in advance prior to the inspection, and a signal having a potential that varies from the potential of the inspection signal according to the quality of the pixel portion is output as a potential signal. “Possibility of the pixel portion” means whether or not the pixel portion has a defect, and the level relationship between the reference potential and the potential of the potential signal varies depending on the defect occurring in the pixel portion.

  The amplifier compares the potential between the potential signal supplied to the first terminal and the potential signal supplied to the second terminal, and the first signal is supplied when the potential signal supplied to the first terminal is low. When the potential of the terminal is lowered and the potential signal supplied to the first terminal is high, the potential of the first terminal is made higher and output. That is, at the time of this inspection, for example, when the potential of the potential signal output from the pixel unit and supplied to the first terminal is slightly lower than the reference potential supplied to the second terminal, the reference In order that the potential of the potential signal supplied to the first terminal lower than the potential is not obscured by noise applied to the wiring such as the data line, the amplifier uses the potential signal supplied to the first terminal. A low potential signal with a lower potential is output. On the other hand, for example, when the potential of the potential signal output from the pixel portion and supplied to the first terminal has a slightly higher potential than the reference potential supplied to the second terminal, it is higher than the reference potential. The amplifier has a potential higher than that of the potential signal supplied to the first terminal so that the high potential of the potential signal supplied to the first terminal is not obscured by noise applied to the wiring such as the data line. Outputs a high potential signal.

  Further, in the present invention, in particular, a capacitor is electrically connected to at least one of the first and second terminals. Therefore, it is possible to reduce the amount of pushdown generated in the reference potential or potential signal of the first and second terminals (that is, the amount of potential fluctuation due to field through). Thereby, it is possible to prevent the amplifier from malfunctioning and to obtain an accurate comparison result.

  In addition, in the present invention, in particular, the capacitance is obtained by laminating the first electrode made of the first metal film, the first dielectric film, and the second electrode made of the second metal film in this order. It has a MIM (Metal Insulator Metal) structure. In the MIM structure, the capacitor can be formed with a simple structure as compared with the case where the capacitor electrode is formed of, for example, a polysilicon film. Therefore, it is possible to realize the addition of capacitance to the terminal without complicating the structure of the amplifier.

  In one aspect of the electro-optical device of the present invention, each of the plurality of pixel portions includes a lower electrode made of the same film as the first metal film and the same film as the first dielectric film on the substrate. A storage capacitor in which a second dielectric film and an upper electrode made of the same film as the second metal film are stacked in this order.

  According to this aspect, the first electrode constituting the capacitor is formed of the same film as the lower electrode, and the first dielectric film constituting the capacitor is the same film as the second dielectric film, and the capacitor Is formed from the same film as the upper electrode. Here, the “same film” means films formed on the same occasion in the manufacturing process and are the same type of film. Note that the phrase “same film” does not mean that the film is continuous as a single film, but basically a film part of the same film that is separated from each other is sufficient. It is. Therefore, the first electrode, the first dielectric film, and the second electrode constituting the capacitor can be formed on the same occasion as the formation of the lower electrode, the second dielectric film, and the upper electrode, respectively. That is, the capacitor can be formed without causing a complicated laminated structure on the substrate and a complicated manufacturing process.

  Note that the storage capacitor improves, for example, the potential holding characteristic of the pixel electrode constituting the pixel portion, and the display can have high contrast.

  In another aspect of the electro-optical device according to the aspect of the invention, the capacitor is electrically connected only to a terminal to which the reference potential is supplied among the first and second terminals.

  According to this aspect, since the capacitor is connected to the terminal to which the reference potential is supplied, the amount of pushdown generated at this terminal can be reduced, and fluctuations in the reference potential at this terminal can be suppressed and the amplifier can accurately A comparative result can be obtained. Furthermore, since the capacitor is electrically connected only to the terminal to which the reference potential is supplied among the first and second terminals, for example, the capacitor is electrically connected to both the first and second terminals. The number of capacitors to be formed can be halved as compared with the case of the case. Therefore, an accurate comparison result can be obtained from the amplifier with little or no decrease in the yield of the electro-optical device due to manufacturing variations in capacitance.

  An electronic apparatus of the present invention comprises the above-described electro-optical device of the present invention in order to solve the above problems.

  According to the electronic apparatus of the present invention, since it includes the electro-optical device of the present invention described above, a projection display device, a mobile phone, an electronic notebook, a word processor, a viewfinder type, or a monitor capable of high-quality display. Various electronic devices such as a direct-view video tape recorder, a workstation, a videophone, a POS terminal, and a touch panel can be realized. Further, as the electronic apparatus of the present invention, for example, an electrophoretic device such as electronic paper can be realized.

  In order to solve the above problems, a method of manufacturing an electro-optical device according to the present invention includes a step of forming a plurality of scan lines and a plurality of data lines intersecting each other on a substrate, and the plurality of scans on the substrate. Forming a plurality of pixel portions in a matrix form corresponding to intersections of the lines and the plurality of data lines, and having first and second terminals on the substrate and supplied to the first terminals If the potential signal supplied to the first terminal is low, the potential of the first terminal is set lower than that of the potential signal supplied to the second terminal. A step of forming an amplifier for outputting the first terminal with a higher potential when the potential signal supplied to the first terminal is high; and the first and second on the substrate. A reference potential is supplied to one of the terminals and the other is input to the pixel portion Forming a supply means for reading out and supplying a signal, and electrically connecting to at least one of the first and second terminals on the substrate and from the first metal film Forming a capacitor by stacking a second electrode composed of a first electrode, a first dielectric film, and a second metal film in this order, and forming the capacitors by the step of forming the capacitors. A storage electrode by stacking a lower electrode made of the same film as the first metal film, an upper electrode made of the same film as the first dielectric film and the second metal film in this order. To do.

  According to the method for manufacturing an electro-optical device of the present invention, the above-described electro-optical device of the present invention can be manufactured. In particular, since a capacitor is electrically connected to at least one of the first and second terminals, the amount of pushdown generated in the reference potential or potential signal of the first and second terminals is reduced. can do. Furthermore, the first electrode, the first dielectric film and the second electrode constituting the capacitor are formed on the same occasion as the formation of the lower electrode, the second dielectric film and the upper electrode, respectively. Capacitance can be formed without complicating the structure or manufacturing process.

  The operation and other advantages of the present invention will become apparent from the best mode for carrying out the invention described below.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, a driving circuit built-in type TFT active matrix driving type liquid crystal device, which is an example of the electro-optical device of the present invention, is taken as an example.

(First embodiment)
The liquid crystal device according to the first embodiment will be described with reference to FIGS.

  First, the overall configuration of the liquid crystal device according to the present embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view showing the configuration of the liquid crystal device according to this embodiment, and FIG. 2 is a cross-sectional view taken along the line H-H 'in FIG.

  1 and 2, in the liquid crystal device according to the present embodiment, a TFT array substrate 10 and a counter substrate 20 are arranged to face each other. A liquid crystal layer 50 is sealed between the TFT array substrate 10 and the counter substrate 20, and the TFT array substrate 10 and the counter substrate 20 are provided with a sealing material 52 provided in a seal region positioned around the image display region 10a. Are bonded to each other.

  In FIG. 1, a light-shielding frame light-shielding film 53 that defines the frame area of the image display region 10a is provided on the counter substrate 20 side in parallel with the inside of the seal region where the sealing material 52 is disposed. An X driver circuit 101 and an external circuit connection terminal 102 are provided along one side of the TFT array substrate 10 in a region located outside the seal region where the seal material 52 is disposed in the peripheral region. A sampling circuit 77 is provided inside the seal region along one side so as to be covered with the frame light-shielding film 53. The Y driver circuit 104 is provided so as to be covered with the frame light shielding film 53 inside the seal region along two sides adjacent to the one side. On the TFT array substrate 10, vertical conduction terminals 106 for connecting the two substrates with the vertical conduction material 107 are arranged in regions facing the four corner portions of the counter substrate 20. Thus, electrical conduction can be established between the TFT array substrate 10 and the counter substrate 20.

  On the TFT array substrate 10, lead wirings 90 are formed for electrically connecting the external connection terminals 102 to the X driver circuit 101, the Y driver circuit 104, the vertical conduction terminal 106, and the like.

  In FIG. 2, on the TFT array substrate 10, a laminated structure in which pixel switching TFTs as drive elements, wiring lines such as scanning lines and data lines are formed is formed. In the image display area 10a, a pixel electrode 9a is provided in an upper layer of wiring such as a pixel switching TFT, a scanning line, and a data line. On the other hand, a light shielding film 23 is formed on the surface of the counter substrate 20 facing the TFT array substrate 10. A counter electrode 21 made of a transparent material such as ITO (Indium Tin Oxide) is formed on the light shielding film 23 so as to face the plurality of pixel electrodes 9a. Further, the liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several types of nematic liquid crystals are mixed, and takes a predetermined alignment state between the pair of alignment films.

  Although not shown here, in addition to the X driver circuit 101 and the Y driver circuit 104, the TFT array substrate 10 will be described later for inspecting the quality, defects, and the like of the liquid crystal device during manufacturing or at the time of shipment. Thus, a precharge and reference circuit 13 constituting a part of the “supplying unit” according to the present invention, a differential amplifier circuit 4a as an example of the “amplifier” according to the present invention, and the like are formed.

  Next, the circuit configuration of the liquid crystal device according to the present embodiment will be described with reference to FIGS. FIG. 3 is a block diagram showing the main circuit configuration of the liquid crystal device according to this embodiment. FIG. 4 is a circuit diagram showing an electrical configuration of the pixel portion.

  In FIG. 3, the liquid crystal device according to the present embodiment includes a pixel unit 2a, a sampling circuit 77, a Y driver circuit 104, an X driver circuit 101, a display data readout circuit 4, a transmission gate 60, a precharge and a reference on a TFT array substrate 10. A circuit 13 is provided.

  The pixel portion 2a is two-dimensionally arranged in a matrix of n rows × m columns in the image display area 10a. Here, m and n are natural numbers, respectively. More specifically, as shown in FIG. 3, the pixel unit 2 a includes the first column, the second column,..., The m-th column from the right side in the image display region 10 a, the first row, the second column from the upper side. Are arranged in a matrix of rows,..., N-th row. That is, the pixel portion 2a which is a unit display element is provided corresponding to the intersection of the data line S (ie, S1, S2,... Sm) and the scanning line G (ie, G1, G2,..., Gn). It has been.

  As shown in FIG. 4, the pixel section 2a includes a TFT 30, a liquid crystal capacitor Clc, and an additional capacitor Cs as an example of the “storage capacitor” according to the present invention.

  The liquid crystal capacitance Clc is a capacitance due to the pixel electrode 9a, the counter electrode 21, and the liquid crystal layer 50 (see FIG. 2).

  The additional capacitor Cs is electrically connected in parallel to the liquid crystal capacitor Clc and has a MIM (Metal Insulator Metal) structure as will be described later.

  The TFT 30 has a source terminal s electrically connected to the data line S and a gate terminal g electrically connected to the scanning line G. The TFT 30 is switched on and off by a predetermined voltage signal supplied from the Y driver circuit 104.

  The drain of the TFT 30 is electrically connected to one end of each of the liquid crystal capacitor Clc and the additional capacitor Cs, and the other end of the additional capacitor Cs is electrically connected to the common fixed potential CsCOM. When a predetermined voltage signal is input to the gate terminal g of the TFT 11 and the TFT 30 is turned on, the voltage applied to the source terminal s of the TFT 30 electrically connected to the data line S is applied to the liquid crystal capacitor Clc and the additional capacitor Cs. The supplied predetermined potential is maintained. Thereby, it is possible to hold the image signal (or also referred to as “pixel signal”) supplied to the pixel unit 2a for a long time when image display is performed.

  In FIG. 3 again, the sampling circuit 77 includes a plurality of sampling switches 77s, and in response to the output timing signal from the X driver circuit 101, the image signal input from the video signal line 7 is converted into the data lines S1, S2,. ..., supplied to Sm. The video signal line 7 includes a signal line that supplies a signal to an odd column of the plurality of pixel portions 2a in a matrix and a signal line that supplies a signal to the even column, and are electrically connected to terminals ino and ine, respectively. Has been. The data lines S1, S2,..., Sm are electrically connected to the n pixel units 2a in each column, and the image signals from the data lines S1, S2,. The pixel portion 2a (more specifically, the liquid crystal capacitance Clc and the additional capacitance Cs included in each pixel portion 2a) is input, that is, written.

  As shown in FIG. 3, the video signal line 7 is provided with a differential amplifier 110 including a current mirror amplifier. The differential amplifier 110 prevents a difference between a high level signal (hereinafter referred to as “HIGH signal”) and a low level signal (hereinafter referred to as “LOW signal”) from being reduced due to a capacitance component of the video signal 7 itself. Therefore, the HIGH signal and the LOW signal are clarified and the output signals outo and oute are output at high speed and with high accuracy.

  The display data readout circuit 4 is provided on the TFT array substrate 10 for the inspection of the pixel portion 2a, and a plurality of pixel portions provided in the image display region 10a when viewed in plan on the TFT array substrate 10. Between the 2a and the display data reading circuit 4, there is provided a transmission gate 60 that constitutes a part of the “supply means” according to the present invention.

  The display data readout circuit 4 has a plurality of differential amplifier circuits 4a, and serves as a reference for inspection and potential read from the pixel portion to be inspected at the two input terminals se and so of the differential amplifier circuit 4a. A reference potential (also referred to as “reference”) is applied.

  Here, the differential amplifier circuit included in the display data reading circuit will be described with reference to FIGS. FIG. 5 is a circuit diagram showing the electrical configuration of the differential amplifier circuit.

  In FIG. 5, a differential amplifier circuit 4a is a cross-coupled differential amplifier circuit including p-channel Tr1 and Tr2 and n-channel Tr3 and Tr4. More specifically, a series circuit in which Tr1 and Tr2 are electrically connected in series and a series circuit in which Tr3 and Tr4 are electrically connected in series are electrically connected in parallel. The gates of Tr1 and Tr3 are electrically connected to the terminal So. The gates of Tr2 and Tr4 are electrically connected to the terminal Se. The connection points of the sources and drains of the transistors Tr1 and Tr2 are electrically connected to the power supply terminal sp, and the connection points of the sources and drains of the transistors Tr3 and Tr4 are electrically connected to the power supply terminal sn.

  As shown in FIG. 3 again, the terminals se and so are electrically connected to the se wiring 4f and the so wiring 4g that supply potentials to these terminals, respectively. One of the se wiring 4f and the so wiring 4g is supplied with a signal potential read from the pixel portion 2a to be inspected, and the other is supplied with a reference. A power supply voltage VDD is supplied to the power supply terminal sp via the power supply transistor 4d, and a ground potential is supplied to the power supply terminal sn from the reference potential point via the power supply transistor 4e. The power supply transistors 4d and 4e are controlled to be turned on and off by drive signals SAp-ch and SAn-ch supplied via terminals 4b and 4c, respectively.

  Note that a pull-up circuit 31 is electrically connected to the terminal 4b. FIG. 6 is a circuit diagram showing an electrical configuration of the pull-up circuit. As shown in FIG. 6, the pull-up circuit 31 includes a p-channel transistor 131 whose gate is grounded. The transistor 31 supplies the power supply VDD to the terminal 4b.

  In FIG. 5, the differential amplifier circuit 4a configured in this way raises the potential supplied to the terminals se and so to one of the power supply potential and the other to the potential of the reference potential point (for example, ground potential). . For example, when a potential slightly higher than the terminal so is supplied to the terminal se, the transistor Tr4 is turned on first among the transistors Tr1 to Tr4. Since the transistor Tr4 is turned on, the potential of the terminal so drops to the low ground potential of the terminal sn. Then, since the terminal so is lowered to the low ground potential of the terminal sn, the transistor Tr1 whose gate end is electrically connected to the terminal so is turned on. As a result, the terminal se rises to the high power supply voltage VDD of the power supply terminal sp.

  As described above, the differential amplifier 4a functions so as to increase the higher potential among the potentials applied to the terminals se and so, and lower the lower potential.

  In FIG. 3 again, the transmission gate 60 is constituted by transistors 60s provided corresponding to the data lines S1, S2,... Sm. The so wiring 4g electrically connected to the terminal so of the differential amplifier 4a is electrically connected to the source of the transistor 60s, and the gate of the transistor 60s is electrically connected to the control terminal 9b. The transistor 60s is turned on by a HIGH connection control signal input via the control terminal 9b, and a test circuit provided outside the liquid crystal device is connected to the data lines S1, S2,. ing.

  The control terminal 9b is electrically connected to the pull-down circuit 35. FIG. 7 is a circuit diagram showing an electrical configuration of the pull-down circuit. As shown in FIG. 7, the pull-down circuit 35 includes a transistor 135. By the pull-down circuit 35, the control terminal 9b is normally kept LOW. As a result, normally, the transistor 60s is off, and the display data read circuit 4 is disconnected from each data line S. At the time of testing (or at the time of inspection), a high connection control signal is supplied to the connection control terminal 9b, so that the transistor 60s is turned on and the display data reading circuit 4 is electrically connected to the data line S. It has become. In FIG. 3, the pull-down circuits 32, 33, and 34 are configured similarly to the pull-down circuit 35.

  In FIG. 3, a precharge / reference circuit 13 and an equalize circuit 8 are also provided between the plurality of pixel portions 2 a and the display data readout circuit 4. The equalize circuit 8 constitutes an example of the “supply means” according to the present invention, together with the precharge and reference circuit 13 and the transmission gate 60 described above.

  The precharge and reference circuit 13 includes two transistors 3ce and 3co corresponding to each differential amplifier circuit 4a. The transistor 3co has a source electrically connected to the voltage application terminal 3a and a drain electrically connected to the terminal so of the differential amplifier circuit 4a via the so wiring 4g. The transistor 3ce has a source electrically connected to the voltage application terminal 3a and a drain electrically connected to the terminal se of the differential amplifier circuit 4a via the se wiring 4f. A precharge voltage is supplied to the voltage application terminal 3a. The precharge voltage is also used as a reference signal as it is.

  The gates of the transistors 3ce and 3co are both electrically connected to the control terminal 3b, and a precharge control signal is input to the control terminal 3b. The HIGH precharge control signal is applied to the gates of the transistors 3co and 3ce via the control terminal 3b, so that the transistors 3co and 3ce are turned on, and the precharge voltage supplied to the control terminal 3a is set to the se wiring 4f and It is supplied to the so wiring.

  That is, the se wiring 4f electrically connected to the terminal se of the differential amplifier circuit 4a is used as a reference wiring for maintaining the precharge voltage from the outside as a reference voltage and supplying it to the terminal se.

  That is, in the liquid crystal device according to the present embodiment, the inspection wiring and the source wiring that are electrically connected to one terminal of the differential amplifier circuit 4a are connected, and one data is output by one differential amplifier circuit 4a. Inspection of the pixel portion electrically connected to the line S is possible. Note that the number of differential amplifier circuits 4a is the same as the number m of columns of the plurality of pixel portions 4a arranged in a matrix of n rows × m columns.

  In the precharge period, a precharge voltage is supplied to the so wiring 4g and the se wiring 4f. The precharge process is for applying a precharge voltage to the data line S, the so wiring 4g, and the se wiring 4f in order to inspect various characteristics. Various voltages can be selected as the precharge voltage. For example, the power supply voltage VDD or the ground potential may be used, or an intermediate potential thereof may be used. In this embodiment, the precharge voltage is set to an intermediate potential, for example.

  In FIG. 3, the equalize circuit 8 has n transistors 8a whose sources and drains are electrically connected to the so wiring 4g and the se wiring 4f, respectively. The transistor 8a has a gate electrically connected to the control terminal 8b and is turned on by a HIGH equalization control signal from the control terminal 8b so that the so wiring 4g and the se wiring 4f have the same potential. .

  By the way, in the inspection of the pixel portion of the liquid crystal device according to the present embodiment, as described later, for example, LOW or HIGH is written in each pixel portion 2a, and the signal written in the pixel portion 2a is read to read the differential amplifier circuit 4a. To the terminal so. On the other hand, a reference is given to the terminal se of the differential amplifier circuit 4a. As described above, the differential amplifier circuit 4a reduces the low level potential of the two inputs (that is, the inputs to the terminal so and the terminal se) to the ground potential and raises the high level potential to the power supply potential. Thus, the subtle level difference between the two inputs is increased to facilitate the determination of the level of the two inputs. However, the differential amplifier circuit 4a malfunctions due to the difference in capacitance between the wirings electrically connected to the terminals se and so of the differential amplifying circuit 4a (that is, electric capacitance or wiring capacitance), and the pixel portion is defective. An error may occur in the determination.

  Next, the malfunction of the above-described differential amplifier circuit will be described with reference to FIGS. FIG. 8 is a timing chart for explaining a malfunction of the differential amplifier circuit.

  FIG. 8 shows the precharge control signal PCG and the equalize control signal EQ, the scanning signal G1 supplied to the scanning line G1, the potential of the terminal so, and the potential of the terminal se.

  3 and 8, before supplying the signal potential from the pixel portion 2a to the terminal so of the differential amplifier circuit 4a, the precharge voltage is supplied to the se wiring 4g and the data line S which are inspection wirings, and the terminal se and so are set to the same potential. For this precharge and equalization processing, a HIGH precharge control signal PCG is applied to the gates of the transistors 3ce and 3co, and a HIGH equalize control signal EQ is applied to the gate of the transistor 8a.

  Immediately before supplying the signal potential from the pixel portion 2a to the terminal so of the differential amplifier circuit 4a, the precharge signal PCG and the equalization control signal EQ are switched from HIGH to LOW in order to stop the precharge and equalization processing (FIG. 8). With this switching from HIGH to LOW, push-down (that is, potential fluctuation or voltage drop due to field-through) occurs at the terminals so and se due to the parasitic capacitance of the transistors 3co, 3ce, and 8a.

  At the time of inspection of the pixel portion 2a, the transistor 60s is on, and the so wiring 4g and the data line S are electrically connected to the terminal so of the differential amplifier circuit 4a. On the other hand, the only wiring that is electrically connected to the terminal se of the differential amplifier circuit 4a is the se wiring 4f. The wiring capacity of the so wiring 4g and the data line S is sufficiently larger than the wiring capacity of only the se wiring 4f. For this reason, as shown in FIG. 8, at the timing when the precharge control signal PCG and the equalize control signal EQ are switched from HIGH to LOW, the pushdown generated at the terminal so (refer to the pushdown amount Δ1 in FIG. 8) is relatively On the other hand, there is a high possibility that a relatively large pushdown (see pushdown amount Δ2 in FIG. 8) will occur at the terminal se.

  When HIGH is supplied to the scanning line G1 and the signal of the pixel portion 2a is transferred to the terminal so, the potential of the terminal so changes in accordance with the potential written in the pixel portion 2a. In FIG. 8, when HIGH is written in the pixel portion 2a, the potential of the terminal so rises slightly (see the solid line portion indicating the potential of the terminal so in FIG. 8). On the other hand, when LOW is written in the pixel portion 2a, the potential of the terminal so slightly decreases (see the dashed line indicating the potential of the terminal so in FIG. 8). The differential amplifier circuit 4a compares the potentials of the terminals so and se. As shown in FIG. 8, if the push-down of the terminal se is relatively large and the potential of the terminal se (that is, the reference) becomes lower than the potential of the terminal so when LOW is written in the pixel portion 2a, In the amplifier circuit 4a, the terminal so always becomes the power supply voltage VDD regardless of the signal level written in the pixel portion 2a. For this reason, the quality of the pixel unit 2a cannot be determined.

  Therefore, as shown in FIG. 3, in this embodiment, in particular, each terminal se and the reference of the terminal se after pushdown are set higher than the potential of the terminal so when LOW is written in the pixel portion. A capacitor 4h is electrically connected between the reference potential (ie, ground potential) point.

  Since the liquid crystal device according to the present embodiment is configured as described above, before the TFT array substrate 10 and the counter substrate 20 are bonded to each other and the liquid crystal is sealed in the manufacturing process, the electrical characteristics of the plurality of pixel units 2a are obtained. The property can be evaluated or inspected. As a defect to be inspected for electrical characteristics, for example, a defect that the pixel unit 2a is fixed to LOW due to leakage of the additional capacitor Cs that is a data holding capacitor of each pixel unit 2a (hereinafter referred to as “LOW”). There is a defect in which the pixel portion 2a is fixed to HIGH due to leakage between the source and drain of the TFT as a switching element (hereinafter referred to as “HIGH fixing defect”).

  Next, the inspection and operation of the liquid crystal device according to the present embodiment will be described with reference to the drawings.

  Before describing the inspection of the pixel portion of the liquid crystal device in the manufacturing process, first, an operation when the liquid crystal device according to the present embodiment performs normal image display will be described with reference to FIG.

  In FIG. 3, first, in two video signal lines 7, odd-numbered and even-numbered image signals are respectively input to input terminals ine and ino of the video signal line 7. Each image signal is supplied to each data line S via a plurality of sampling switches 77 s constituting the sampling circuit 77 in accordance with a column selection signal (ie, output timing signal) from the X driver circuit 101. .

  The image signal supplied to each data line S is the pixel portion 2a (more specifically, the liquid crystal capacitance Clc and the additional capacitance Cs) in the row selected when the scanning line G from the Y driver circuit 104 becomes HIGH. Is written to. That is, in the selected scanning line G, the image signal supplied to the data line S is supplied and held as a display image signal in the corresponding pixel portion 2a. By performing this operation in, for example, row order, a desired image is displayed in the image display area 10a of the liquid crystal device.

  The precharge and reference circuit 13 applies a precharge voltage Vpre to each data line S before the scanning line G becomes HIGH. The precharge voltage Vpre is supplied to the voltage application terminal 3 a of the precharge and reference circuit 13. The timing for supplying the precharge voltage Vpre is determined by a precharge control signal PCG given to the control terminal 3b.

  When an image is displayed as a liquid crystal device as a product or a prototype, the transistor 60s of the transmission gate 60 is off, and the display data reading circuit 4 does not operate and is not used.

  Next, the inspection procedure of the liquid crystal device according to the present embodiment will be described with reference to FIGS. FIG. 9 is a block diagram of the inspection system. FIG. 10 is a flowchart showing an example of the entire flow of inspection. FIG. 11 is a timing chart for explaining the read operation in step ST2 of FIG. FIG. 12 is an explanatory diagram showing a writing state of each pixel portion at the time of inspection.

  As shown in FIG. 9, the liquid crystal device 1 at the time of inspection (that is, the TFT array substrate 10 on which the plurality of pixel portions 2a and the various circuits described above are formed before being bonded to the counter substrate 20), and pixel data Is electrically connected to the test device 15 capable of writing and reading the data via the connection cable 16. The connection cable 16 includes the terminals ino and ine of the video signal line 7 of the liquid crystal device 1, the terminals 4 b and 4 d of the signal line of the display data reading circuit 4, the terminals 3 a and 3 b of the precharge and reference circuit 13, etc. Electrical connection is made (see FIG. 3).

  By supplying a predetermined voltage from the test device 15 to each terminal in a predetermined order to be described later, the electrical characteristics of the plurality of pixel portions 2a can be inspected. Below, the procedure for inspecting whether or not there is a LOW fixed defect among the above-described defects will be described as the contents of the inspection.

  As shown in FIG. 10, first, by a writing process, a predetermined pixel signal (or pixel data) is input from the input terminals ino and ine of the video signal line 7 to each pixel unit 2a which is a cell (step ST1). . The inspection of the pixel portion 2a is performed by determining whether or not the pixel portion 2a in the column to be inspected is normal with respect to the pixel portion 2a in the reference column. Each timing signal shown in FIG. 11 is generated by the test apparatus 15 and supplied to each terminal.

  In this embodiment, the reference is supplied from the outside, and it is not necessary to write the reference to the pixel unit 2a. Each pixel portion 2a is written for inspection. That is, for example, in the case of inspecting a LOW fixing defect, as shown in FIG. 12, all the scanning lines G are turned on and HIGH is written in all the pixel portions 2a. FIG. 12 shows that the pixel signal written to each pixel unit 2a of n rows × m columns is HIGH (indicated by “H” in FIG. 12).

  In addition, when LOW is written in each pixel portion 2a, it is possible to inspect a HIGH fixing defect. Hereinafter, an example will be described in which HIGH is written in all the pixel portions 2a and a plurality of pixel portions 2a are inspected, but only a part of the pixel portions may be inspected. After the image signal is written, the gate of the scanning line G is turned off.

  At this time, the drive signal SAp-ch is the power supply potential VDD, the drive signal SAn-ch is the ground potential, and each differential amplifier circuit 4a of the display data read circuit 4 is in a non-operating state.

  Next, as shown in FIG. 10, pixel signals are read out by a reading process (step ST2). By supplying a high connection control signal TE (see FIG. 11) to the connection control terminal 9b, each transistor 60s of the transmission gate 60 is turned on. Thereby, the transistor 60s is turned on, and the data lines S1, S2,..., Sm and each of the so wirings 4g are electrically connected. Thus, the written pixel signal is read for each row and supplied to the display data reading circuit 4.

  Immediately before reading out such pixel signals, precharge and equalization processing are performed. That is, after the above-described predetermined pixel signal is written to all the pixel portions 2a, first, the precharge control signal PCG (see FIG. 11) supplied to the control terminal 3b of the precharge and reference circuit 13 becomes HIGH.

  As shown in FIG. 11, in order to secure the data holding time, the precharge control signal PCG supplied to the terminal 3a of the precharge and reference circuit 13 becomes HIGH only for the data holding time t1.

  Thus, the precharge voltage Vpre supplied to the voltage application terminal 3a is applied to the so wiring 4g and each source wiring S through the transistor 3co, and is applied to the se wiring 4f through the transistor 3ce. In the se wiring 4f, when the differential amplifier circuit 4a operates, the precharge voltage Vpre functions as a reference voltage. For example, an intermediate potential is selected as the precharge voltage Vpre.

  The precharge voltage Vpre of each data line S is set to an intermediate potential between HIGH and LOW, and the common fixed potential CsCOM (see FIG. 4) is set to the LOW potential. The common fixed potential CsCOM is set to the LOW potential because when the additional capacitor Cs, which is a data holding capacitor, has a leakage failure, the common fixed potential CsCOM at the leak destination becomes the LOW potential. This is to make it lower. Then, a slightly long time is set for the first precharge period so that a voltage change due to a leak failure appears.

  Further, as shown in FIG. 11, when the precharge voltage Vpre and the reference are applied, the HIGH equalize control signal EQ is also supplied to the control terminal 8b, the transistor 8a of the equalize circuit 8 is also turned on, and the so wiring The 4g and se wiring 4f have the same potential. Thus, at this time, the data lines S and the terminals so and se of the differential amplifier circuit 4a are in an intermediate potential state.

  Next, immediately before the pixel signal is read, the precharge control signal PCG and the equalize control signal EQ are set to LOW to stop the precharge and reference processing. At this time, the gates of the transistors 3co, 3ce, and 8a change from HIGH to LOW, thereby causing pushdown.

  In the present embodiment, in particular, the capacitor 4h is connected to the terminal se, and the potential drop of the terminal se due to pushdown is sufficiently suppressed. As a result, the push-down amount at the terminal se (that is, the potential drop amount) and the push-down amount at the terminal so are almost or completely the same in practice. Note that the amount of potential drop at the terminals so and se due to the push-down is sufficiently small, and is not shown in FIG.

  Next, as shown in FIG. 11, after the data holding time t <b> 1 has elapsed, the scanning line G <b> 1 is set to HIGH and pixel signal readout is started. At this time, the drive signal SAp-ch is the power supply potential VDD, the drive signal SAn-ch is the ground potential, and each differential amplifier circuit 4a is not yet operated.

  When the scanning line G1 is set to HIGH, pixel signals are simultaneously output from the pixel units 2a connected to the scanning line G1. That is, the charges written and held in the pixel portion 2a (specifically, the additional capacitor Cs) move all at once to the corresponding data line S. When HIGH is written in each pixel portion 2a and the pixel portion 2a is normal, the potential of each data line S and so wiring 4g slightly increases as shown by the solid line in FIG. If there is a leak in the additional capacitor Cs and the pixel signal of the pixel unit 2a changes to LOW, the potential of each data line S slightly drops as shown by the broken line in FIG. . On the other hand, as shown in FIG. 11, the potential of the terminal se to which the reference is supplied is almost the intermediate potential because the push-down amount is sufficiently small.

  As shown in FIG. 11, after setting the scanning line G1 to HIGH, the connection control signal TE to the connection control terminal 9b is set to LOW, and the transistor 60s of the transmission gate 60 is turned off for a predetermined time t2. That is, at the predetermined time t2, the connection control signal TE, the precharge control signal PCG, and the equalize control signal EQ are all LOW, and the transistors 9a, 3ce, 3co, and 8a are all turned off. The wiring 4f is in a floating state. Therefore, the intermediate potential of the se wiring 4f and the slightly increased potential of the so wiring 4g are maintained in the se wiring 4f and the so wiring 4g, respectively, and are not affected by other wiring such as the data line S.

  As shown in FIG. 11, the drive signal SAn-ch is changed from LOW to HIGH at the same time as or before or after the connection control signal TE is changed to LOW, and the drive signal SAp-ch is changed from HIGH to LOW.

  When the pixel unit 2a is normal, the drive signal SAn-ch becomes HIGH, so that the ground potential is applied to the power supply terminal sn of the differential amplifier circuit 4a, and becomes a lower potential among the terminals se and so. The terminal se that is present falls to the ground potential (see the solid line of the terminal se in FIG. 11). Further, when the drive signal SAp-ch becomes LOW, the power supply voltage VDD is applied to the power supply terminal sp of the differential amplifier circuit 4a, and the terminal so that has a higher potential among the terminals se and so has the power supply voltage VDDD. (See the solid line of the terminal so in FIG. 11).

  When the LOW fixing defect occurs in the pixel portion 2a, the drive signal SAn-ch becomes HIGH, so that the ground potential is applied to the power supply terminal sn of the differential amplifier circuit 4a. The terminal so that is at a low potential falls to the ground potential (see the broken line of the terminal so in FIG. 11). In addition, when the drive signal SAp-ch becomes LOW, the power supply voltage VDD is applied to the power supply terminal sp of the differential amplifier circuit 4a, and the terminal se having a higher potential among the terminals se and so becomes the power supply voltage VDD. (See the broken line of the terminal se in FIG. 11). That is, the level relationship between the potentials of the terminals so and se is opposite to the level relationship when the pixel portion 2a is normal.

  Next, as shown in FIG. 10 again, the potentials determined at the terminals se and so are compared (step ST3). That is, when the potentials of the terminals so and se are determined to be LOW or HIGH, the connection control signal TE is set to HIGH to turn on the transistor 60s of the transmission gate 60 in order to output the potential of the terminal so.

  The determined potential of the terminal so of the differential amplifier circuit 4a is supplied to the corresponding data line S from the so wiring 4g. The gates TG1 to TGm of each sampling switch 77s of the sampling circuit 77 are opened in order (that is, an output timing signal is supplied from the X driver circuit 101), and the pixel signal of each pixel unit 2a in the first row is supplied from the video signal line 7. Read in order and output to output terminals outo and oute.

  When the pixel signals of all the pixel portions electrically connected to the scanning line G1 are read, the scanning line G1 is changed from HIGH to LOW, the drive signal SAn-ch is changed from HIGH to LOW, and the drive signal SAp-ch is changed to LOW. To HIGH to stop the operation of the differential amplifier circuit 4a.

  Next, as shown in FIG. 11, the precharge control signal PCG and the equalize control signal EQ are set to HIGH to precharge all the data lines S. Note that the second and subsequent precharge times may not be as long as the first time. After the precharge operation (that is, after the precharge time has elapsed, the precharge control signal PCG and the equalize control signal EQ are changed from HIGH to LOW), the potential of the second scanning line G2 is changed to HIGH, thereby The TFT 30 of each pixel unit 2a in the second row is turned on. Thereafter, the readout operation described above is repeated for each scanning line G up to the pixel portion 2a electrically connected to the n-th scanning line Gn, and finally pixel signals are read from all the pixel portions 2a.

  The determined potentials of the terminals so and se are output from the output terminals outo and oute to the test apparatus 15. The test device 15 compares the pixel signal read in the reading process with the pixel signal written in the writing process. As shown in FIG. 11, when the pixel portion 2a is normal, HIGH is output to the output terminals outo and oute (see the solid lines of the output terminals outo and oute in FIG. 11). On the other hand, when a LOW fixing defect has occurred in the pixel portion 2a, LOW is output (see the broken lines of the output terminals outo and oute in FIG. 11). Therefore, the test apparatus 15 can determine whether or not a LOW fixing defect has occurred in the pixel portion 2a to be inspected.

  Next, as shown in FIG. 10, the test apparatus 15 identifies a pixel unit 2 a (or also referred to as “cell”) whose pixel signal read from the pixel unit 2 a to be inspected is not HIGH, and detects an abnormal pixel unit (or abnormal pixel unit). For example, a predetermined pixel unit number (or cell number) corresponding to each pixel unit is output so as to be displayed on a monitor screen (not shown) (step ST4).

  In this way, each differential amplifier circuit 4a can determine the quality of each pixel unit 2a by comparing the reference potential (ie, intermediate potential) applied from the outside with the potential of each data line S. To do.

  It is obvious that the HIGH fixed defect can be inspected by setting the reference to an intermediate potential and writing LOW in the pixel portion 2a to be inspected.

  As described above, in the manufacturing process of the liquid crystal device, before or after the TFT array substrate 10 in which the plurality of pixel portions 2a and the like are formed is bonded to the counter substrate 20, the quality of the plurality of pixel portions 2a is determined or detected. Therefore, the yield can be reduced and the manufacturing period can be shortened, the number of defective products can be reduced, and the cost can be reduced. In particular, in the case of a prototype, it can be expected to shorten the development period and the development cost. Furthermore, since the quality of the pixel portion 2a can be detected before the TFT array substrate 10 is bonded to the counter substrate 20, so-called repair is facilitated.

  In the present embodiment, in particular, a capacitor 4h is added to a terminal se to which a se wiring 4f to which a reference is supplied is electrically connected. Therefore, the pushdown amounts generated at the terminals se and so are almost equal to each other in practice. Accordingly, no malfunction occurs in the differential amplifier circuit 4a, and the inspection of the pixel portion 2a can be performed with high accuracy.

  Next, a specific configuration of the capacitor electrically connected to the terminal of the differential amplifier circuit will be described. Particularly in the present embodiment, the capacitor 4h (see FIG. 3) is formed at the same opportunity as the pixel portion 2a.

  First, a specific configuration of the pixel portion will be described with reference to FIGS. FIG. 13 and FIG. 14 are plan views showing a partial configuration related to the pixel portion on the TFT array substrate, which respectively correspond to a lower layer portion (FIG. 13) and an upper layer portion (FIG. 14) in a laminated structure to be described later. To do. FIG. 15 is a cross-sectional view taken along line AA ′ when FIGS. 13 and 14 are overlapped. In FIG. 15, the scale of each layer / member is different for each layer / member so that each layer / member can be recognized on the drawing.

  13 to 15, each circuit element of the pixel portion 2a described above with reference to FIGS. 3 and 4 is structured on the TFT array substrate 10 as a patterned conductive film. The TFT array substrate 10 is made of, for example, a glass substrate, a quartz substrate, an SOI substrate, a semiconductor substrate, and the like, and is disposed to face the counter substrate 20 made of, for example, a glass substrate or a quartz substrate. Each circuit element includes, in order from the bottom, a first layer including the scanning line G, a second layer including the TFT 30 and the like, a third layer including the data line S and the like, a fourth layer including the additional capacitor Cs, and the like. It consists of the 5th layer containing 9a etc. Further, the base insulating film 12 is provided between the first layer and the second layer, the first interlayer insulating film 41 is provided between the second layer and the third layer, the second interlayer insulating film 42 is provided between the third layer and the fourth layer, and the fourth layer. A third interlayer insulating film 43 is provided between the layer and the fifth layer, respectively, to prevent a short circuit between the aforementioned elements. Of these, the first to third layers are shown in FIG. 13 as lower layer portions, and the fourth to fifth layers are shown in FIG. 14 as upper layer portions.

(Structure of the first layer-scanning lines, etc.)
The first layer is composed of scanning lines G. The scanning line G is patterned into a shape including a main line portion extending along the X direction in FIG. 13 and a protruding portion extending in the Y direction in FIG. 13 where the data line S extends. Such a scanning line G is made of, for example, conductive polysilicon, and other refractory metals such as titanium (Ti), chromium (Cr), tungsten (W), tantalum (Ta), and molybdenum (Mo). It can be formed of a metal simple substance, an alloy, a metal silicide, a polysilicide, or a laminate thereof including at least one of

  The scanning line G is arranged on the lower layer side of the TFT 30 so as to include a region facing the channel region 1a ′, and is made of a conductive film.

(Second layer configuration-TFT, etc.)
The second layer is composed of the TFT 30. The TFT 30 has an LDD (Lightly Doped Drain) structure, for example, and includes a gate electrode 30a, a semiconductor layer 1a, and an insulating film 2 including a gate insulating film that insulates the gate electrode 30a from the semiconductor layer 1a. The gate electrode 30a is made of, for example, conductive polysilicon. The semiconductor layer 1a is made of, for example, polysilicon, and includes a channel region 1a ′, a low concentration source region 1b and a low concentration drain region 1c, and a high concentration source region 1d and a high concentration drain region 1e. The TFT 30 preferably has an LDD structure. However, the TFT 30 may have an offset structure in which no impurity is implanted into the low-concentration source region 1b and the low-concentration drain region 1c. It may be a self-aligned type in which a high concentration source region and a high concentration drain region are formed by implanting the film.

  The gate electrode 30a of the TFT 30 is electrically connected to the scanning line G through a contact hole 12cv formed in the base insulating film 12 in a part 30b. The base insulating film 12 is made of, for example, a silicon oxide film, and is formed on the entire surface of the TFT array substrate 10 in addition to the interlayer insulating function between the first layer and the second layer. Has a function of preventing changes in the element characteristics of the TFT 30 caused by the above.

  The TFT 30 according to the present embodiment is a top gate type, but may be a bottom gate type.

(3rd layer configuration-data lines, etc.)
The third layer includes a data line S and a relay layer 600.

  The data line S is formed as a three-layer film of aluminum, titanium nitride, and silicon nitride in order from the bottom. The data line S is formed so as to partially cover the channel region 1 a ′ of the TFT 30. For this reason, the channel region 1a ′ of the TFT 30 can be shielded from incident light from the upper layer side by the data line S that can be disposed close to the channel region 1a ′. The data line S is electrically connected to the high-concentration source region 1d of the TFT 30 through a contact hole 81 that penetrates the first interlayer insulating film 41.

  Note that a conductive film having a lower reflectance than the conductive film such as an Al film constituting the main body of the data line S may be formed on the side of the data line S facing the channel region 1a. In this way, the return light described above is reflected on the surface of the data line S facing the channel region 1a, that is, the lower layer side of the data line S, and multiple reflected light, stray light, etc. are generated from this. Can be prevented. Therefore, the influence of light on the channel region 1a can be reduced. Such a data line S has a reflectance higher than that of an Al film or the like constituting the body of the data line S on the surface of the data line S facing the channel region 1a, that is, the lower layer side of the data line S. A low material metal or a barrier metal may be formed. Note that chromium (Cr), titanium (Ti), titanium nitride (TiN), tungsten (W), or the like can be used as a metal having a lower reflectance than that of an Al film or the like, or as a barrier metal.

  The relay layer 600 is formed as the same film as the data line S. As shown in FIG. 13, the relay layer 600 and the data line S are formed so as to be separated from each other. The relay layer 600 is electrically connected to the high-concentration drain region 1 e of the TFT 30 through a contact hole 83 that penetrates the first interlayer insulating film 41.

  The first interlayer insulating film 41 is made of, for example, NSG (non-silicate glass). In addition, for the first interlayer insulating film 41, silicate glass such as PSG (phosphorus silicate glass), BSG (boron silicate glass), BPSG (boron phosphorus silicate glass), silicon nitride, silicon oxide, or the like can be used.

(Fourth layer configuration-additional capacity, etc.)
The fourth layer is composed of an additional capacitor Cs. The additional capacitor Cs includes a capacitor electrode 300 as an example of the “upper electrode” according to the present invention and a lower electrode 71 as an example of the “lower electrode” according to the present invention. ”Is disposed so as to face each other through a dielectric film 75 as an example.

  The extending portion of the capacitor electrode 300 is electrically connected to the relay layer 600 through a contact hole 84 that penetrates the second interlayer insulating film 42.

  Each of the capacitor electrode 300 and the lower electrode 71 is made of a metal film, for example, a metal simple substance including at least one of refractory metals such as Ti, Cr, W, Ta, and Mo, an alloy, a metal silicide, a polysilicide, These are laminated or preferably made of tungsten silicide.

  As shown in FIG. 14, the dielectric film 75 is formed in a non-opening region located in the gap of the opening region for each pixel when viewed in plan on the TFT array substrate 10, that is, almost formed in the opening region. It has not been. The dielectric film 75 is formed of a silicon nitride film or the like having a high dielectric constant without considering the transmittance. In addition to the silicon nitride film, for example, a single layer film or a multilayer film such as hafnium oxide (HfO 2), alumina (Al 2 O 3), tantalum oxide (Ta 2 O 5) or the like may be used as the dielectric film.

  The second interlayer insulating film 42 is made of, for example, NSG. In addition, for the second interlayer insulating film 42, silicate glass such as PSG, BSG, or BPSG, silicon nitride, silicon oxide, or the like can be used. The surface of the second interlayer insulating film 42 is subjected to a planarization process such as a chemical polishing process (CMP), a polishing process, a spin coat process, or a recess embedding process. Therefore, the unevenness caused by these elements on the lower layer side is removed, and the surface of the second interlayer insulating layer 42 is flattened. Such planarization may be performed on the surface of another interlayer insulating film.

(Fifth layer configuration-pixel electrode, etc.)
A third interlayer insulating film 43 is formed on the entire surface of the fourth layer, and a pixel electrode 9a is formed thereon as a fifth layer. The third interlayer insulating film 43 is made of, for example, NSG. In addition, the third interlayer insulating film 43 can be made of silicate glass such as PSG, BSG, or BPSG, silicon nitride, silicon oxide, or the like. The surface of the third interlayer insulating film 43 is subjected to a planarization process such as CMP similarly to the second interlayer insulating film 42.

  A pixel electrode 9a (indicated by a broken line 9a 'in FIG. 14) is disposed in each of the pixel areas partitioned vertically and horizontally, and the data lines S and the scanning lines G are arranged in a lattice pattern at the boundaries. (See FIGS. 13 and 14). The pixel electrode 9a is made of a transparent conductive film such as ITO.

  The pixel electrode 9a is electrically connected to the extending portion of the capacitor electrode 300 through a contact hole 85 that penetrates the interlayer insulating film 43 (see FIG. 15). Therefore, the potential of the capacitor electrode 300, which is the conductive film immediately below the pixel electrode 9a, is the pixel potential. Therefore, the pixel potential is not adversely affected by the parasitic capacitance between the pixel electrode 9a and the underlying conductive film during the operation of the liquid crystal device.

  Further, as described above, the extended portion of the capacitor electrode 300 and the relay layer 600 and the relay layer 600 and the high-concentration drain region 1e of the TFT 30 are electrically connected through the contact holes 84 and 83, respectively. ing. That is, the pixel electrode 9a and the high-concentration drain region 1e of the TFT 30 are relay-connected through the relay layer 600 and the extended portion of the capacitor electrode 300.

  An alignment film 16 that has been subjected to a predetermined alignment process such as a rubbing process is provided above the pixel electrode 9a.

  The above is the configuration of the pixel portion on the TFT array substrate 10 side.

  On the other hand, the counter substrate 20 is provided with a counter electrode 21 on the entire surface of the counter substrate 20, and an alignment film 22 is further provided thereon (under the counter electrode 21 in FIG. 15). As with the pixel electrode 9a, the counter electrode 21 is made of a transparent conductive film such as an ITO film. A light-shielding film 23 is provided between the counter substrate 20 and the counter electrode 21 so as to cover at least a region facing the TFT 30 in order to prevent generation of light leakage current in the TFT 30.

  A liquid crystal layer 50 is provided between the TFT array substrate 10 thus configured and the counter substrate 20. The liquid crystal layer 50 is formed by sealing liquid crystal in a space formed by sealing the peripheral portions of the substrates 10 and 20 with a sealing material. The liquid crystal layer 50 takes a predetermined alignment state by the alignment film 16 and the alignment film 22 that have been subjected to an alignment process such as a rubbing process in a state where an electric field is not applied between the pixel electrode 9 a and the counter electrode 21. It is like that.

  The configuration of the pixel portion described above is common to each pixel portion as shown in FIGS. Such pixel portions are periodically formed in the image display region 10a (see FIG. 1).

  Next, a specific configuration of the capacitor electrically connected to the terminal of the differential amplifier circuit will be described with reference to FIGS. FIG. 16 is a cross-sectional view including a capacitor electrically connected to a terminal of the differential amplifier.

  As described above with reference to FIG. 15, each pixel unit 2 a has a lower electrode 71 made of a metal film, a dielectric film 75, and a capacitor electrode 300 made of a metal film stacked in this order on the TFT array substrate 10. The additional capacitor Cs is provided. That is, the additional capacitor Cs has an MIM structure.

  As shown in FIG. 16, in the region where the capacitor 4h is formed, the base insulating film 12 and the interlayer insulating films 41 and 42 are stacked on the TFT array substrate 10 similarly to the region where the pixel portion 2a is formed. ing. A capacitor 4 h is formed on the interlayer insulating film 42.

  Particularly in this embodiment, the first electrode 4h1 constituting the capacitor 4h is formed of the same film as the lower electrode 71 (see FIG. 15) constituting the additional capacitor Cs, and the dielectric film 4h3 constituting the capacitor 4h is added. The second electrode 4h2 constituting the capacitor 4s is formed of the same film as the dielectric film 75 (see FIG. 15) constituting the capacitor Cs, and the second electrode 4h2 constituting the capacitor 4h. That is, the capacitor 4h has an MIM structure. Therefore, the capacity can be increased as compared with the case where the electrode having the capacity 4 h is formed of, for example, a polysilicon film. Accordingly, a sufficient capacitance can be formed to reduce the amount of pushdown generated in the signals output to the terminals so and se in a relatively small area on the TFT array substrate 10, so that the size of the TFT array substrate 10 can be reduced. The differential amplifier 4a can be prevented from malfunctioning with little or preferably no increase, and an accurate comparison result can be obtained.

  Further, as described above, since the capacitor 4h is formed of the same film as the additional capacitor Cs, the first electrode 4h1, the dielectric film 4h3, and the second electrode 4h2 constituting the capacitor 4h each constitute the additional capacitor Cs. The lower electrode 71, the dielectric film 75, and the capacitor electrode 300 can be formed at the same opportunity. That is, it is possible to form the capacitor 4h without complicating the laminated structure on the substrate and the manufacturing process.

  Further, when the capacitor 4h is formed with the MIM structure, the capacitor can be formed with a simple structure as compared with the case where the capacitor electrode is formed of, for example, a polysilicon film. Therefore, it is possible to add capacitance to the terminals without complicating the structure of the differential amplifier 4a, and it is possible to improve the manufacturing yield.

  Next, a manufacturing method of the liquid crystal device according to the present embodiment will be described with reference to FIG. FIG. 17 is a process diagram showing a series of manufacturing steps for manufacturing the liquid crystal device according to this embodiment. 17 corresponds to the cross-sectional view of the pixel portion shown in FIG. 15 and the cross-sectional view of the capacitor shown in FIG.

  First, as shown in step (a) of FIG. 17, in the region where the pixel portion 2a is to be formed (that is, the image display region 10a), the scanning line G to the first interlayer insulating film 41 are formed on the TFT array substrate 10. Each layer structure is formed and laminated. At this time, the TFT 30 is formed in a region corresponding to the intersection of the scanning line G and the data line S to be formed later. In each step, a normal semiconductor integration technique can be used. Further, after the formation of the first interlayer insulating film 41, the surface thereof may be planarized by CMP treatment or the like. On the other hand, the base insulating film 12 and the first interlayer insulating film 41 are stacked on the TFT array substrate 10 at the same opportunity as the stacking in the pixel portion 2a in the peripheral region where the capacitor 4h is to be formed.

  Subsequently, in a region where the pixel portion 2a is to be formed, a predetermined position on the surface of the first interlayer insulating film 41 is etched to reach the contact hole 81 having a depth reaching the high concentration source region 1d and the high concentration drain region 1e. A contact hole 83 having a depth is opened. Next, a conductive light shielding film is laminated in a predetermined pattern, and the data line S and the relay layer 600 are formed. The data line S is formed so as to partially cover the channel region 1 a of the TFT 30 and is connected to the high-concentration source region 1 d through the contact hole 81. The relay layer 600 is connected to the high-concentration drain region 1 e through the contact hole 83. Next, a second interlayer insulating film 42 is formed on the entire surface of the TFT array substrate 10 (that is, a region including a region where the pixel portion 2a is to be formed and a region where the capacitor 4h is to be formed). After the formation of the second interlayer insulating film 42, the surface thereof is planarized by CMP processing or the like.

  Subsequently, a metal film is stacked on a region where the additional capacitor Cs is to be formed and a region where the capacitor 4h is to be formed among regions where the pixel portion 2a is to be formed. Thereby, a lower electrode 71 made of a metal film is formed in a region where the pixel portion 2a is to be formed, and a first electrode 4h1 made of a metal film is formed in a region where the capacitor 4h is to be formed. That is, the lower electrode 71 and the first electrode 4h1 are formed by laminating the same metal film at the same opportunity in the manufacturing process. The lower electrode 71 and the first electrode 4h1 are separated from each other.

  The lower electrode 71 is formed in a predetermined region on the surface of the second interlayer insulating film 42 including a region facing the channel region 1a ′. In order to reduce the possibility of defects due to electric field concentration, a taper may be formed using wet etching at a predetermined edge of the lower electrode 71.

  Next, as shown in step (b) of FIG. 17, a dielectric film is formed in a region including the region where the additional capacitor Cs is to be formed and the region where the capacitor 4h is to be formed among the regions where the pixel portion 2a is to be formed. Laminate. Thereby, the dielectric film 75 is formed in the region where the pixel portion 2a is to be formed, and the dielectric film 4h3 is formed in the region where the capacitor 4h is to be formed. That is, the dielectric films 75 and 4h3 are formed by stacking the same dielectric films on the same occasion in the manufacturing process. The dielectric films 75 and 4h3 are separated from each other. The dielectric film 75 is formed in a non-opening region on the TFT array substrate 10.

  Next, as shown in step (c) of FIG. 17, etching is performed at a predetermined position on the surface of the dielectric film 75 in the region where the pixel portion 2 a is to be formed, and the contact hole 84 having a depth reaching the intermediate layer 600. Open the hole.

  Subsequently, a metal film is stacked on a region where the additional capacitor Cs is to be formed and a region where the capacitor 4h is to be formed among regions where the pixel portion 2a is to be formed. Thus, the capacitor electrode 300 made of a metal film is formed in the region where the pixel portion 2a is to be formed, and the second electrode 4h2 made of a metal film is formed in the region where the capacitor 4h is to be formed. That is, the capacitor electrode 300 and the second electrode 4h2 are formed by laminating the same metal film at the same opportunity in the manufacturing process. The capacitive electrode 300 and the second electrode 4h2 are separated from each other. Each of the additional capacitor Cs and the capacitor 4h formed in this way has an MIM structure.

  Thus, when the capacitor 4h is formed with the MIM structure, the capacitor can be formed with a simple structure as compared with the case where the capacitor electrode is formed of, for example, a polysilicon film. Therefore, it is possible to add capacitance to the terminals without complicating the structure of the differential amplifier 4a, and it is possible to improve the manufacturing yield.

  Next, a third interlayer insulating film 43 is formed on the entire surface of the TFT array substrate 10 (see FIGS. 15 and 16). After the formation of the second interlayer insulating film 42, the surface thereof is planarized by CMP processing or the like.

  Subsequently, as shown in FIG. 15, in a region where the pixel portion 2 a is to be formed, a predetermined position on the surface of the third interlayer insulating film 43 is etched, and a contact hole having a depth reaching the extending portion of the capacitor electrode 300. 85 is opened. Next, the pixel electrode 9 a is formed at a predetermined position on the surface of the third interlayer insulating film 43. At this time, the pixel electrode 9a is also formed inside the contact hole 85. However, since the hole diameter of the contact hole 85 is large, the coverage is good.

According to the liquid crystal device manufacturing method described above, the above-described liquid crystal device of the present embodiment can be manufactured. In particular, the first electrode 4h1, the dielectric film 4h3, and the second electrode 4h2 constituting the capacitor 4h are formed on the same occasion as the formation of the lower electrode 71, the dielectric film 75, and the capacitor electrode 300, respectively. The capacitor 4h can be formed without complicating the laminated structure and the manufacturing process.
Second Embodiment
Next, a liquid crystal device according to a second embodiment will be described with reference to FIG. FIG. 18 is a block diagram having the same concept as in FIG. 3 in the second embodiment. In FIG. 18, the same components as those in the first embodiment shown in FIGS. 1 to 17 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  In FIG. 18, for simplification of the drawing, illustration of the X driver circuit 101, the Y driver circuit 104, the video signal line 7 and the like for driving the plurality of pixel portions 2a is omitted.

  18, the liquid crystal device according to this embodiment includes a plurality of pixel units 2a, an X driver circuit 101, a Y driver circuit 104, a sampling circuit 77, a video signal line 7, a differential amplifier circuit 101, and a display data readout circuit 4. The configuration is the same as that of the liquid crystal device according to the first embodiment described above. The configurations of the equalizing circuit 8 and the precharge and reference circuit 13 provided between the display data reading circuit 4 and the plurality of pixel portions 2a arranged in the image display area 10a are also related to the first embodiment described above. The same as the liquid crystal device.

  This embodiment is different from the liquid crystal device according to the first embodiment described above in that a transmission gate 62 is employed instead of the transmission gate 60. In other words, the pixel portion 4a electrically connected to the four data lines S can be inspected by one differential amplifier circuit 4a. Therefore, one differential amplifier circuit 4a can be formed for every interval at which the four data lines S are arranged, the area of the differential amplifier circuit 4a is increased, the driving capability is improved, and the differential amplification is performed. The inspection accuracy can be improved by reducing the variation of the circuit 4a. The pull-down circuit 36 is configured in the same manner as the pull-down circuit 35 described above with reference to FIG.

  In FIG. 18, the transmission gate 62 selectively electrically connects the so wiring 4g to one of the two data lines S, and selectively selects the se wiring 4f to one of the two data lines S. Connect electrically. That is, the differential amplifier circuit 4a is provided for every four data lines S. The so wiring 4g electrically connected to the terminal so of the differential amplifier circuit 4a is connected to the (4u + 1) th column or the (4u + 2) th column (where u is an integer of 0 or more) through the transistors 62a and 62b, respectively. It is electrically connected to the data line S. The se wiring 4f electrically connected to the terminal se of the differential amplifier circuit 4a is electrically connected to the data line S in the (4u + 3) th column or the (4y + 4) th column through the transistors 62c and 62d, respectively. Is done.

  Terminals te1 to te4 are electrically connected to the gates of the transistors 62a to 62d, respectively. For example, an external circuit such as a TE gate decode circuit is electrically connected to the terminals te1 to te4 and supplied with connection control signals TE1 to TE4, respectively. The connection control signals TE1 to TE4 are signals for determining to which data line S the so wiring 4g and the se wiring 4f of the differential amplifier circuit 4a are electrically connected. The transistors 62a to 62d to which the LOW connection control signals TE1 to TE4 are applied to the gates are turned off, and the electrical connection between the so wiring 4g and se wiring 4f and the data line S is cut off. On the contrary, the transistors 32a to 32d to which the HIGH connection control signals TE1 to TE4 are applied to the gates are turned on, and the so wiring 4g and se wiring 4f are electrically connected to the data line S.

  With this configuration, when the connection control signal TE1 is supplied to the terminal te1, the transistor 62a is turned on, and the data line S in the (4u + 1) th column is electrically connected to the so wiring 4g. Therefore, it is possible to inspect the pixel portion 2a electrically connected to the data lines S1, S5, S9,. Similarly, when the connection control terminals TE2 to TE4 are respectively supplied to the terminals te2 to te4, the transistors 62b to 62d are turned on, and the data line S in the (4u + 2) th column to the (4u + 4) th column is connected to the so wiring 4g. Electrically connected. Therefore, the quality of the pixel portion 2a electrically connected to each data line S can be inspected. The connection control signals TE1 to TE4 are switched to LOW or HIGH according to the inspection flow for only one of the terminals te1 to te4 corresponding to the data line S to be inspected, and the other three The connection control signal maintains LOW.

  Further, in the present embodiment, in particular, in addition to the capacitor 4h electrically connected to the terminal se of the differential amplifier circuit 4a, the capacitor 4i electrically connected to the terminal so is provided. This is different from the liquid crystal device according to one embodiment. Therefore, when the differential amplifier circuit 4a corresponding to the data lines S (for example, the data lines S1 to S4) in the (4u + 1) th column, the (4u + 2) th column, the (4u + 3) th column, and the (4u + 4) th column is viewed. The values of the capacitors 4i and 4h are the sum of the wiring capacities of the (4u + 1) th column data line and the (4u + 2) th column data line (for example, the data lines S1 and S2) (or the (4u + 3) th column data line), respectively. By setting the value larger than the (4u + 4) th column data line (for example, the sum of the wiring capacities of the data lines S3 and S4), the amount of pushdown at the terminals se and so is relatively small. can do. Therefore, it is possible to prevent the reference of the terminal se after the push-down has occurred from becoming lower than the potential of the terminal so at the time of LOW writing. That is, it is possible to prevent an error from occurring in the determination result of the differential amplifier circuit 4a.

  In addition, in the present embodiment, not only the capacitor 4h but also the capacitor 4i has the same MIM structure as the additional capacitor Cs in the pixel portion 2a. That is, in the same manner as described above for the capacitor 4h with reference to FIGS. 15 and 16, the two electrodes constituting the capacitor 4i are the lower electrode 71 and the capacitor electrode 300 (see FIG. 15) constituting the additional capacitor Cs. The dielectric films formed from the same film and constituting the capacitor 4i are the same film as the dielectric film 75 (see FIG. 15) constituting the additional capacitor Cs. Therefore, in addition to the capacitor 4h, the capacitor 4i can also be increased in capacity compared to the case where the electrode is formed of, for example, a polysilicon film. Therefore, by setting the value sufficiently larger than the wiring capacity of the data line S in a relatively small area on the TFT array substrate 10, the amount of pushdown of the terminals se and so can be made relatively sufficiently small. Can do. That is, the differential amplifier 4a can be prevented from malfunctioning with little or preferably no increase in the size of the TFT array substrate 10, and an accurate comparison result can be obtained.

  Furthermore, as described above, not only the capacitor 4h but also the capacitor 4i is composed of the same film as the additional capacitor Cs. Therefore, the two electrodes and the dielectric film constituting the capacitor 4i are lower portions constituting the additional capacitor Cs. The electrode 71, the capacitor electrode 300, and the dielectric film 75 can be formed on the same occasion. That is, the capacitors 4h and 4i can be formed without complicating the manufacturing process.

(Electronics)
Next, the case where the liquid crystal device which is the above-described electro-optical device is applied to various electronic devices will be described.

  First, a projector using this liquid crystal device as a light valve will be described. FIG. 19 is a plan view showing a configuration example of the projector. As shown in FIG. 19, a projector 1100 includes a lamp unit 1102 made of a white light source such as a halogen lamp. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by four mirrors 1106 and two dichroic mirrors 1108 arranged in the light guide 1104, and serves as a light valve corresponding to each primary color. The light enters the liquid crystal panels 1110R, 1110B, and 1110G.

  The configurations of the liquid crystal panels 1110R, 1110B, and 1110G are the same as those of the liquid crystal device described above, and are driven by R, G, and B primary color signals supplied from the image signal processing circuit. The light modulated by these liquid crystal panels enters the dichroic prism 1112 from three directions. In this dichroic prism 1112, R and B light is refracted at 90 degrees, while G light travels straight. Accordingly, as a result of the synthesis of the images of the respective colors, a color image is projected onto the screen or the like via the projection lens 1114.

  Here, paying attention to the display images by the liquid crystal panels 1110R, 1110B, and 1110G, the display image by the liquid crystal panel 1110G needs to be horizontally reversed with respect to the display images by the liquid crystal panels 1110R, 1110B.

  Since light corresponding to the primary colors R, G, and B is incident on the liquid crystal panels 1110R, 1110B, and 1110G by the dichroic mirror 1108, it is not necessary to provide a color filter.

  Next, an example in which the liquid crystal device is applied to a mobile personal computer will be described. FIG. 20 is a perspective view showing the configuration of this personal computer. In FIG. 20, the computer 1200 includes a main body 1204 provided with a keyboard 1202 and a liquid crystal display unit 1206. The liquid crystal display unit 1206 is configured by adding a backlight to the back surface of the liquid crystal device 1005 described above.

  Further, an example in which the liquid crystal device is applied to a mobile phone will be described. FIG. 21 is a perspective view showing the configuration of this mobile phone. In FIG. 21, a mobile phone 1300 includes a reflective liquid crystal device 1005 together with a plurality of operation buttons 1302. In the reflective liquid crystal device 1005, a front light is provided on the front surface thereof as necessary.

  In addition to the electronic devices described with reference to FIGS. 19 to 21, a liquid crystal television, a viewfinder type, a monitor direct-view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, a word processor, a work Examples include a station, a videophone, a POS terminal, a device equipped with a touch panel, and the like. Needless to say, the present invention can be applied to these various electronic devices.

  In addition to the liquid crystal device described in the above embodiment, the present invention also includes a reflective liquid crystal device (LCOS) in which elements are formed on a silicon substrate, a plasma display (PDP), a field emission display (FED, SED), The present invention can also be applied to an organic EL display, a digital micromirror device (DMD), an electrophoresis apparatus, and the like.

  The present invention is not limited to the above-described embodiment, and can be appropriately changed without departing from the spirit or idea of the invention that can be read from the claims and the entire specification, and an electro-optical device with such a change, In addition, an electronic apparatus including the electro-optical device is also included in the technical scope of the present invention.

It is a top view which shows the whole structure of the liquid crystal device which concerns on 1st Embodiment. It is sectional drawing of HH 'of FIG. 1 is a block diagram illustrating a main circuit configuration of a liquid crystal device according to a first embodiment. It is a circuit diagram which shows the electrical structure of a pixel part. It is a circuit diagram which shows the electric constitution of a differential amplifier circuit. It is a circuit diagram which shows the electrical structure of a pull-up circuit. It is a circuit diagram which shows the electric constitution of a pull-down circuit. 5 is a timing chart for explaining a malfunction of the differential amplifier circuit. It is a block diagram of an inspection system. It is a flowchart which shows the example of the whole flow of a test | inspection. 11 is a timing chart for explaining a read operation in step ST2 of FIG. It is explanatory drawing which shows the writing state of each pixel part at the time of a test | inspection. It is a top view showing the partial structure which concerns on the pixel part on a TFT array substrate, and is a figure equivalent to a lower layer part among laminated structures. It is a top view showing the partial structure concerning the pixel part on a TFT array substrate, and is a figure corresponded to the upper layer part among laminated structures. It is AA 'sectional drawing at the time of superposing FIG.13 and FIG.14. It is sectional drawing containing the capacity | capacitance electrically connected to the terminal of the differential amplifier. It is process drawing which shows a series of manufacturing processes which manufacture the liquid crystal device which concerns on 1st Embodiment. It is a block diagram with the same meaning as FIG. 3 in 2nd Embodiment. It is a top view which shows the structure of the projector which is an example of the electronic device to which the electro-optical apparatus is applied. 1 is a perspective view showing a configuration of a personal computer as an example of an electronic apparatus to which an electro-optical device is applied. It is a perspective view which shows the structure of the mobile telephone which is an example of the electronic device to which the electro-optical apparatus is applied.

Explanation of symbols

  2a ... Pixel part, 4a ... Differential amplifier circuit, 4h, 4i ... Capacitance, 4h1 ... First electrode, 4h2 ... Second electrode, 4h3 ... Dielectric film, 7 ... Image signal line, 8 ... Equalize circuit, 9a ... Pixel Electrode, 77 ... Sampling circuit, 10 ... TFT array substrate, 10a ... Image display area, 13 ... Precharge and reference circuit, 20 ... Counter substrate, 60,62 ... Transmission gate, 71 ... Lower electrode, 75 ... Dielectric film, DESCRIPTION OF SYMBOLS 101 ... X driver circuit, 102 ... External circuit connection terminal, 104 ... Y driver circuit, 300 ... Capacitance electrode, Cs ... Additional capacity, G ... Scanning line, S ... Data line, so, se ... Terminal

Claims (5)

On the board
A plurality of scan lines and a plurality of data lines intersecting each other;
A plurality of pixel portions arranged in a matrix corresponding to intersections of the plurality of scanning lines and the plurality of data lines;
The first and second terminals are provided, and the potential signal supplied to the first terminal is compared with the potential signal supplied to the second terminal, and then supplied to the first terminal. When the potential signal is low, the potential of the first terminal is lowered, and when the potential signal supplied to the first terminal is high, the potential of the first terminal is raised and output. An amplifier;
Supply means for supplying a reference potential to one of the first and second terminals and reading and supplying a potential signal input to the pixel portion to the other;
A first electrode made of a first metal film, a first dielectric film, and a second metal film made of a second metal and electrically connected to at least one of the first and second terminals. An electro-optical device comprising: a capacitor in which electrodes are laminated in this order.   Each of the plurality of pixel portions includes a lower electrode made of the same film as the first metal film, a second dielectric film made of the same film as the first dielectric film, and the first electrode on the substrate. 2. The electro-optical device according to claim 1, further comprising a storage capacitor in which upper electrodes made of the same film as the two metal films are stacked in this order.   3. The electro-optical device according to claim 1, wherein the capacitor is electrically connected only to a terminal to which the reference potential is supplied out of the first and second terminals.   An electronic apparatus comprising the electro-optical device according to any one of claims 1 to 3. Forming a plurality of scanning lines and a plurality of data lines intersecting each other on a substrate;
Forming a plurality of pixel portions in a matrix on the substrate corresponding to the intersection of the plurality of scanning lines and the plurality of data lines;
The first and second terminals are provided on the substrate, and the potential of the potential signal supplied to the first terminal and the potential signal supplied to the second terminal are compared, and the first When the potential signal supplied to the first terminal is low, the potential of the first terminal is lowered, and when the potential signal supplied to the first terminal is high, the potential of the first terminal is further increased. Forming an amplifier to output at a higher level; and
Forming a supply means on the substrate for supplying a reference potential to one of the first and second terminals and reading and supplying a potential signal input to the pixel portion on the other;
On the substrate, a first electrode made of a first metal film, a first dielectric film, and a second so as to be electrically connected to at least one of the first and second terminals. Forming a capacitor by laminating the second electrode made of the metal film in this order,
By the step of forming the capacitor, each of the plurality of pixel portions is formed of a lower electrode made of the same film as the first metal film, the first dielectric film, and the same film as the second metal film. A storage capacitor is formed by stacking upper electrodes formed in this order.

Images