JP2006343617A - Electrooptical device and electronic appliance - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To conduct inspection with sufficient measurement accuracy without necessitating a contact etc. of a probe from the outside. <P>SOLUTION: An electrooptical device is equipped with a plurality of scanning lines and a plurality of signal lines, a plurality of pixel portions, and a plurality of first amplifying means which are arranged corresponding to respective pairs of two signal lines, to which a first electric potential signal is supplied via one signal line out of the two signal lines and a second electric potential signal as a reference electric potential is supplied via the other signal line and which outputs a first low electric potential signal or a first high electric potential signal. Furthermore, the electrooptical device is equipped with a plurality of second amplifying means which are arranged on the side of a pixel array region opposite to that of the first amplifying means, to which a first electric potential signal is supplied via one signal line out of the two signal lines and a second electric potential signal is supplied via the other signal line and which outputs a second low electric potential signal or a second high electric potential signal. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a technical field of an electro-optical device such as a liquid crystal device and an electronic apparatus such as a liquid crystal projector.

  Conventionally, display devices such as liquid crystal devices are widely used in devices such as mobile phones and projectors. 2. Description of the Related Art A liquid crystal display device using a TFT (Thin Film Transistor) or the like is configured by adhering a TFT substrate and a counter substrate and sealing liquid crystal between the substrates. In general, an inspection of whether a manufactured liquid crystal device operates normally is performed on a finished product. For example, a predetermined image signal is input to the liquid crystal device as display data, and is projected, displayed, or the like to check whether the data is correctly displayed or whether there is a defective pixel.

  However, the method of inspecting a finished product is not preferable from the viewpoint of manufacturing process management. The reason is that a defective product is found after the substrate manufacturing process, so that the detection of the defective product is delayed.

  For this reason, the time until failure detection for process management is fed back becomes longer. As a result, the yield reduction period becomes longer and the manufacturing cost increases. Also, in the case of a prototype, since the period of time from the evaluation of the prototype to the feedback to the design is prolonged, the development period is prolonged and the development cost is increased. Furthermore, after the product is completed, so-called repair, that is, repair of a defective portion is difficult.

  Therefore, it is desired to find a defect, particularly a defective pixel of a display device, in the manufacturing process of the substrate.

  As one of such inspection methods, a technique for inspecting a liquid crystal display device by bringing a test probe into contact with an electrode pad of the liquid crystal display device and supplying a predetermined current has been proposed (for example, Patent Document 1). Similarly, a technique has been proposed in which a predetermined voltage is applied to each pixel of the TFT based on the capacitor capacitance characteristics of the pixel, and the function of the TFT is inspected based on the waveforms of the discharge current and the discharge voltage (for example, Patent Documents). 2).

  In addition, a technique for inspecting the operation of each pixel electrode by detecting the amount of change in the potential of the pixel electrode using an inspection counter electrode corresponding to the pixel electrode of the TFT substrate has been proposed (for example, patents). Reference 3).

Japanese Patent Laid-Open No. 5-341302 JP-A-7-333278 JP-A-10-104563

  However, in the case of the techniques described in Patent Document 1 and Patent Document 3 described above, in the inspection apparatus, mechanical position accuracy is required to bring a predetermined probe or the like into contact with or close to an electrode pad or the like from the outside of the substrate. . As a result, there is a technical problem that the inspection time becomes long in order to ensure mechanical alignment accuracy. Furthermore, in the case of a high-definition liquid crystal display device, a thin probe or the like must be brought into contact with many electrode pads by performing mechanical control, and these methods may not be applied.

  Further, in the method described in Patent Document 2 described above, various capacitance components between the liquid crystal display device and the measurement device, for example, the capacitance in the source line, the video line, the electrode pad terminal, and the like are affected, so that the capacitance of the pixel itself is relatively low. If it is small, there is a technical problem that sufficient measurement accuracy cannot be obtained.

  The present invention has been made in view of the above-described conventional problems, and provides an electro-optical device capable of realizing inspection capable of obtaining sufficient measurement accuracy without requiring contact with an external probe. This is the issue.

  In order to solve the above problems, an electro-optical device according to an aspect of the invention includes a plurality of scanning lines and a plurality of signal lines disposed on the substrate so as to intersect with each other in the pixel array region, and the plurality of signal lines. And a plurality of pixel portions provided corresponding to intersections of the plurality of scanning lines and a plurality of signal lines each including two signal lines among the plurality of signal lines. The first potential signal is supplied via one of the two signal lines, and the reference potential is supplied via the other signal line of the two signal lines. (I) when the potential of the first potential signal is lower than the potential of the second potential signal, it is lower than the potential of the first potential signal via the one signal line. A first low potential signal having a potential; (ii) a potential of the first potential signal is the second potential signal; A plurality of first amplifying means for outputting a first high potential signal having a potential higher than the potential of the first potential signal via the one signal line when the potential is higher than the potential of the potential signal; and the plurality of signals Corresponding to each of the sets of lines and provided on the opposite side of the pixel array region from the first amplifying means, the first potential signal is supplied via the one signal line. The second potential signal is supplied via the other signal line, and (i) when the potential of the first potential signal is lower than the potential of the second potential signal, the second potential signal is sent via the one signal line. A second low-potential signal having a potential lower than the potential of the first potential signal; (ii) when the potential of the first potential signal is higher than the potential of the second potential signal, A second high potential having a potential higher than the potential of the first potential signal; And a plurality of second amplifier means for outputting a degree.

  According to the electro-optical device of the present invention, during the operation, an image signal is supplied to each pixel unit via the data line by, for example, an X-driver circuit. At the same time, a scanning signal is supplied to each pixel unit via the scanning line by the Y-driver circuit. For example, a pixel switching thin film transistor (hereinafter referred to as “pixel switching TFT”) provided for each pixel portion has a gate connected to a scanning line, and selectively selects an image signal as a pixel electrode in accordance with the scanning signal. To supply. Accordingly, for example, by driving an electro-optical material such as liquid crystal sandwiched between the pixel electrode and the counter electrode in each pixel portion, active matrix driving is possible. At this time, the storage capacitor improves the potential holding characteristic in the pixel portion, and the display can have high contrast.

  In particular, the present invention includes first amplification means. The first amplifying unit determines a first high-potential signal or a first low-potential signal via one signal line, for example, whether the pixel unit is good or bad, at the time of inspection performed prior to the operation of the electro-optical device. Output to the means. Such inspection is preferably performed before the electro-optical device is bonded to the pair of substrates, for example, when a substrate called an element array substrate, an element substrate, or a TFT array substrate is completed. Is done.

  More specifically, at the time of this inspection, for example, when the first potential signal output from the pixel portion has a slightly higher potential than the second potential signal, the first potential with respect to the potential of the second potential signal. The first amplifying means has a first high potential whose potential is higher than that of the first potential signal so that a high signal potential is not obscured by noise applied to the first signal line and the second signal line. For example, the signal is output to the first determination means via one signal line. When the first potential signal has a slightly lower potential than the second potential signal, the first signal line and the second signal line indicate that the potential of the first potential signal is lower than the potential of the second potential signal. In order not to be obscured by the applied noise, the amplifying means lowers the potential of the first potential signal, and then outputs the first low potential signal whose potential is kept low through one signal line. Here, the “first potential signal” is a signal reflecting the quality of the pixel portion, and more specifically, for example, is a signal output according to the quality of the pixel portion. For example, an inspection signal is supplied to the pixel portion in advance prior to the inspection, and a signal having a potential that varies from the potential of the inspection signal according to the quality of the pixel portion is output as the first potential signal. “Possibility of the pixel portion” means whether or not the pixel portion has a defect, and the level relationship between the potentials of the first potential signal and the second potential signal varies depending on the defect occurring in the pixel portion. . The “second potential signal” has a reference potential that serves as a reference for increasing or decreasing the potential of the first potential signal.

  The first determination unit is, for example, an external circuit provided outside the substrate of the electro-optical device of the present invention. For example, the potential of the inspection signal that is supplied in advance to the pixel unit and serves as a basis of the first potential signal. Is higher or lower than the potential of the second potential signal, and the potential of the first high potential signal or the first potential is compared with the potential of the signal output from the first amplification means based on the second potential signal. Whether the pixel portion is good or bad is determined by voltage logic that compares information about whether the potential of the low potential signal is high or low.

  According to such a determination method, when the potential of the inspection signal that is the basis of the first potential signal is higher than the potential of the second potential signal, if the first high potential signal is output from the first amplifying unit, It is determined that no defect has occurred in the pixel portion electrically connected to the signal line, that is, the pixel portion to which the inspection signal that is the basis of the first potential signal is supplied. On the other hand, if the first low potential signal is output from the first amplifying means when the potential of the inspection signal that is the basis of the first potential signal is higher than the potential of the second potential signal, it is electrically connected to one signal line. It is determined that some defect has occurred in the pixel portion. If the first low potential signal is output from the first amplifying means when the potential of the inspection signal that is the source of the first potential signal is lower than the potential of the second potential signal, it is electrically connected to one signal line. This means that no defect has occurred in the pixel portion. A pixel that is electrically connected to one signal line if the first high potential signal is output from the first amplifying means when the potential of the inspection signal that is the basis of the first potential signal is lower than the potential of the second potential signal. It is determined that some defect has occurred in the pixel portion, that is, the pixel portion to which the inspection signal that is the basis of the first potential signal is supplied.

  Furthermore, in the present invention, in particular, a second amplifying unit is further provided corresponding to each of the plurality of signal line sets and on the opposite side of the pixel array region from the first amplifying unit. Similarly to the first amplifying means, the second amplifying means outputs the second high potential signal or the second low potential signal to, for example, a second determining means for determining the quality of the pixel portion via one signal line.

  By the second amplifying means, the first potential signal and the second potential signal can be input from the side opposite to the pixel array area from the first amplifying means, in other words, the first potential signal can be detected. In addition, the first and second potential signals can be detected at high speed. For example, the first and second potential signals from the pixel portion provided in the area opposite to the first amplifying means in the pixel array area, that is, located in the area away from the first amplifying means, are supplied to the second amplifying means. Can also be detected. Since the pixel portion located in a region farther from the first amplifying means is closer to the second amplifying means, the first and second potential signals from such a pixel portion are generated by the second amplifying means only by the first amplifying means. It can be detected at a higher speed than the case. That is, for example, the quality of the pixel portion can be determined at high speed by the second determination unit in addition to the first determination unit. On the other hand, for a pixel unit located in a region away from the second amplifying unit, the quality of the pixel unit can be determined by the first determining unit, for example, at higher speed than when only the second amplifying unit is used. Therefore, the quality of the pixel portion located in any region in the pixel array region can be determined at high speed by the first amplification unit and the second amplification unit.

  As described above, according to the electro-optical device of the present invention, it is not necessary to contact the probe from the outside, and it is possible to inspect with sufficient measurement accuracy. Furthermore, the first and second potential signals from the pixel portion located in any region in the pixel array region can be detected accurately and at high speed, and the quality of the pixel portion can be determined accurately and in a short time. In addition, it is possible to make a determination at a relatively early stage in various manufacturing processes. Accordingly, the yield of electro-optical devices such as liquid crystal devices can be increased, and the manufacturing cost can be reduced.

  In one aspect of the electro-optical device according to the aspect of the invention, the first potential signal is a signal supplied to all or part of the plurality of pixel portions, and the second potential signal is a signal supplied from the outside. is there.

  According to this aspect, since the second signal as the reference signal can be stably supplied from the outside, it is possible to more reliably determine the quality of the pixel unit. That is, a defect in the pixel portion can be reliably detected as a defect for each pixel portion.

  In another aspect of the electro-optical device of the present invention, each of the plurality of first and the plurality of second amplifying units includes a plurality of differences electrically connected to each of the plurality of signal lines. It has a dynamic amplification circuit.

  According to this aspect, the first and second potential signals are collectively supplied from each of the pair of two signal lines to the differential amplifier circuit electrically connected to each pair. A high potential signal or a low potential signal can be output from each differential amplifier circuit provided for each set of two signal lines. That is, the potential difference between the first and second potential signals can be clearly output.

  In another aspect of the electro-optical device of the present invention, each of the plurality of pixel units has a storage capacitor.

  According to this aspect, it is possible to detect a storage capacity defect.

  In another aspect of the electro-optical device of the present invention, the electro-optical device further includes a precharge circuit that is electrically connected to the plurality of signal lines and precharges the plurality of pixel portions.

  According to this aspect, before the inspection, for example, it is possible to supply the inspection signal that is the basis of the first potential signal from the precharge circuit to the plurality of pixel units, that is, precharge, which is practically convenient.

  In another aspect of the electro-optical device of the present invention, the electro-optical device is provided in a region near the first amplifying unit when viewed from the pixel portion on the substrate surface of the substrate, and is in the middle of the pair of signal lines. A first transmission gate electrically connected; first switching means for switching on / off of the first transmission gate; and a region closer to the second amplification means as viewed from the pixel portion on the substrate surface of the substrate. A second transmission gate electrically connected in the middle of the pair of signal lines, and a second switching means for switching on and off the second transmission gate, The first potential signal and the second potential signal are the same as each other when the first transmission gate is switched on by the first switching means. The second transmission gate is supplied to the first amplifying means through the signal line and the second transmission gate is turned on by the second switching means. Supplied to amplification means.

  According to this aspect, the first and second potential signals can be supplied to the first or second amplifying means by switching the first or second transmission gate to the on state, for example, when checking the quality of the pixel portion. As described above, the pixel portion and the first or second amplifying means can be electrically connected through a pair of signal lines. The first and second transmission gates are switched on and off by the first and second switching means, respectively. The first and second transmission gates are electrically connected not only to one signal line but also to the other signal line, and when the first potential signal is supplied to the first or second amplification means, The second potential signal can be supplied to the first or second amplifying means via the other signal line in accordance with the timing at which the first potential signal is supplied to the first or second amplifying means.

  In order to solve the above problems, an electronic apparatus according to the present invention includes the above-described electro-optical device according to the present invention (including various aspects thereof).

  Since the electronic apparatus of the present invention includes the above-described electro-optical device of the present invention, a projection display device, a television, a mobile phone, an electronic notebook, a word processor, a view capable of performing high-quality image display. Various electronic devices such as a finder type or a monitor direct-view type video tape recorder, a workstation, a videophone, a POS terminal, and a touch panel can be realized. In addition, as an electronic apparatus of the present invention, for example, an electrophoretic device such as electronic paper, an electron emission device (Field Emission Display and a Conduction Electron-Emitter Display), an electrophoretic device, and a device using the electron emission device, DLP (Digital Light Processing) and the like can also be realized. In addition, since such an electronic apparatus includes the above-described electro-optical device, the yield is improved.

  Such an operation and other advantages of the present invention will become apparent from the embodiments described below.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, a driving circuit built-in type TFT active matrix driving type liquid crystal device, which is an example of the electro-optical device of the present invention, is taken as an example.

(First embodiment)
The liquid crystal device according to the first embodiment will be described with reference to FIGS.

  First, the overall configuration of the liquid crystal device according to the present embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view showing the overall configuration of the liquid crystal device according to this embodiment, and FIG. 2 is a cross-sectional view taken along the line H-H ′ of FIG. 1.

  1 and 2, in the liquid crystal device according to the present embodiment, a TFT array substrate 10 and a counter substrate 20 are arranged to face each other. A liquid crystal layer 50 is sealed between the TFT array substrate 10 and the counter substrate 20, and the TFT array substrate 10 and the counter substrate 20 are included in an image display region 10a as an example of the “pixel array region” according to the present invention. They are bonded to each other by a sealing material 52 provided in a surrounding sealing region.

  In FIG. 1, a light-shielding frame light-shielding film 53 that defines the frame area of the image display region 10a is provided on the counter substrate 20 side in parallel with the inside of the seal region where the sealing material 52 is disposed. An X-driver circuit 101 and an external circuit connection terminal 102 are provided along one side of the TFT array substrate 10 in a region located outside the seal region where the seal material 52 is disposed in the peripheral region. The sampling circuit 110 is provided so as to be covered with the frame light shielding film 53 on the inner side of the seal region along the one side. The Y-driver circuit 104 is provided so as to be covered with the frame light-shielding film 53 inside the seal region along two sides adjacent to the one side. On the TFT array substrate 10, vertical conduction terminals 106 for connecting the two substrates with the vertical conduction material 107 are arranged in regions facing the four corner portions of the counter substrate 20. Thus, electrical conduction can be established between the TFT array substrate 10 and the counter substrate 20.

  On the TFT array substrate 10, a lead wiring 90 is formed for electrically connecting the external circuit connection terminal 102 to the X-driver circuit 101, the Y-driver circuit 104, the vertical conduction terminal 106, and the like. .

  In FIG. 2, on the TFT array substrate 10, a laminated structure in which wiring such as a pixel switching TFT (Thin Film Transistor) as a driving element, a scanning line, and a data line is formed. In the image display area 10a, a pixel electrode 9a is provided in an upper layer of wiring such as a pixel switching TFT, a scanning line, and a data line. An alignment film is formed on the pixel electrode 9a. On the other hand, on the counter substrate 20, in addition to the counter electrode 21, a lattice-shaped or striped light-shielding film 23 and an alignment film are formed on the uppermost layer portion. The liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several types of nematic liquid crystals are mixed, and takes a predetermined alignment state between the pair of alignment films.

  Although not shown here, on the TFT array substrate 10, in addition to the X-driver circuit 101 and the Y-driver circuit 104, as will be described later, “first amplifying means” and “second” A plurality of first and second differential amplifier circuits, precharge circuits, first and second transmission gates, etc., each constituting an example of the “amplifying means” are formed.

  Next, the circuit configuration of the liquid crystal device according to the present embodiment will be described with reference to FIGS. FIG. 3 is a block diagram showing the main circuit configuration of the liquid crystal device according to this embodiment. FIG. 4 is a circuit diagram showing an electrical configuration of the pixel portion. FIG. 5 is a circuit diagram showing an electrical configuration of the pull-down circuit. FIG. 6 is a conceptual diagram showing a state of a pixel portion to which a signal is supplied in advance at the time of inspection. FIG. 7 is a circuit diagram showing an electrical configuration of the pull-up circuit. In the following, for the sake of simplicity, the odd number (that is, the first number) along the direction in which the scanning line Gj (j = 1, 2,..., N; an integer greater than or equal to 2) extends as viewed from the left side in the drawing. (3), (5),...) Signal line Soi (i = 1, 2,..., M; m is an integer of 2 or more) is “one signal line” of the present invention. The signal lines Sei (i = 1, 2,..., M; m is an integer) selected and arranged in even-numbered (0th, 2nd, 4th,...) The description will be made on the assumption that the “signal line” is selected.

  In FIG. 3, the liquid crystal device of this embodiment includes a Y-driver circuit 104, an X-driver circuit 101, a sampling circuit 110, and a pixel unit 70 on the TFT array substrate 10.

  The Y-driver circuit 104 sequentially supplies a switching signal for each scanning line when the pixel unit 70 is inspected. Here, the switching signal is a signal different from the scanning signal for image display supplied to the pixel unit 70 when displaying an image, and an inspection signal described later supplied in advance to the pixel unit 70 is used as the pixel signal. This is a signal for switching the switching element included in the pixel unit 70 to the on state.

  The X-driver circuit 101 supplies a sampling signal to the sampling switch 111 that constitutes the sampling circuit 110, and switches the sampling switch 111 to an on state. Here, the “sampling signal” is different from a signal supplied from the X-driver circuit 101 to the sampling circuit 110 when displaying an image, and the first differential amplifier circuit 15 or the second differential amplifier circuit described later. This is a signal for individually outputting the first or second high potential signal or the first or second low potential signal output from 215 to an external test circuit for each of the signal lines Soi and Sei.

  When inspecting the pixel unit 70, the sampling circuit 110 outputs the first and second potential signals in correspondence with the signal lines Soi and Sei to which the pixel unit 70 to be inspected is electrically connected, The first or second high potential signal or the first or second low potential signal is output to an external test circuit via the image signal supply lines 112o and 112e.

  The pixel unit 70 is provided in the image display region 10a corresponding to the intersection of the signal lines Soi and Sei and the scanning line Gj.

  As shown in FIG. 4, the pixel unit 70 includes a TFT 73, a liquid crystal element 72, and a storage capacitor 73.

  The TFT 71 has a source electrically connected to the signal line Soi or Sei, and a gate electrically connected to the scanning line Gj. The TFT 71 is switched on and off by a switching signal supplied from the Y-driver circuit 104. The pixel unit 70 outputs the first potential signal to the signal line Soi and outputs the second potential signal to the signal line Sei. The liquid crystal element 72 has a liquid crystal injected between the TFT array substrate 10 and a counter substrate disposed so as to correspond to the TFT array substrate 10, and a pair of electrodes for sandwiching the liquid crystal. The storage capacitor 73 temporarily holds an image signal supplied to the pixel unit 70 when image display is performed, and enables active matrix driving of the plurality of pixel units 70.

  Referring again to FIG. 3, the liquid crystal device of this embodiment further includes a first inspection circuit 4 and a second inspection circuit 204 on the TFT array substrate 10.

  The first inspection circuit 4 includes a plurality of first differential amplifier circuits 15, a first differential amplifier circuit first drive signal supply circuit 21, and a first differential that constitute an example of the “first amplifier” of the present invention. Second drive signal supply circuit 22 for amplifier circuit, equalize circuit 23, voltage application wiring 24, precharge circuit 25, first connection circuit 26 as an example of the “first switching means” of the present invention, TFTs 11, 12a, 12b , 13p, and 13n, a first transmission gate 6, a plurality of signal lines Soi, and a plurality of signal lines Sei.

  A plurality of signal lines Soi and Sei are respectively extended from the image display region 10a to the first differential amplifier circuit 15, and are electrically connected to connection points So and Se of the first differential amplifier circuit 15, respectively. Yes. The signal lines Soi and Sei intersect the plurality of scanning lines Gj (j = 1, 2,..., N; n is an integer of 2 or more) provided in the image display area 10a. It extends in the image display area. The pixel portion 70 provided in the image display region 10a is arranged in accordance with the intersection of the signal lines Soi and Sei and the plurality of scanning lines Gj, and is electrically connected to the signal lines Soi and Sei.

  The first connection circuit 26 includes a first test signal supply line 45 that is electrically connected to the test circuit via a first test circuit connection gate terminal, and a pull-down circuit 35. The first test signal supply line 45 supplies a series of test signals supplied from the test circuit to the first transmission gate 6 when the pixel unit 70 is inspected. The pull-down circuit 35 stabilizes the potential of the first test signal supply line 45 so that the first test signal supplied to the first transmission gate 6 via the first test signal supply line 45 does not fluctuate.

  As shown in FIG. 5, the pull-down circuit 35 includes a TFT 135 having a gate electrically connected to the power supply VDD, a grounded source, and a drain electrically connected to the first test signal supply line 45. This reduces the fluctuation of the potential of the first test signal supply line 45 when the first test signal is supplied. The pull-down circuits 32, 32, 33, 34, 232 and 235 also have the same circuit configuration as the pull-down circuit 35.

  In FIG. 3 again, the first transmission gate 6 is provided in the middle of each of the signal lines Soi and Sei. The first transmission gate 6 is provided on the side close to the first differential amplifier circuit 15 when viewed from the pixel unit 70, and includes a plurality of TFTs 14 electrically connected in the middle of each of the signal lines Soi and Sei. Yes. The plurality of TFTs 14 are collectively turned on according to the first test signal supplied from the first test circuit via the first test signal supply line 45 when the pixel unit 70 is inspected. As a result, it is possible to secure supply paths for the first and second potential signals supplied to the first differential amplifier circuit 15 via the signal lines Soi and Sei, respectively. In the pixel unit 70 described above with reference to FIG. If the provided TFT 71 is switched to the ON state, the first potential signal and the second potential signal are collectively transmitted from each pixel unit 70 to each first differential amplifier circuit 15 via each of the signal lines Soi and Sei. Can supply.

  Here, at the time of inspection, an inspection signal and a reference signal having a predetermined potential are supplied to the plurality of pixel units 70 in advance. In the present embodiment, as shown in FIG. 6, the pixel portion 70 provided corresponding to the signal line Soi has a potential higher than an intermediate potential (indicated as “M” in FIG. 8) as a reference potential. (Hereinafter referred to as “HIGH potential” as appropriate; indicated as “H” in FIG. 8), an intermediate potential reference signal is supplied to the pixel portion 70 provided corresponding to the signal line Sei. Is done. In the present embodiment, the intermediate potential is half of the power supply voltage Vdd of the power supply VDD, that is, Vdd / 2. Therefore, in the image display area 10a, the columns of the pixel portions 70 supplied with the intermediate potential signal and the columns of the pixel portions 70 supplied with the HIGH potential signal are alternately arranged.

  The first potential signal is a signal obtained by reading the inspection signal that has been supplied to the pixel unit 70 in advance from the pixel unit 70, and is different from the potential of the inspection signal, that is, the HIGH potential, depending on the malfunction that has occurred in the pixel unit 70. Output with potential. The second potential signal is a signal in which the reference signal previously supplied to the pixel unit 70 is read from the pixel unit 70, and is supplied to the first differential amplifier circuit 15 through the signal line Sei simultaneously with the first potential signal. Supplied. The second potential signal, that is, the potential of the reference signal is output as an intermediate potential. The intermediate potential is a reference potential to be compared when the first differential amplifier circuit 15 determines the level of the potential of the first potential signal. The first potential signal may be a signal supplied to all or a part of the plurality of pixel units 70, and the second potential signal may be a signal supplied from the outside. In this case, since the second signal as the reference signal can be stably supplied from the outside, it is possible to more reliably determine whether the pixel unit 70 is good or bad.

  The equalize circuit 23 includes an equalize signal supply line 43 and a pull-down circuit 33, and a precharge signal for switching on / off of the TFT 11 is supplied to the gate of the TFT 11 via the equalize signal supply line 43. The pull-down circuit 33 reduces fluctuations in the potential of the equalize signal supply line 43.

  The precharge circuit 25 includes a precharge signal supply line 44 electrically connected to the gates of the TFTs 12 a and 12 b and a pull-down circuit 34 electrically connected to the precharge signal supply line 44. The precharge signal supply line 44 is also electrically connected to the equalize signal supply line 43. The precharge signal supply line 44 supplies a precharge signal supplied from the outside to the gates of the TFTs 11, 12a, and 12b through the precharge terminal in order to switch on and off the TFTs 11, 12a, and 12b. The pull-down circuit 34 reduces fluctuations in the potential of the precharge signal supply line 44.

  The voltage application wiring 24 is electrically connected to the source of the TFT 12a and the drain of the 12b, and applies a precharge voltage to the TFTs 12a and 12b. The precharge voltage is set to an intermediate potential in advance and is supplied to the TFTs 12a and 12b. The precharge voltage is supplied to the TFTs 12a and 12b before the first and second potential signals are supplied to the first differential amplifier circuit 15 through the signal lines Soi and Sei, respectively.

  The TFTs 11, 12a, and 12b are switched on by a precharge signal, and the signals such that the potential difference between the signal lines Soi and Sei is reduced before the first and second potential signals are supplied to the signal lines Soi and Sei, respectively. The potentials of the lines Soi and Sei are set. More specifically, the source and drain of the TFT F11, the drain of the TFT 12a, and the source of the TFT 12b are electrically connected to the signal lines Soi and Sei, and a precharge signal is supplied to the gates of the TFTs 11, 12a, and 12b. After that, a precharge voltage is supplied between the source and drain of each of the TFTs 12a and 12b. As a result, a current flows between the source and drain of the TFT 11 and between the source and drain of the TFTs 12a and 12b so that the potential difference between the signal lines Soi and Sei is reduced, and the potentials of the signal lines Soi and Sei are intermediate potentials. Is equal to Therefore, on the premise that the first differential amplifier circuit 15 compares the first and second potential signals, the potentials of the signal lines Soi and Sei supplying these signals to the first differential amplifier circuit 15 can be made uniform.

  When the first and second potential signals are supplied to the first differential amplifier circuit 15 through the signal lines Soi and Sei having the same potential, the first and second potential signals output from the pixel unit 70. The first and second potential signals are supplied to the first differential amplifier circuit 15 while maintaining the potential relationship between the first and second potential signals. Accordingly, it is possible to reduce the fluctuation of the potential relationship between the potential of the first potential signal and the potential of the second potential signal due to the potential difference between the signal lines Soi and Sei, and the potentials of the first potential signal and the second potential signal can be reduced. Reversal of the elevation relationship can be reduced.

  The first differential amplifier circuit first drive signal supply circuit 21 includes a first differential amplifier circuit first drive signal supply line 41 and a pull-up circuit 31. The first drive signal supply line 41 for the first differential amplifier circuit is electrically connected to the gate of the TFT 13p electrically connected to the first differential amplifier circuit 15, and the first drive supplied from the outside. The signal SApE is supplied to the gate of the TFT 13p. The first drive signal SApE is a drive signal for driving the first differential amplifier circuit 15, and as will be described later, the first differential amplifier circuit 15 is a signal input to each of the connection points So and Se. Of these, it functions as a sense amplifier that increases the potential of a signal having a high potential and lowers the potential of a low signal. The TFT 13p is a p-channel TFT, and the TFT 13p is turned on when the first drive signal SApE is supplied to the gate, and supplies the power supply VDD to the connection terminal Sp of the first differential amplifier circuit 15.

  As shown in FIG. 7, the pull-up circuit 31 includes a p-channel TFT 131 whose gate is grounded. The TFT 131 supplies the power VDD to the first drive signal supply line 41 for the first differential amplifier circuit. The pull-up circuit 231 has the same circuit configuration as the pull-up circuit 31.

  The first differential amplifier circuit second drive signal supply circuit 22 includes a first differential amplifier circuit second drive signal supply line 42 and a pull-down circuit 32. The second drive signal supply line 42 for the first differential amplifier circuit is electrically connected to the gate of the TFT 13n electrically connected to the first differential amplifier circuit 15, and the second drive signal supplied from the outside. A signal SAnE is supplied to the gate of the TFT 13n. The TFT 13n is an n-channel TFT and is turned on when the second drive signal SAnE is supplied to the gate, and supplies the power supply VDD to the first differential amplifier circuit 15. The pull-down circuit 32 maintains the potential of the second drive signal supply line 42 for the first differential amplifier circuit.

  One first differential amplifier circuit 15 is provided for each pair of signal lines in which the signal lines Soi and Sei are a pair. When the first transmission gate 6 is turned on, the first and second potential signals are supplied from the signal lines Soi and Sei to the connection points So and Se of the first differential amplifier circuit 15, respectively. The first differential amplifier circuit 15 compares the first and second potential signals to each of the first high potential signal and the first low potential signal via the signal lines Soi and Sei to the test circuit that is a determination unit. Is output.

  The second inspection circuit 204 is provided opposite to the first inspection circuit 4 with respect to the image display area 10a. The second inspection circuit 204 includes a plurality of second differential amplifier circuits 215, a second differential amplifier circuit first drive signal supply circuit 221, and a first differential which constitute an example of the “second amplifier” of the present invention. The second drive signal supply circuit 222 for the amplifier circuit, the second connection circuit 226 which is an example of the “second switching means” of the present invention, the TFTs 213p and 213n, the second transmission gate 206, the plurality of signal lines Soi, and the plurality of signal lines A signal line Sei is provided.

  A plurality of signal lines Soi and Sei extend from the image display region 10a to the second differential amplifier circuit 215, and are electrically connected to the connection points So and Se of the second differential amplifier circuit 215, respectively. Yes. That is, the first differential amplifier circuit 15 and the second differential amplifier circuit 215 are electrically connected to both sides of the image display region 10a in the signal lines Soi and Sei, respectively.

  The second connection circuit 226 has a circuit configuration similar to that of the first connection circuit 26 described above. That is, the second connection circuit 226 includes a second test signal supply line 245 that is electrically connected to the second test circuit via a second test circuit connection gate terminal, and a pull-down circuit 235. The second test signal supply line 245 supplies a series of test signals supplied from the test circuit to the second transmission gate 206 when the pixel unit 70 is inspected. The pull-down circuit 235 stabilizes the potential of the second test signal supply line 245 so that the second test signal supplied to the second transmission gate 206 via the second test signal supply line 245 does not fluctuate.

  Similar to the first transmission gate 6, the second transmission gate 206 is provided in the middle of each of the signal lines Soi and Sei. The second transmission gate 206 is provided on the side close to the second differential amplifier circuit 215 when viewed from the pixel portion 70, and includes a plurality of TFTs 214 electrically connected in the middle of each of the signal lines Soi and Sei. Yes. When the TFT array substrate 10 is inspected, the plurality of TFTs 214 are collectively turned on according to a test signal supplied from the test circuit via the second test signal supply line 245. As a result, it is possible to secure supply paths for the first and second potential signals supplied to the second differential amplifier circuit 215 via the signal lines Soi and Sei, respectively. In the pixel unit 70 described above with reference to FIG. If the provided TFT 71 is switched to the ON state, the first potential signal and the second potential signal are collectively transmitted from each pixel unit 70 to each second differential amplifier circuit 215 via each of the signal lines Soi and Sei. Can supply.

  The first drive signal supply circuit 221 for the second differential amplifier circuit has a circuit configuration similar to that of the first drive signal supply circuit 21 for the first differential amplifier circuit. That is, the second differential amplifier circuit first drive signal supply circuit 221 includes a second differential amplifier circuit first drive signal supply line 241 and a pull-up circuit 231. The first drive signal supply line 241 for the second differential amplifier circuit is electrically connected to the gate of the TFT 213p that is electrically connected to the second differential amplifier circuit 215, and the first drive signal supplied from the outside. The signal SApE is supplied to the gate of the TFT 213p. Similar to the first differential amplifier circuit 15, the second differential amplifier circuit 215 increases the potential of a signal having a high potential among the signals input to the connection points So and Se, and increases the potential of a low signal. It functions as a sense amplifier that lowers the frequency. The TFT 213p is a p-channel TFT, and the TFT 213p is turned on when the first drive signal SApE is supplied to the gate, and supplies the power supply VDD to the connection terminal Sp of the second differential amplifier circuit 215. The pull-up circuit 231 supplies the power VDD to the second differential amplifier circuit first drive signal supply line 241.

  The second drive signal supply circuit 222 for the second differential amplifier circuit has a circuit configuration similar to that of the second drive signal supply circuit 22 for the first differential amplifier circuit. That is, the second drive signal supply circuit 222 for the second differential amplifier circuit includes a second drive signal supply line 242 for the second differential amplifier circuit and a pull-down circuit 232. The second drive signal supply line 242 for the second differential amplifier circuit is electrically connected to the gate of the TFT 213n that is electrically connected to the second differential amplifier circuit 215, and the second drive signal supplied from the outside. A signal SAnE is supplied to the gate of the TFT 213n. The TFT 213n is an n-channel TFT, which is turned on when the second drive signal SAnE is supplied to the gate, and supplies the power supply VDD to the second differential amplifier circuit 215. The pull-down circuit 232 maintains the potential of the second drive signal supply line 242 for the second differential amplifier circuit.

  Similar to the first differential amplifier 15, one second differential amplifier circuit 215 is provided for each signal line pair including the signal line Soi and the signal line Sei. When the second transmission gate 206 is turned on, the first and second potential signals are supplied from the signal lines Soi and Sei to the connection points So and Se of the second differential amplifier circuit 215, respectively. The second differential amplifier circuit 215 compares the first potential signal and the second potential signal to the test circuit that is a determination unit via each of the signal lines Soi and Sei, and outputs the second high potential signal or the second low potential signal. Outputs a potential signal.

  Next, the configuration of the first and second differential amplifier circuits will be described in detail with reference to FIG. FIG. 8 is a circuit diagram showing an electrical configuration of the first differential amplifier circuit. The second differential amplifier circuit 215 has a circuit configuration similar to that of the first differential amplifier circuit. Hereinafter, the description of the configuration of the second differential amplifier circuit 215 will be omitted as appropriate.

  In FIG. 8, the first differential amplifier circuit 15 is a cross-coupled differential amplifier circuit including p-channel TFTs 51 and 52 and n-channel TFTs 53 and 54. More specifically, a series circuit in which the TFTs 51 and 52 are electrically connected in series and a series circuit in which the TFTs 53 and 54 are electrically connected in series are electrically connected in parallel. The gate of the TFT 51 is electrically connected to the connection point So between the TFTs 52 and 54. The gate of the TFT 52 is electrically connected to the connection point Se between the TFTs 51 and 53. The gate of the TFT 53 is electrically connected to the connection point So between the TFTs 52 and 54. The gate of the TFT 54 is electrically connected to the connection point Se between the TFTs 51 and 53. The connection point So is electrically connected to the signal line Soi, and the connection point Se is electrically connected to the signal line Sei. The connection point Sp between the TFTs 51 and 52 is electrically connected to the drain of the TFT 13p. A connection point Sn between the TFTs 53 and 54 is electrically connected to the drain of the TFT 13n. In the second differential amplifier circuit 215, the connection point Se is electrically connected to the drain of the TFT 213p. The connection point Sn is electrically connected to the drain of the TFT 213n.

  When the first potential signal has a slightly higher potential than the second potential signal, the first differential amplifier circuit 15 outputs the first high potential signal whose potential is higher than that of the first potential signal. The signal is output to a test circuit which is a determination means via the signal line Soi. Thus, according to the first high potential signal whose potential has been increased, it is possible to clarify that the potential of the first potential signal is higher than the potential of the second potential signal. When the first potential signal has a slightly lower potential than the second potential signal, the first differential amplifier circuit 15 has a first low potential signal whose potential is lower than that of the first potential signal. Is output via the signal line Soi. According to such a first low potential signal, it is possible to clarify that the potential of the first potential signal is lower than the potential of the second potential signal.

  The second potential signal supplied to the first differential amplifier circuit 15 via the signal line Sei is a reference potential that serves as a reference when the potential of the first potential signal is increased or decreased. The first potential signal is a signal that reflects whether or not the pixel portion 70 electrically connected to the signal line Soi has a defect, that is, the quality of the pixel portion 70, and the second potential signal and the first potential signal. Is slightly smaller than the potential that fluctuates depending on the wiring capacitance of these signal lines. The first differential amplifier circuit 15 outputs the first high potential signal or the first low potential signal so that the level relationship between the potential of the first potential signal and the second potential signal can be clearly determined.

  Similar to the first differential amplifier circuit 15, the second differential amplifier circuit 215 is configured to output the second high potential signal or the second potential signal so that the level relationship between the potential of the first potential signal and the potential of the second potential signal can be clearly determined. 2 Outputs a low potential signal.

  Next, the operation principle of the test circuit will be described with reference to FIG. 3 again. In order to simplify the description, the operation principle of the test circuit based on the first high potential signal or the first low potential signal output from the first differential amplifier circuit 15 will be described here. The test circuit operates similarly based on the second high potential signal or the second high potential signal output from the second differential amplifier circuit 215.

  A test circuit (not shown in FIG. 3) determines whether or not a defect has occurred in the pixel portion 70 electrically connected to the signal line Soi based on voltage logic. That is, the test circuit compares the potential of the inspection signal that is the source of the first potential signal supplied to the pixel unit 70 in advance with respect to the potential of the second potential signal, and the potential of the intermediate potential and the first high potential signal. Alternatively, it is determined whether or not a defect has occurred in the pixel unit 70 by comparing with information on the level of the potential of the first low potential signal. More specifically, if the first high potential signal is output from the first differential amplifier circuit 15 when the potential of the inspection signal that is the source of the first potential signal is higher than the intermediate potential, the signal line Soi is electrically connected. The test circuit determines that a defect has not occurred in the pixel unit 70 connected to the pixel unit 70, that is, the pixel unit 70 to which the inspection signal that is the basis of the first potential signal is supplied. Similarly, if the first low potential signal is output from the first differential amplifier circuit 15 when the potential of the inspection signal that is the source of the first potential signal is lower than the potential of the second potential signal, the first signal line is connected to the first signal line. The test circuit determines that there is no malfunction in the pixel portion 70 that is electrically connected, that is, the pixel portion 70 to which the inspection signal that is the source of the first potential signal is supplied.

  If the first low-potential signal is output from the first differential amplifier circuit 15 when the potential of the inspection signal that is the basis of the first potential signal is higher than the potential of the second potential signal, the first differential signal is electrically connected to the signal line Soi. The test circuit determines that some malfunction has occurred in the pixel unit 70 that has been supplied, that is, the pixel unit 70 to which the inspection signal that is the basis of the first potential signal has been supplied. If the high potential signal is output from the differential amplifier circuit 15 when the potential of the inspection signal that is the basis of the first potential signal is lower than the potential of the second potential signal, the pixel unit 70 that is electrically connected to the signal line Soi. That is, the test circuit determines that some trouble has occurred in the pixel unit 70 to which the inspection signal that is the basis of the first potential signal is supplied.

  Next, referring to FIGS. 3 and 8, the procedure in which the first differential amplifier circuit outputs the first high potential signal or the first low potential signal and the second differential amplifier circuit has the second high potential signal or the first high potential signal. (2) A procedure for outputting a low potential signal will be described. Here, a case where a first potential signal having a higher potential than the potential of the second potential signal having an intermediate potential is supplied to the first differential amplifier circuit 15 and the second differential amplifier circuit 215 will be described as an example. explain. The procedure for the second differential amplifier circuit 215 to output the second high potential signal or the second low potential signal is the procedure for the first differential amplifier circuit to output the first high potential signal or the first low potential signal. It is the same. Hereinafter, description of the procedure in which the second differential amplifier circuit 215 outputs the second high potential signal or the second low potential signal will be omitted as appropriate.

  3 and 8, when the second drive signal SAnE is supplied from the first differential amplification circuit second drive signal supply circuit 22 to the TFT 13n, the TFT 13n is turned on, and the connection point Sn is connected via the TFT 13n. Approaches the ground potential. Since the source potential of the TFT 53 is set to an intermediate potential, a current flows between the source and drain of the TFT 53, and the potential of the connection point Se decreases. At this time, since the gate of the p-channel TFT 52 is electrically connected to the connection point Se, the TFT 52 is switched to the on state when the potential at the connection point Se decreases. When the first drive signal SApE is supplied from the first drive signal supply circuit 21 for the first differential amplifier circuit to the TFT 13p, the TFT 13p is turned on, and the power supply VDD is supplied to the connection point Sp via the TFT 13p. . Thereby, the power supply VDD is supplied to the connection point So through the TFTs 13p and 52, and the potential of the connection point So is increased.

  In this way, the first differential amplifier circuit 15 raises the potential of the first potential signal and lowers the potential of the second potential signal. According to the first differential amplifier circuit 15, when the first potential signal is higher than the intermediate potential, the first potential signal is output to the determination means such as the first test circuit as the first high potential signal having a higher potential. it can. Accordingly, the determination means such as the first test circuit can clearly determine the level relationship between the reference signal having a potential lower than the intermediate potential and the first high potential signal, and determines whether the pixel unit 70 is good or bad based on the voltage logic. Can be judged.

  When the potential of the first potential signal is lower than the potential of the second potential signal, the TFTs 51 and 54 operate in the same manner as the TFTs 52 and 53 described above, and the first low potential signal is output based on the first potential signal. . In this case, the second potential signal set to the intermediate potential is output as the first reference signal with the increased potential, and the first potential signal has a potential lower than that of the first reference signal. It is output as a potential signal. The first reference signal is a signal output from the first differential amplifier circuit 215 based on the second potential signal.

  Similarly to the first differential amplifier circuit 15, the second differential amplifier circuit 215 increases the potential of the first potential signal and decreases the potential of the second potential signal. According to the second differential amplifier circuit 215, when the first potential signal is higher than the intermediate potential, the first potential signal can be output to a determination unit such as a test circuit as a second high potential signal having a higher potential. Therefore, the determination means such as a test circuit can clearly determine the level relationship between the reference signal having a potential lower than the intermediate potential and the second high potential signal, and can determine the quality of the pixel unit 70 based on the voltage logic. .

  When the potential of the first potential signal is lower than the potential of the second potential signal, the first low potential signal is output based on the first potential signal, similarly to the first differential amplifier circuit 15. In this case, the second potential signal set to the intermediate potential is output as a second reference signal having an increased potential, and the first potential signal has a potential lower than that of the reference signal. Is output as The second reference signal is a signal output from the second differential amplifier circuit 215 based on the second potential signal.

  As described above, in this embodiment, in particular, the second differential amplifier circuit 215 is further provided in addition to the first differential amplifier circuit 15. In other words, the second differential amplifier circuit 215 is further provided corresponding to each of the sets of the signal lines Soi and Sei and on the opposite side of the image display area 10a from the first differential amplifier circuit 15. . Similar to the first differential amplifier circuit 15, the second differential amplifier circuit 215 determines whether the pixel unit 70 is good by using the second high potential signal or the second low potential signal via one signal line Soi. Output to the circuit.

  The second differential amplifier circuit 215 can input, in other words, detect the first potential signal and the second potential signal from the opposite side of the first differential amplifier circuit 15 with respect to the image display region 10a. The first and second potential signals can be detected at a higher speed than when only one differential amplifier circuit 15 is used. For example, the first and second pixels from the pixel unit 70 provided in the region opposite to the first differential amplifier circuit 15 in the image display region 10 a, that is, in a region away from the first differential amplifier circuit 15. The potential signal can also be detected by the second differential amplifier circuit 215. Since the pixel unit 70 located in a region away from the first differential amplifier circuit 15 is closer to the second differential amplifier circuit 215, the first and second potential signals from the pixel unit 70 are the second differential signal. The amplifier circuit 215 can perform detection at a higher speed than the case using only the first differential amplifier circuit 15. That is, the quality of the pixel unit 70 can be determined at high speed by the test circuit based on the second high potential signal or the second low electron signal in addition to the first high potential signal or the first low potential signal. On the other hand, the pixel unit 70 located in a region away from the second differential amplifier circuit 215 is determined only by the second differential amplifier circuit 215 by the test circuit based on the first high potential signal or the first low potential signal. The quality of the pixel unit 70 can be determined at a higher speed than the case. Therefore, the first differential amplifier circuit 15 and the second differential amplifier circuit 215 can determine whether the pixel unit 70 in the image display region 10a is good or not at high speed.

  As described above, according to the liquid crystal device of the present embodiment, it is not necessary to contact an external probe, and an inspection with sufficient measurement accuracy can be performed. Further, the first and second potential signals from any pixel unit 70 in the image display region 10a can be detected accurately and at high speed, and the quality of the pixel unit 70 can be determined accurately and in a short time. Accordingly, the yield of the liquid crystal device can be increased, and the manufacturing cost can be reduced.

  Next, referring to FIG. 9, the first differential amplifier circuit 15 and the second differential amplifier circuit 215 are connected to the first or second high potential signal or the first or second low signal via the signal lines Soi and Sei. The timing of various signals when outputting a potential signal will be described. FIG. 9 is a timing chart showing timings for outputting various signals via the signal lines Soi and Sei. In FIG. 9, the pixel unit 70 corresponding to the signal line Soi is an inspection target, and the pixel unit 70 corresponding to the signal line Sei is used as a reference. That is, as described above with reference to FIG. 6, in the image display region 10a, the columns of the pixel portions 70 to which the intermediate potential signal is supplied and the columns of the pixel portions 70 to which the HIGH potential signal is supplied are alternately arranged. Take the case where it becomes a state.

  In FIG. 9, the inspection signal and the reference signal are supplied to the pixel unit 70 by the timing t1. That is, as described above with reference to FIG. 6, in the image display region 10a, the columns of the pixel portions 70 to which the intermediate potential signal is supplied and the columns of the pixel portions 70 to which the HIGH potential signal is supplied are alternately arranged. It is in the state. The precharge circuit 25 supplies the precharge signal PCG to the gates of the TFTs 11, 12a and 12b via the precharge signal supply line 44 at timing t1. The TFTs 11, 12 a and 12 b are turned on, and a precharge voltage is applied to the signal lines Soi and Sei via the voltage application wiring 24. Thereby, the potentials of the signal lines Soi and Sei are set to the intermediate potential. Thereafter, the precharge circuit 25 ends the supply of the precharge signal PCG at the timing t2.

  After the first transmission gate 6 and the second transmission gate 206 are switched on, the scanning line G1 supplies a switching signal to the pixel unit 70 at the timing t3, and the first and second potential signals are the signal lines, respectively. The signals are supplied to the first differential amplifier circuit 15 and the second differential amplifier circuit 215 via Soi and Sei. Note that the scanning line G1 supplies a switching signal to all the pixel portions 70 electrically connected to the scanning line G1, and the TFT 71 included in the pixel portion 70 electrically connected to the scanning line G1 is switched on. It is done. The first and second potential signals are transmitted from each of the plurality of pixel portions 70 electrically connected to the scanning line G1 to the first differential amplification circuit 15 and the second differential amplification circuit 215 corresponding to the pixel portions 70. Supplied.

  Here, when there is no malfunction in the pixel portion 70, the first potential signal having a potential higher than the intermediate potential, that is, the HIGH potential, is applied to the signal line in the same manner as the potential of the inspection signal previously supplied to the pixel portion 70. The voltage is supplied to the first differential amplifier circuit 15 and the second differential amplifier circuit 215 via the Soi. At this time, the first potential signal has a potential slightly higher than the intermediate potential. The potential of the signal line Sei that outputs the second potential signal is a preset intermediate potential, which is slightly lower than the potential of the first potential signal. As described above, when there is no problem in the pixel unit 70, the level relationship between the potential of the inspection signal and the intermediate potential supplied in advance to the pixel unit 70 is the potential of the first potential signal and the second potential. The signal potential level is maintained as it is.

  When the second drive signal SAnE is supplied from the second drive signal supply circuit 22 for the first differential amplifier circuit to the TFT 13n at the timing t4, the first differential amplifier circuit 15 lowers the potential of the signal line Sei. As a result, the potential of the connection point Se having a lower potential than the potential of the connection point So to which the first potential signal is supplied is lowered to a potential lower than that at the time of supplying the second potential signal. Similarly, when the second drive signal SAnE is supplied from the second drive signal supply circuit 222 for the second differential amplifier circuit to the TFT 213n at the timing t4, the second differential amplifier circuit 215 decreases the potential of the signal line Sei. . As a result, the potential of the connection point Se having a lower potential than the potential of the connection point So to which the first potential signal is supplied is lowered to a potential lower than that at the time of supplying the second potential signal.

  At timing t5, when the first drive signal SApE is supplied from the first drive signal supply circuit 21 for the first differential amplifier circuit to the TFT 13p, the first differential amplifier circuit 15 is connected to the first potential signal. The potential of So is increased from the potential at the time when the second potential signal is supplied. Similarly, when the first drive signal SApE is supplied from the first drive signal supply circuit 221 for the second differential amplifier circuit to the TFT 213p at timing t5, the first potential signal is supplied to the second differential amplifier circuit 215. The potential at the connection point So is made higher than the potential at the time when the second potential signal is supplied.

  At each of timings t4 and t5, the potential of the connection point Se to which the second potential signal having a low potential among the signals supplied to the first differential amplifier circuit 15 is supplied is lowered to a lower value. The potential at the connection point So to which the one-potential signal is supplied is raised higher. Thereby, the level relationship of the potentials of the connection points So and Se becomes clear. The first differential amplifier circuit 15 outputs a first high potential signal having the potential of the connection point So to a determination unit such as a test circuit via the signal line Soi. At the same time, the first differential amplifier circuit 15 outputs a reference signal having the potential of the connection point Se to the determination means such as a test circuit via the signal line Sei. Similarly, the second differential amplifier 215 outputs a second high potential signal having the potential at the connection point So to a determination unit such as a test circuit via the signal line Soi. At the same time, the second differential amplifier circuit 215 outputs a reference signal having the potential of the connection point Se to a determination unit such as a test circuit via the signal line Sei.

  The test circuit compares the first high potential signal and the first reference signal. Since the potential of the first high potential signal is higher than that of the first potential signal, and the potential of the first reference signal is lower than the intermediate potential, the test circuit uses the second potential signal and the second potential signal. It can be clearly determined that the potential of the first high potential signal is higher than the potential of the first reference signal as compared to the case of comparing the first potential signal having a slightly higher potential. Similarly, it can be clearly determined that the potential of the second high potential signal is higher than the potential of the second reference signal. Here, the level relationship between the potential of the inspection signal and the intermediate potential matches the level relationship between the potential of the first high potential signal and the potential of the first reference signal or the potential of the first high potential signal and the second reference signal. Therefore, the test circuit determines that there is no defect in the pixel unit 70 to be inspected.

  Next, in order to determine whether the pixel portion electrically connected to the scanning line G2 is good or bad, a precharge voltage is supplied to the signal lines Soi and Sei between timings t6 and t7, and these signal lines are again set to the intermediate potential. Set to

  At timing t8, the scanning line G2 outputs a switching signal, and the switching signal is supplied to the pixel portion 70 that is electrically connected to the scanning line G2. The pixel unit 70 supplied with the switching signal transmits the first potential signal to the first differential amplifier circuit 15 and the second differential signal via the signal line Soi in the same manner as the pixel unit 70 electrically connected to the scanning line G1. Output to the amplifier circuit. At this time, the signal line Sei supplies the second potential signal to the first differential amplifier circuit 15 and the second differential amplifier circuit 215. Accordingly, the first high potential signal or the first low potential corresponding to the pixel portion 70 electrically connected to the scanning line G2 among the pixel portions 70 electrically connected to the signal line Soi in the same manner as the scanning line G1. The potential signal and the first and second reference signals are output from the differential amplifier circuit to the test circuit via each signal line, and the quality of the pixel unit 70 electrically connected to the scanning line G2 can be determined. In this way, it is possible to sequentially determine the quality of the pixel portion electrically connected to each of the scanning lines G3, G4,..., Gn. In addition, as already described, the first high potential signal or the first low potential signal output from each first differential amplifier circuit 15 and the first reference signal are supplied to the differential amplifier circuit 15 via the sampling circuit 110. Since it is possible to output to the test circuit every time, it is possible to determine pass / fail for each pixel unit 70, and that there is no defect in each of the plurality of pixel units 70 arranged in the image display area 10a. I can confirm.

  Next, with reference to FIG. 9, a case where a defect occurs in the pixel portion will be described.

  As described above with reference to FIG. 6, the pixel unit 70 includes, in the image display region 10 a, a column of pixel units 70 to which an intermediate potential signal is supplied and a pixel to which a HIGH potential signal (that is, an inspection signal) is supplied. The rows of the sections 70 are arranged alternately. At timing t <b> 3 when the switching signal is supplied from the scanning line G <b> 1 to the pixel unit 70, the pixel unit 70 supplies a first potential signal having a potential slightly lower than the intermediate potential to the first differential amplifier circuit 15. Note that the potential of the connection point So to which the first potential signal having a potential lower than the intermediate potential is supplied is L0 indicated by a dotted line in the drawing. Here, the first potential signal has a potential lower than the intermediate potential when, for example, the pixel portion 70 includes a TFT in which current leakage occurs or a storage capacitor 73 in which current leakage occurs. Equivalent to. Similarly, the pixel unit 70 also supplies a first potential signal having a potential slightly lower than the intermediate potential to the second differential amplifier circuit 215. Here, in particular, the time until the first potential signal is supplied from the pixel unit 70 to the first differential amplifier circuit 15 and the second differential amplifier circuit 215 corresponds to any region in the image display region 10a. It depends on whether it is located in. That is, when the distance between the pixel unit 70 and the second differential amplifier circuit 215 is shorter than the distance between the pixel unit 70 and the first differential amplifier circuit 15 in plan view on the TFT array substrate 10. In other words, the first potential signal is supplied to the second differential amplifier circuit 215 in a shorter time than that supplied to the first differential amplifier circuit 15. Conversely, when viewed in plan on the TFT array substrate 10, the distance between the pixel unit 70 and the first differential amplifier circuit 15 is greater than the distance between the pixel unit 70 and the second differential amplifier circuit 215. Is shorter than the second differential amplifier circuit 215, the first potential signal is supplied to the first differential amplifier circuit 15 in a shorter time. Therefore, the pixel unit 70 located in any region of the image display region 10a can be transferred to the first differential amplifier circuit 15 or the second differential amplifier circuit 215 in a shorter time than the case of using only one differential amplifier circuit. A first potential signal can be supplied.

When the second drive signal SAnE is supplied from the second drive signal supply circuit 22 for the first differential amplifier circuit to the TFT 13n at the timing t4, the first differential amplifier circuit 15 has a first potential lower than the intermediate potential. The potential of the connection point So to which the potential signal is supplied is lowered to a lower potential (indicated by a dotted line L1 in the figure). More specifically, the potential of the first potential signal supplied to the connection point So of the first differential amplifier circuit 15 is equal to the potential of the second potential signal supplied to the connection point Se of the first differential amplifier circuit 15. Since it is slightly lower, the first differential amplifier circuit 15 compares the potentials of the first potential signal and the second potential signal, and lowers the potential of the signal line Soi to a lower potential. The first differential amplifier circuit 15 outputs a low potential signal having a potential equal to the potential at the connection point So. Similarly, for the second differential amplifier circuit 215, when the second drive signal SAnE is supplied from the second drive signal supply circuit 222 for the second differential amplifier circuit to the TFT 213n, the second differential amplifier circuit 215 becomes intermediate. The potential of the connection point So to which the first potential signal having a potential lower than the potential is supplied is lowered to a lower potential (indicated by a dotted line L1 in the figure). More specifically, the potential of the first potential signal supplied to the connection point So of the second differential amplifier circuit 15 is the second differential amplifier circuit 21.
5 is slightly lower than the potential of the second potential signal supplied to the connection point Se, the second differential amplifier circuit 215 compares the potentials of the first potential signal and the second potential signal and determines the potential of the signal line Soi. Lower to a lower potential. The second differential amplifier circuit 215 outputs a low potential signal having a potential equal to the potential at the connection point So.

  At timing t5, when the first drive signal SApE is supplied from the first drive signal supply circuit 21 for the first differential amplifier circuit to the TFT 13p, the differential amplifier circuit 15 increases the potential of the second potential signal. Since the potential of the connection point Se is higher than the potential of the connection point So lowered by the first differential amplifier circuit 15, the first differential amplifier circuit 15 sets the potential of the connection point Se higher than the intermediate potential. Increase to potential. The first differential amplifier circuit 15 outputs a first reference signal having a potential equal to the potential of the connection point Se whose potential is higher than the intermediate potential. When the first drive signal SApE is supplied from the first drive signal supply circuit 221 for the second differential amplifier circuit to the TFT 213p, the second differential amplifier circuit 215 increases the potential of the second potential signal. Since the potential of the connection point Se is higher than the potential of the connection point So lowered by the second differential amplifier circuit 215, the first differential amplifier circuit 215 makes the potential of the connection point Se higher than the intermediate potential. Increase to potential. The second differential amplifier circuit 215 outputs a second reference signal having a potential equal to the potential of the connection point Se whose potential is higher than the intermediate potential.

  As a result, in the test circuit, the first or second low potential signal and the first or second low potential signal and the first potential signal and the second potential signal, which are supplied to the signal line Soi and the signal line Sei, are maintained. A second reference signal is detected. The test circuit can clearly detect that the potential of the first potential signal is lower than the intermediate potential by detecting the first or second low potential signal whose potential is lowered from the first potential signal. The level relationship between the first low potential signal and the intermediate potential is opposite to the level relationship between the potential of the inspection signal and the potential of the intermediate potential. In such a case, the test circuit has a problem in the pixel unit 70. Is determined.

  As described above, according to the liquid crystal device of the present embodiment, the first or second high potential signal whose potential is compared in the test circuit with the level relationship between the potential of the inspection signal and the intermediate potential supplied to the pixel unit 70 in advance. Alternatively, it is determined whether or not there is a malfunction in the pixel unit 70 by determining whether or not the potential relationship of the first or second low potential signal and the potential of the first or second reference signal match. it can. Furthermore, the first and second potential signals from the pixel unit 70 located in any region in the image display region 10a can be detected accurately and at high speed, and the quality of the pixel unit 70 can be determined accurately and in a short time. Accordingly, the yield of electro-optical devices such as liquid crystal devices can be increased, and the manufacturing cost can be reduced.

(Electronics)
Next, the case where the liquid crystal device which is the above-described electro-optical device is applied to various electronic devices will be described.

  First, a projector using this liquid crystal device as a light valve will be described. FIG. 10 is a plan view showing a configuration example of the projector. As shown in FIG. 10, a projector 1100 includes a lamp unit 1102 made of a white light source such as a halogen lamp. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by four mirrors 1106 and two dichroic mirrors 1108 arranged in the light guide 1104, and serves as a light valve corresponding to each primary color. The light enters the liquid crystal panels 1110R, 1110B, and 1110G.

  The configurations of the liquid crystal panels 1110R, 1110B, and 1110G are the same as those of the liquid crystal device described above, and are driven by R, G, and B primary color signals supplied from the image signal processing circuit. The light modulated by these liquid crystal panels enters the dichroic prism 1112 from three directions. In this dichroic prism 1112, R and B light is refracted at 90 degrees, while G light travels straight. Accordingly, as a result of the synthesis of the images of the respective colors, a color image is projected onto the screen or the like via the projection lens 1114.

  Here, paying attention to the display images by the liquid crystal panels 1110R, 1110B, and 1110G, the display image by the liquid crystal panel 1110G needs to be horizontally reversed with respect to the display images by the liquid crystal panels 1110R, 1110B.

  Note that since light corresponding to the primary colors R, G, and B is incident on the liquid crystal panels 1110R, 1110B, and 1110G by the dichroic mirror 1108, it is not necessary to provide a color filter.

  Next, an example in which the liquid crystal device is applied to a mobile personal computer will be described. FIG. 11 is a perspective view showing the configuration of the personal computer. In FIG. 11, the computer 1200 includes a main body 1204 provided with a keyboard 1202 and a liquid crystal display unit 1206. The liquid crystal display unit 1206 is configured by adding a backlight to the back surface of the liquid crystal device 1005 described above.

  Further, an example in which the liquid crystal device is applied to a mobile phone will be described. FIG. 12 is a perspective view showing the configuration of this mobile phone. In FIG. 12, a mobile phone 1300 includes a reflective liquid crystal device 1005 together with a plurality of operation buttons 1302. In the reflective liquid crystal device 1005, a front light is provided on the front surface thereof as necessary.

  In addition to the electronic devices described with reference to FIGS. 10 to 12, a liquid crystal television, a viewfinder type, a monitor direct view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, a word processor, a work Examples include a station, a videophone, a POS terminal, a device equipped with a touch panel, and the like. Needless to say, the present invention can be applied to these various electronic devices.

  In addition to the liquid crystal device described in the above embodiment, the present invention also includes a reflective liquid crystal device (LCOS) in which elements are formed on a silicon substrate, a plasma display (PDP), a field emission display (FED, SED), It can also be applied to an organic EL display or the like.

  The present invention is not limited to the above-described embodiments, and can be appropriately changed without departing from the spirit or concept of the invention that can be read from the claims and the entire specification. An electronic apparatus including the electro-optical device is also included in the technical scope of the present invention.

It is a top view which shows the whole structure of a liquid crystal device. It is sectional drawing of HH 'of FIG. It is the block diagram which showed the main circuit structures of the liquid crystal device. It is a circuit diagram which shows the electrical structure of a pixel part. It is a circuit diagram which shows the electric constitution of a pull-down circuit. It is a conceptual diagram which shows the state of the pixel part to which the signal was supplied previously at the time of an inspection. It is a circuit diagram which shows the electrical structure of a pull-up circuit. It is a circuit diagram which shows the electrical structure of a 1st differential amplifier circuit. It is a timing chart which showed the timing which various signals output at the time of inspection of a liquid crystal device. It is a top view which shows the structure of the projector which is an example of the electronic device to which the electro-optical apparatus is applied. 1 is a perspective view showing a configuration of a personal computer as an example of an electronic apparatus to which an electro-optical device is applied. It is a perspective view which shows the structure of the mobile telephone which is an example of the electronic device to which the electro-optical apparatus is applied.

Explanation of symbols

  9a ... pixel electrode, 4 ... first inspection circuit, 6 ... first transmission gate, 10 ... TFT array substrate, 10a ... image display area, 15 ... first differential amplifier circuit, 20 ... counter substrate, 25 ... precharge circuit DESCRIPTION OF SYMBOLS 50 ... Liquid crystal layer 70 ... Pixel part 73 ... Storage capacity 101 ... X-driver circuit 104 ... Y- driver circuit 110 ... Sampling circuit 204 ... Second inspection circuit 215 ... Second differential amplifier circuit 206, second transmission gate, Gj, scanning line, Soi, Sei, signal line

Claims (7)

On the board
A plurality of scanning lines and a plurality of signal lines arranged to cross each other in the pixel array region;
A plurality of pixel portions provided corresponding to intersections of the plurality of signal lines and the plurality of scanning lines;
The plurality of signal lines are provided corresponding to each of a plurality of signal line sets each including two signal lines, and one of the two signal lines is interposed via one signal line. And a second potential signal as a reference potential is supplied via the other signal line of the two signal lines, and (i) the potential of the first potential signal is the first potential signal. When the potential is lower than the potential of the two-potential signal, the first low-potential signal having a potential lower than the potential of the first potential signal is transmitted through the one signal line, and (ii) the potential of the first potential signal is A plurality of first amplifying means for outputting a first high potential signal having a potential higher than the potential of the first potential signal via the one signal line when the potential is higher than the potential of the second potential signal;
Corresponding to each set of the plurality of signal lines and provided on the opposite side of the pixel array region from the first amplification means, the first potential signal is transmitted through the one signal line. And the second potential signal is supplied via the other signal line, and (i) when the potential of the first potential signal is lower than the potential of the second potential signal, the one signal line A second low potential signal having a potential lower than the potential of the first potential signal via (ii) the one signal when the potential of the first potential signal is higher than the potential of the second potential signal; And a plurality of second amplifying means for outputting a second high potential signal having a potential higher than the potential of the first potential signal via a line. The first potential signal is a signal supplied to all or part of the plurality of pixel portions,
The electro-optical device according to claim 1, wherein the second potential signal is a signal supplied from the outside.   Each of the plurality of first and the plurality of second amplifying means includes a plurality of differential amplifier circuits electrically connected one by one for each set of the plurality of signal lines. The electro-optical device according to claim 1.   4. The electro-optical device according to claim 1, wherein each of the plurality of pixel units has a storage capacitor. 5.   5. The electro-optical device according to claim 1, further comprising a precharge circuit that is electrically connected to the plurality of signal lines and precharges the plurality of pixel portions. 6. . A first transmission gate provided in a region near the first amplifying means when viewed from the pixel portion on the substrate surface of the substrate, and electrically connected in the middle of the set of two signal lines;
First switching means for switching on and off the first transmission gate;
A second transmission gate that is provided in a region near the second amplifying means when viewed from the pixel portion on the substrate surface of the substrate, and is electrically connected in the middle of the pair of signal lines;
And second switching means for switching the second transmission gate on and off,
The first potential signal and the second potential signal are transmitted to the first amplifying unit via the pair of signal lines in a state where the first transmission gate is switched on by the first switching unit. The second transmission gate is supplied to the second amplifying means via the signal line of two sets in a state where the second transmission gate is turned on by the second switching means. Item 6. The electro-optical device according to any one of Items 1 to 5. An electronic apparatus comprising the electro-optical device according to claim 1.

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