JP2006323044A - Substrate for electrooptical apparatus, electrooptical apparatus with same, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To detect whether one pixel section is nondefective or not, without being affected by other pixel sections, and to consistently determine whether the pixel section is nondefective or not, even if noise is applied. <P>SOLUTION: The pixel section 70 is provided one each for an intersection area Pji where a pair of signal lines Soi and Sei intersect with one scanning line. The pixel section 70 is electrically connected to only a first signal line Soi which is selected as one signal line in the signal line Soi and the signal line Sei included in a signal line group Pji. A second potential signal having a middle potential is supplied to a differential amplifier circuit 15 via the signal line Sei to which the pixel section is not electrically connected in the intersection area Pji. Consequently, the second potential signal is kept in the middle potential, without being affected by whether the pixel section is nondefective or not, and based on the second potential signal and the first potential signal output from the pixel section, the pixel section is correctly determined to be nondefective or not. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention is a substrate for use in an electro-optical device such as a liquid crystal device, and includes an electro-optical device substrate on which a semiconductor element such as a TFT for driving an electro-optical element such as a liquid crystal is formed, and the same The present invention relates to the technical field of electro-optical devices and electronic devices.

  An electro-optical device such as a liquid crystal device includes a step of inspecting a substrate for an electro-optical device such as a TFT array substrate on which a thin film transistor (hereinafter referred to as “TFT”) is formed, a TFT array substrate, a liquid crystal, and the like. And a step of enclosing a liquid crystal between opposing substrates on which an opposing electrode for driving the electro-optical element is formed. The inspection of whether or not the finished liquid crystal device operates normally is performed based on whether or not the image displayed by the completed liquid crystal device is correctly displayed. In such an electro-optical device, if a defect of the TFT formed on the TFT array substrate is not detected in the process of inspecting the TFT array substrate, the defect is detected by the inspection performed on the liquid crystal device which is the finished product. Will be.

  As countermeasures when a defect is detected in the finished liquid crystal device, measures such as exchanging the TFT array substrate after repairing the liquid crystal from the liquid crystal device or repairing the defective part can be considered. These measures are practically difficult to adopt in view of a decrease in yield and an increase in cost when manufacturing the product. In addition, the process after forming the TFT array substrate becomes a useless process, and there is a problem in that the yield is reduced and the cost is increased when manufacturing an electro-optical device such as a liquid crystal device.

  As one means for solving such a problem, for example, Patent Document 1 discloses that a pixel corresponds to every intersection of two signal lines and scanning lines electrically connected to a comparator in a pixel array. Disclosed is a technique for inspecting whether or not a pixel is defective by comparing potential information supplied to two pixels when the electro-optical device substrate is formed.

JP 2004-226551 A

  However, according to the technique disclosed in Patent Document 1, when a pixel arranged in a region where one signal line and a scanning line intersect between two signal lines electrically connected to a comparator is inspected The potentials of the signals supplied to the pixels arranged in the region where the other signal line and the scanning line intersect with each other become the reference potential, and the reference potential fluctuates due to a defect in the pixel on the reference potential side. As a result, it is determined that there is a defect in a normal pixel to be inspected, and there is a technical problem that a defect of one pixel is detected as a defect of two pixels. In addition, there is a problem that it is difficult to electrically detect what kind of trouble occurs in which part of a semiconductor element such as a TFT or a capacitor included in one pixel.

  A method of judging the quality of the pixel by comparing the potential of the signal line on the reference potential side and the potential of the signal line to which the pixel to be inspected is electrically connected after being amplified by, for example, a differential amplifier is also considered. It is done. However, when noise is applied to a signal line that is electrically connected to a pixel to be inspected or a signal line that is maintained at a reference potential, the level relationship between the potentials of these two signal lines is accurately determined. This makes it difficult to accurately detect the presence or absence of a pixel defect. More specifically, when the potential of a signal output according to the presence or absence of a pixel defect is slightly higher or lower than the reference potential, it is output according to the quality of the pixel due to the fluctuation of the reference potential due to noise. Therefore, it may be difficult to accurately determine the quality of the pixel.

  Therefore, the present invention has been made in view of the above-described problems. For example, the quality of a pixel can be determined pixel by pixel, and the quality of a pixel can be accurately determined even when noise is applied to a signal line. It is an object of the present invention to provide an electro-optical device substrate configured as described above, an electro-optical device including the substrate, and an electronic apparatus.

  In order to solve the above problems, an electro-optical device substrate according to a first aspect of the present invention includes a substrate, a plurality of scanning lines and a plurality of signal lines arranged so as to intersect with each other on the substrate, One of the plurality of signal lines is provided corresponding to each intersection of the plurality of signal lines configured as a set of two signal lines and the plurality of scanning lines. A plurality of pixel circuits electrically connected to only one of the two signal lines corresponding to each of the two signal lines, a first potential signal being supplied via the one signal line, and the 2 A second potential signal is supplied via the other signal line of the two signal lines, and (i) when the potential of the first potential signal is lower than the potential of the second potential signal, the one signal line is A low potential signal having a potential lower than the potential of the first potential signal via (ii) the first potential signal; When the potential of the signal is higher than the potential of the second potential signal comprises amplifying means for a high potential signal is output having a potential higher than the potential of the first potential signal through said one of the signal lines.

  In the electro-optical device substrate according to the first aspect of the present invention, the two signal lines are physically equivalent wirings, and are arranged so as to cross a plurality of scanning lines in the image display region. ing. Here, “physically equivalent” means that at least one of physical components such as the width, thickness, and constituent material of the wiring is equivalent.

  Of the two signal lines, the signal line selected as one signal line in the intersecting region may not be selected as one signal line in the intersecting region where the two signal lines intersect with other scanning lines. is there. Needless to say, the pixel circuit may be electrically connected only to a specific signal line in each of the intersecting regions where the two signal lines intersect with the plurality of scanning lines. The “intersection area” may be an area where two signal lines intersect with one scanning line. For example, two signal lines are aligned with other signal lines along the direction in which one scanning line extends. This includes a case where one pixel circuit is provided in any one of the regions where each of these two signal lines intersects one scanning line when they are arranged apart from each other. Further, when one signal line arranged oddly from the edge of the image display area and one signal line arranged evenly from the edge of the image display area are two signal lines along one scanning line, each intersection Only one of the odd-numbered signal line and the even-numbered signal line in the region may be selected as one signal line, or the signal line selected as one signal line is different for each crossing region. It's okay.

  The pixel circuit is provided for each of a plurality of intersecting regions where a plurality of sets of two signal lines intersect with one scanning line. The “intersection region” is a region having a certain spread in which each of a plurality of sets of two signal lines intersects one scanning line. More specifically, for example, for the electro-optical device of the present invention. When an electro-optical device is configured using a substrate, it means a region where a pixel portion is provided. The pixel circuit is electrically connected to only one signal line in an intersecting region where two signal lines intersect with one scanning line, and other signal lines for supplying the second potential signal are others. Are not electrically connected. Therefore, the second potential signal is output at a constant potential without being affected by the quality of the other pixel circuits, and the level relationship between the potential of the first potential signal and the potential of the second potential signal reflecting the quality of the pixel circuit. Based on this, the quality of each pixel circuit can be determined. The “pixel circuit” is a circuit including various elements formed on the substrate for the electro-optical device before configuring the electro-optical device, and is included in a part of the pixel portion when the electro-optical device is completed. It is. Accordingly, the pixel circuit is formed on the substrate in accordance with the arrangement of the pixel portion when the electro-optical device is finally completed.

  The amplifying means outputs a high potential signal or a low potential signal via one signal line. More specifically, for example, when the first potential signal output from the pixel circuit has a slightly higher potential than the second potential signal, the potential of the first potential signal with respect to the potential of the second potential signal is reduced. The amplifying means transmits a high-potential signal whose potential is higher than that of the first potential signal through one signal line so that the high level is not obscured by noise applied to the first signal line and the second signal line. For example, it outputs to the determination means. When the first potential signal has a slightly lower potential than the second potential signal, the first signal line and the second signal line indicate that the potential of the first potential signal is lower than the potential of the second potential signal. In order not to be obscured by the applied noise, the amplifying means lowers the potential of the first potential signal and then outputs a low potential signal whose potential is kept low via one signal line. Here, the “first potential signal” is a signal reflecting the quality of the pixel circuit, and more specifically, for example, is a signal output according to the quality of the pixel circuit. For example, an inspection signal is supplied to the pixel circuit in advance prior to the inspection, and a signal having a potential that varies from the potential of the inspection signal according to the quality of the pixel circuit is output as the first potential signal. “Possibility of the pixel circuit” means whether or not the pixel circuit has a defect, and the level relationship between the potentials of the first potential signal and the second potential signal varies depending on the defect occurring in the pixel circuit. .

  The second potential signal supplied via the other signal line has a reference potential that serves as a reference for increasing or decreasing the potential of the first potential signal. Here, since the other signal line is not electrically connected to the pixel circuit in the intersection region, when the pixel circuit provided in the intersection region is judged good or bad, it is influenced by the good or bad of the pixel circuit. There is nothing. Therefore, for example, if the other signal lines are set to the reference potential at the time of inspection, the second potential signal is output with the same potential as the reference potential.

  According to the substrate for an electro-optical device of the present invention, the level of the potentials of the first potential signal and the second potential signal is not changed due to the presence or absence of noise or malfunction of the pixel circuit, and the quality of the pixel circuit is reflected. These signals can be supplied to the amplifying means while maintaining the height relationship between the potential of the first potential signal and the potential of the second potential signal. The “noise” is not limited to an unexpected voltage applied from the outside of each signal line. For example, the first potential signal is a signal that reflects whether or not a pixel circuit electrically connected to one signal line has a defect, that is, whether or not the pixel circuit is good. The difference from the reflected potential of the first potential signal is slightly smaller than the potential that fluctuates depending on the wiring capacitance of one signal line, and the potential level determined by this slight potential difference is shown. The amplification means outputs a high potential signal or a low potential signal so that it can be discriminated. Therefore, even when noise, which is one of the causes for changing the potentials of the first potential signal and the second potential signal, is added, and even when a potential change occurs in each signal line, the amplifying means does not change the first potential signal. In addition, the high potential signal or the low potential signal is output to the determination unit so that the level relationship of the potential of the second potential signal can be clearly determined. Thereby, the determination means can determine whether or not a defect occurs in the pixel circuit electrically connected to one of the signal lines based on the voltage logic.

  Whether the pixel circuit is good or bad is, for example, information on whether the potential of the inspection signal that is the source of the first potential signal supplied in advance to the pixel circuit is higher or lower than the potential of the second potential signal, and the second potential signal Based on the information on whether the potential of the high potential signal or the potential of the low potential signal is higher or lower than the potential of the signal output from the amplification means.

  According to such a determination method, when the potential of the inspection signal that is the basis of the first potential signal is higher than the potential of the second potential signal, if a high potential signal is output from the amplifying means, one signal line is electrically connected. Therefore, it is determined that no malfunction has occurred in the pixel circuits connected to each other, that is, the pixel circuits to which the inspection signal that is the basis of the first potential signal is supplied. On the other hand, if the low potential signal is output from the amplification means when the potential of the inspection signal that is the basis of the first potential signal is higher than the potential of the second potential signal, the pixel circuit electrically connected to one signal line It is determined that some trouble has occurred. When the potential of the inspection signal that is the source of the first potential signal is lower than the potential of the second potential signal, if a low potential signal is output from the amplifying means, the pixel circuit that is electrically connected to one of the signal lines is defective. Means that has not occurred. If the high potential signal is output from the amplification means when the potential of the inspection signal that is the basis of the first potential signal is lower than the potential of the second potential signal, the pixel circuit electrically connected to one signal line, that is, the first It is determined that some malfunction has occurred in the pixel circuit to which the inspection signal that is the source of the one-potential signal is supplied.

  As described above, according to the electro-optical device substrate according to the first aspect of the present invention, the potential of the second potential signal or the potential of the first potential signal varies depending on noise or the presence or absence of a defect in the pixel circuit. And the quality of the pixel circuit can be accurately determined. In addition, since the other signal circuit that outputs the second potential signal is not electrically connected to the other signal line in the region extending along one scanning line, a defect occurs in the pixel circuit to be inspected. If it is not, it is possible to eliminate in principle that it is determined that the pixel circuit is defective. Therefore, according to the electro-optical device substrate according to the first aspect of the present invention, it is possible to accurately and completely detect a defect occurring in the pixel circuit at the stage of manufacturing the substrate. The yield of electro-optical devices such as liquid crystal devices can be increased, and the manufacturing cost can be reduced.

  In one aspect of the electro-optical device substrate according to the first aspect of the present invention, each of the plurality of pixel circuits has a switching element electrically connected to the one scanning line, The first potential signal may be supplied to the amplifying unit via the one signal line in a state where the switching element is turned on in response to the switching signal supplied via the one scanning line. Good.

  According to this aspect, the first potential signal can be supplied to the amplifying unit from the plurality of pixel circuits via one signal line by turning on the switching element. More specifically, for example, by sequentially supplying a switching signal for each row to a switching element electrically connected to each of the last scanning line from the first scanning line of the plurality of scanning lines, the image The quality of all the pixel circuits arranged in the display area can be sequentially checked for each row.

  When switching the switching element to the ON state, it is possible to supply a switching signal from one scanning line to each switching element at once, and whether or not there is a malfunction in the pixel circuit electrically connected to the one scanning line. Can be judged. The switching element is a semiconductor element such as a TFT provided in each pixel circuit in order to drive an electro-optical element such as a liquid crystal element. The switching signal for switching on / off of the switching element is a signal different from the scanning signal supplied from the scanning line to the pixel circuit when displaying an image, and one scanning line when inspecting the pixel circuit separately from the scanning signal. To the switching element electrically connected to the one scanning line.

  In another aspect of the electro-optical device substrate according to the first aspect of the present invention, the electro-optical device substrate is provided in a region of the substrate surface on the side closer to the amplifying means as viewed from the pixel circuit. A transmission gate electrically connected in the middle of the pair of signal lines; and a switching means for switching the transmission gate on and off. The first potential signal and the second potential signal are transmitted by the transmission gate. The signal may be supplied to the amplifying means via the pair of signal lines while being switched to the on state by the switching means.

  According to this aspect, for example, when checking the quality of the pixel circuit, the pixel circuit and the amplifier are connected via the one signal line so that the first potential signal can be supplied to the amplifying unit by switching the transmission gate to the on state. It is possible to conduct between the means. The transmission gate is switched on and off by switching means. The transmission gate may be electrically connected not only to one signal line but also to the other signal line. When the first potential signal is supplied to the amplifying means, the first potential signal is supplied to the amplifying means. The second potential signal can be supplied to the amplifying means via the other signal line in accordance with the supply timing.

  In this aspect, the amplifying means has a plurality of differential amplifier circuits electrically connected one by one for each set of the plurality of signal lines, and the transmission gate is supplied from the switching means. A single transmission gate that is electrically connected in common to the set of the plurality of signal lines so as to be switched on and off by a series of signals, and the first potential signal and the second potential signal are: The single transmission gate may be supplied to the plurality of differential amplifier circuits in a state in which the single transmission gate is switched to an on state in accordance with the series of signals.

  According to this aspect, the first potential signal and the second potential signal are collectively supplied from each pair of two signal lines to the differential amplifier circuit electrically connected to each pair. However, a high potential signal or a low potential signal can be output from each differential amplifier circuit provided for each set of two signal lines.

  In another aspect of the electro-optical device substrate according to the first aspect of the present invention, the amplifying means is electrically connected to each of a plurality of signal line groups each including a plurality of sets of the plurality of signal lines. A plurality of differential amplifier circuits connected to each other, and the transmission gate includes a plurality of signal lines included in the signal line group so as to be individually switched on and off by a plurality of series signals supplied from the switching means. A plurality of transmission gates electrically connected to each set of signal lines, wherein the first potential signal and the second potential signal correspond to a plurality of series of signals supplied from the switching means at different timings; The plurality of transmission gates are supplied to the plurality of differential amplifier circuits in a state where the plurality of transmission gates are switched on for each set of the plurality of signal lines included in the signal line group. It may be.

  According to this aspect, the differential amplifier circuit can be shared by a plurality of pairs of signal lines that are a set of two, and the number of differential amplifiers is smaller than the number of pairs of signal lines that are a set of two. A high potential signal or a low potential signal can be output for each set by a circuit. The plurality of transmission gates are in a state in which the plurality of transmission gates are switched to the on state for each set of the plurality of signal lines included in the signal line group in accordance with a plurality of series of signals supplied from the switching unit at different timings. Therefore, even if one differential amplifier circuit is shared by a set of two signal lines, the first potential signal and the second potential signal are one for each set. Can be supplied to two differential amplifier circuits. Therefore, even when a plurality of pixel circuits are arranged at a narrow pitch in order to improve image quality, the differential amplifier circuit can be provided in a wider space than the pitch of the pixel circuits or signal lines. Thereby, when the differential amplifier circuit has semiconductor elements such as a plurality of transistors, these semiconductor elements can be formed easily and with high quality.

  In another aspect of the electro-optical device substrate according to the first aspect of the present invention, the one signal line is shared with a data line for supplying an image signal to the pixel circuit, and the high potential signal or The low potential signal may be supplied to the determination unit for each pixel circuit in a state where a sampling circuit that samples the image signal on the data line is switched to an on state.

  According to this aspect, one signal line of the set of two signal lines is shared with a data line that supplies an image signal to the pixel circuit. Therefore, a wiring used as a signal line is a data line. There is no need to provide it separately. Therefore, the quality of the pixel circuit can be determined without reducing the size of the opening area in the image display area. Here, the “aperture area” means an area where light is substantially emitted from the pixel portion when the electro-optical device is completed by sampling, and the luminance of the entire image display area increases as the aperture area increases. Can be increased. “Shared” means not only a case where one signal line functions as a data line as it is because one signal line extends to the drive circuit, but also a portion branched from one signal line. The case of functioning as a data line may be included. According to this aspect, it is possible to reduce the narrowing of the opening area by making a configuration capable of inspecting the quality of the pixel portion in the substrate, and it is possible to form a circuit for inspecting the quality of the pixel circuit without deteriorating the image quality.

  The sampling circuit is a circuit that is provided in advance to supply an image signal to the pixel circuit when the electro-optical device is completed. By sharing the data line as one signal line, the sampling circuit is passed through the existing sampling circuit. Thus, a high potential signal or a low potential signal can be supplied to the determination means. In addition, the quality of each of the plurality of pixel circuits electrically connected to one scanning line can be individually determined by sequentially switching on and off the sampling circuit. More specifically, for example, by turning on one sampling switch included in the sampling circuit, a high potential signal or a low potential signal can be output to the determination unit for each pixel circuit via the sampling switch. Accordingly, it is possible to individually check the quality of the pixel circuit electrically connected to one scanning line by sequentially switching the sampling switches.

  According to this aspect, it is possible to individually determine the quality of a plurality of pixel circuits electrically connected to one scanning line, and it is possible to increase the detection accuracy of a pixel circuit in which a defect has occurred. When displaying an image, if the transmission gate is turned off, the data line can be used to supply an image signal, and the image is displayed even if the data line and one signal line are shared. There will be no problem.

  In another aspect of the electro-optical device substrate according to the first aspect of the present invention, the one signal line and the other signal line are arranged in a direction in which the plurality of scanning lines out of the plurality of signal lines extend. May be adjacent to each other.

  According to this aspect, since one signal line and the other signal line constituting a set of two signal lines are adjacent to each other, noise applied to one signal line and the other signal line is The first potential signal supplied from one signal line and the second potential signal supplied from the other signal line are applied to the one signal line and the other signal line to the same or similar extent. Noise having the same potential is applied. Since the amplifying means outputs the high potential signal or the low potential signal by comparing the potentials of the first potential signal and the second potential signal, fluctuations in the potentials of the first potential signal and the second potential signal are output. Are equal, the relative potential level relationship between the first potential signal and the second potential signal is not changed by noise. Therefore, the amplification unit can output the first potential signal having a potential reflecting the quality of the pixel circuit to the determination unit as a high potential signal or a low potential signal, and the quality of the pixel circuit is accurately determined.

  In another aspect of the electro-optical device substrate according to the first aspect of the present invention, the pixel circuit may be connected to the one signal line by electrically connecting the pixel circuit to the one signal line. It may be arranged so that the fluctuation of the generated capacitance is averaged within the image display area.

  In this aspect, for example, when the potential difference between the first potential signal and the second potential signal is slight, the potentials of the first potential signal and the second potential signal are increased or decreased even if the first potential signal is supplied to the amplification means as it is. In order not to change the relationship, a pixel circuit is provided so as to average the capacitance variation of one signal line and the other signal line. More specifically, for example, the pixel circuits may be electrically connected to each signal line by the same number or distribution according to this in the image display area. Thereby, the relative capacitance variation between the signal lines becomes constant. The amplifying means may output a high potential signal or a low potential signal in which the level relationship of the potential of the first potential signal with respect to the potential of the second potential signal is maintained by comparing the first potential signal with the second potential signal. It is possible to reduce erroneous determination of the quality of the pixel circuit.

  In another aspect of the electro-optical device substrate according to the first aspect of the present invention, before the first potential signal and the second potential signal are supplied to the amplifying unit, the two signal lines are connected. There may be further provided a potential setting means for setting the respective potentials of the two signal lines so as to equalize the potentials.

  According to this aspect, when the pixel circuit is inspected, the level relationship between the potentials of the first potential signal and the second potential signal supplied to the amplifying means via the two signal lines can be maintained, and the quality of the pixel circuit can be accurately determined. Can be judged. The potential setting means can be exercised by, for example, a plurality of TFTs electrically connected between two signal lines. When a potential difference is generated between these signal lines, the current of these TFTs The potential of both signal lines can be set to the same potential.

  In order to solve the above problems, a substrate for an electro-optical device according to a second aspect of the present invention includes a substrate, a plurality of scanning lines arranged to extend to an image display area on the substrate, A plurality of first signal lines arranged so as to intersect the plurality of scanning lines in the image display region, and N (N is a natural number of 2 or more) first signal lines among the plurality of first signal lines. Are provided in each of a plurality of intersecting regions where the plurality of scanning lines and the plurality of first signal lines intersect with each other. A plurality of pixel circuits electrically connected to each of the first signal lines, a first potential signal is supplied from the pixel circuits via the first signal line, and a second is supplied via the second signal line. A potential signal is provided, and (i) when the potential of the first potential signal is lower than the potential of the second potential signal, A low potential signal having a potential lower than the potential of the first potential signal via the first signal line; (ii) when the potential of the first potential signal is higher than the potential of the second potential signal, And amplifying means for outputting a high potential signal having a potential higher than the potential of the first potential signal to a determination means for determining the quality of the pixel circuit by voltage logic via one signal line.

  According to the electro-optical device substrate of the second aspect of the present invention, one signal line group includes N (N is a natural number of 2 or more) first signal lines among the plurality of first signal lines. The arranged second signal lines are sequentially paired with each of the N first signal lines, and the first potential signal is supplied to the amplifying means via the first signal line included in the pair. . By sequentially setting a second signal line and each of the N first signal lines as a set, the second signal line for supplying the second potential signal to the amplifying unit is the N first signal lines. The first potential signal that can be sequentially shared and sequentially supplied to the amplifying means via the N first signal lines can be compared with the second potential signal. As a result, the number of second signal lines can be reduced from the number of first signal lines, and the number of signal lines provided in the image display area can be reduced. Accordingly, the light emitted from the pixel portion by the second signal line can be prevented from being blocked, and the pixel circuit is substantially reduced without reducing the size of the opening region that is the region from which the light is emitted from the pixel portion. Can be judged.

  The amplifying unit outputs a high potential signal or a low potential signal to the determination unit via the first signal line that is paired with the second signal line, and the pixel is determined by voltage logic based on the high potential signal or the low potential signal. The quality of the circuit can be determined. More specifically, for example, when the first potential signal has a slightly higher potential than the second potential signal, the first potential signal and the second signal line are caused by noise applied to the first signal line and the second signal line. The amplifying means outputs a high potential signal in which the potential of the first potential signal is increased via the first signal line so that the potential difference of the second potential signal is not obscured. When the first potential signal has a slightly lower potential than the second potential signal, the potential difference between the first potential signal and the second potential signal is caused by noise applied to the first signal line and the second signal line. In order not to obscure, the amplifying means lowers the potential of the first potential signal, and then outputs a low potential signal whose potential is kept low through one signal line. Accordingly, the second potential signal supplied to the amplifying means via the second signal line is a reference potential that serves as a reference when increasing or decreasing the potential of the first potential signal, for example. Note that “noise” and “voltage logic” have the same meaning as in the electro-optical device substrate according to the first aspect of the present invention.

  As described above, according to the electro-optical device substrate according to the second invention of the present invention, whether or not a defect occurs in each pixel circuit as in the case of the electro-optical device substrate according to the first invention of the present invention. Can be detected. Therefore, it is possible to accurately detect a defect occurring in the pixel portion, and accordingly, the yield of an electro-optical device such as a liquid crystal device can be increased, and the manufacturing cost can be reduced.

  In one aspect of the electro-optical device substrate according to the second aspect of the present invention, each of the plurality of pixel circuits has a switching element electrically connected to the one scanning line, The first potential signal may be supplied to the amplifying unit through the first signal line in a state where the switching element is turned on in response to the switching signal supplied through the one scanning line. Good.

  According to this aspect, the first potential signal can be supplied from the plurality of pixel circuits to the amplifying unit via the first signal line by turning on the switching element. More specifically, for example, by sequentially supplying a switching signal for each row to a switching element electrically connected to each of the last scanning line from the first scanning line of the plurality of scanning lines, the image The quality of all the pixel circuits arranged in the display area can be sequentially checked for each row.

  The first potential signal is, for example, a signal obtained by reading out an inspection signal supplied in advance to the pixel circuit from the pixel circuit. When a defect occurs in the pixel circuit, an inspection signal whose potential varies according to the defect is generated. The first potential signal is supplied to the amplification means. When switching the switching element to the ON state, a switching signal can be collectively supplied from one scanning line to each switching element, and whether a pixel circuit electrically connected to the one scanning line has a problem. Can be determined. The switching element is a semiconductor element such as a TFT provided in each pixel circuit in order to drive an electro-optical element such as a liquid crystal element. The switching signal for switching on / off of the switching element is a signal different from the scanning signal supplied from the scanning line to the pixel circuit when displaying an image, and one scanning line when inspecting the pixel circuit separately from the scanning signal. Supplied from

  In another aspect of the electro-optical device substrate according to the second aspect of the present invention, the second signal line is adjacent to the plurality of first signal lines in the image display region. It may be branched into a plurality of branch lines extending along the direction in which.

  According to this aspect, for example, noise or the like applied to the plurality of branch lines is the same as or equivalent to the first signal line adjacent to the branch lines, and the first potential signal and the first signal due to the noise or the like. It can be reduced that the level relationship of the potential of the two-potential signal is reversed from the original level relationship during output. Therefore, the quality of the pixel circuit can be accurately determined based on the high potential signal or the low potential signal output from the amplification unit based on the first potential signal and the second potential signal.

  In another aspect of the electro-optical device substrate according to the second invention of the present invention, the electro-optical device substrate is provided in a region of the substrate surface of the substrate closer to the amplifying means as viewed from the pixel circuit, and the first signal A plurality of transmission gates electrically connected in common to a plurality of signal line groups each including a plurality of lines; and switching means for switching on and off the plurality of transmission gates, wherein the amplification means includes the signal group A plurality of differential amplifier circuits electrically connected one by one, and the plurality of transmission gates are separately electrically connected to a plurality of first signal lines included in the signal line group; The first potential signal is generated by the plurality of transmission gates in accordance with a plurality of series of signals supplied from the switching means at different timings. In a state of switched to the ON state for each of the plurality of first signal lines included in the signal line group may be supplied to the differential amplifier circuit at different timings.

  According to this aspect, for example, when inspecting the quality of the pixel circuit, the first potential signal can be individually supplied to the amplifying unit from the first signal line included in the signal line group. Since one differential amplifier circuit is provided for each of the signal line groups, the differential amplifier circuit is provided for each pair of N first signal lines and second signal lines. The number of differential amplifier circuits can be reduced, and the space per differential amplifier circuit can be widened accordingly. Thereby, for example, a plurality of semiconductor elements included in the differential amplifier circuit can be formed with high quality.

  In order to solve the above problems, an electro-optical device according to the present invention includes the electro-optical device substrate according to the first invention or the second invention described above.

  According to the electro-optical device according to the present invention, since the electro-optical device substrate according to the first or second invention described above is provided, a high-quality electro-optical device with a high yield can be provided.

  In order to solve the above problems, an electronic apparatus according to the present invention includes the above-described electro-optical device of the present invention (including various aspects thereof).

  Since the electronic apparatus of the present invention includes the above-described electro-optical device of the present invention, a projection display device, a television, a mobile phone, an electronic notebook, a word processor, a view capable of performing high-quality image display. Various electronic devices such as a finder type or a monitor direct-view type video tape recorder, a workstation, a videophone, a POS terminal, and a touch panel can be realized. Since such an electronic device includes the above-described electro-optic device substrate, the yield is improved.

  Such an operation and other advantages of the present invention will become apparent from the embodiments described below.

  Hereinafter, embodiments of an electro-optical device substrate, an electro-optical device, and an electronic apparatus according to the present invention will be described with reference to the drawings. In this embodiment, a TFT array substrate is given as an example of the electro-optical device substrate according to the first and second inventions of the present invention, and a liquid crystal provided with a TFT array substrate as an example of the electro-optical device of the present invention. Take the panel as an example.

(First embodiment)
<Configuration of electro-optical device>
First, the configuration of the liquid crystal panel of the present embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a schematic view of a liquid crystal panel 100 when a TFT array substrate 10 as an example of a substrate for an electro-optical device according to the first aspect of the present invention is viewed from the side of a counter substrate 20 together with each component formed thereon. FIG. 2 is a cross-sectional view taken along the line H-H ′ of FIG. 1. Note that the liquid crystal panel 100 of the present embodiment employs a TFT active matrix driving method with a built-in driving circuit.

  1 and 2, the liquid crystal panel 100 includes a TFT array substrate 10 and a counter substrate 20 disposed to face the TFT array substrate 10. A liquid crystal layer 50 is sealed between the TFT array substrate 10 and the counter substrate 20, and the TFT array substrate 10 and the counter substrate 20 are interposed via a seal material 52 provided in a seal region located around the image display region 10 a. Are bonded to each other.

  The sealing material 52 is made of, for example, an ultraviolet curable resin, a thermosetting resin, or the like for bonding the two substrates, and is applied on the TFT array substrate 10 in the manufacturing process and then cured by ultraviolet irradiation, heating, or the like. It is. In the sealing material 52, a gap material such as glass fiber or glass beads for dispersing the distance (inter-substrate gap) between the TFT array substrate 10 and the counter substrate 20 to a predetermined value is dispersed.

  A light-shielding frame light-shielding film 53 that defines the frame area of the image display area 10a is provided on the counter substrate 20 side in parallel with the inside of the seal area where the sealing material 52 is disposed. However, part or all of the frame light shielding film 53 may be provided as a built-in light shielding film on the TFT array substrate 10 side.

  Of the peripheral regions located around the image display region 10 a, the X-driver circuit 101 and the external circuit connection terminal 102 are arranged on one side of the TFT array substrate 10 in the region located outside the seal region where the sealing material 52 is disposed. It is provided along. The Y-driver circuit 104 is provided so as to be covered with the frame light shielding film 53 along one of the two sides adjacent to the one side. The Y-driver circuit 104 may be provided along two sides adjacent to one side of the TFT array substrate 10 on which the X-driver circuit 101 and the external circuit connection terminal 102 are provided. In this case, the two Y-driver circuits 104 are connected to each other by a plurality of wirings provided along the remaining side of the TFT array substrate 10.

  Vertical conductive members 106 functioning as vertical conductive terminals between the two substrates are disposed at the four corners of the counter substrate 20. On the other hand, the TFT array substrate 10 is provided with vertical conduction terminals in a region facing these corner portions. Electrical conduction between the TFT array substrate 10 and the counter substrate 20 can be established by the vertical conduction terminals and the vertical conduction material 106.

  In FIG. 2, on the TFT array substrate 10, an alignment film is formed on the pixel electrode 9a after the pixel switching TFT, the scanning line, the data line and the like are formed. On the other hand, on the counter substrate 20, in addition to the counter electrode 21, a lattice-shaped or striped light-shielding film 23 and an alignment film are formed on the uppermost layer portion. The liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several types of nematic liquid crystals are mixed, and takes a predetermined alignment state between the pair of alignment films.

  When a semiconductor substrate such as silicon is used for the array substrate, a transistor can be used as the pixel switching element.

<Configuration of substrate for electro-optical device>
Next, the configuration of the TFT array substrate 10 and the processing procedure during inspection will be described with reference to FIGS. FIG. 3 is a block diagram showing the main circuit configuration of the TFT array substrate 10. In the following, for the sake of simplicity of explanation, the lines are evenly arranged along the direction in which the scanning line Gj (j = 1, 2,..., N; an integer of 2 or more) extends as viewed from the left side in the drawing. The signal line Soi (i = 1, 2,..., M; m is an integer of 2 or more) is selected as “one signal line” of the present invention, and the odd-numbered signal line Sei (i = 1, 2,..., M; m is an integer) will be described on the assumption that “the other signal line” of the present invention is selected.

  In FIG. 3, the TFT array substrate 10 includes an inspection circuit 4, an X-driver 101, a Y-driver 104, and a sampling circuit 110.

  The inspection circuit 4 includes a plurality of differential amplifier circuits 15, a first drive signal supply circuit 21, a second drive signal supply circuit 22, an equalize circuit 23, and a voltage application wiring 24 that constitute an example of the “amplifying unit” of the present invention. , A precharge circuit 25, a connection circuit 26 as an example of the “switching means” of the present invention, TFTs 11, 12a, 12b, 13p, and 13n, a transmission gate 6, a plurality of signal lines Soi, and a plurality of signal lines Sei. ing. The equalize circuit 23, the voltage application wiring 24, the precharge circuit 25, the TFTs 11, 12a, and 12b constitute an example of the “potential setting means” in the present invention.

  A plurality of signal lines Soi and signal lines Sei extend from the image display region 10 a to the differential amplifier circuit 15, and are electrically connected to connection points So and Se of the differential amplifier circuit 15, respectively. The signal line Soi and the signal line Sei are a plurality of scanning lines Gj (j = 1, 2,..., N; n is 2 or more) provided in the image display area 10a described in detail later with reference to FIG. The image display area 10a extends in the image display area so as to intersect the integer. The pixel portion 70 provided in the image display region 10a is arranged in accordance with the intersection of the signal line Soi and the plurality of scanning lines Gj, and is electrically connected to the signal line Soi. The signal line Sei is not electrically connected to the pixel portion 70.

  The connection circuit 26 includes a test signal supply line 45 electrically connected to the test circuit via a test circuit connection gate terminal, and a pull-down circuit 35. The test signal supply line 45 supplies a series of test signals supplied from the test circuit to the transmission gate 6 when the TFT array substrate 10 is inspected. The pull-down circuit 35 stabilizes the potential of the test signal supply line 45 so that the test signal supplied to the transmission gate 6 via the test signal supply line 45 does not fluctuate.

  Here, as shown in FIG. 7, the pull-down circuit 35 includes a TFT 135 having a gate electrically connected to the power supply VDD, a grounded source, and a drain electrically connected to the test signal supply line 45. And reducing the fluctuation of the potential of the test signal supply line 45 when the test signal is supplied. Note that the pull-down circuits 32, 32, 33, and 34 also have the same circuit configuration as the pull-down circuit 35.

  In FIG. 3 again, the transmission gate 6 is an example of the “single transmission gate” in the present invention, and is provided in the middle of each of the signal line Soi and the signal line Sei. The transmission gate 6 is provided on the side close to the differential amplifier circuit 15 when viewed from the pixel portion 70, and includes a plurality of TFTs 14 electrically connected in the middle of each of the signal lines Soi and Sei. The plurality of TFTs 14 are collectively turned on according to the test signal supplied from the test circuit via the test signal supply line 45 when the TFT array substrate 10 is inspected. As a result, a supply path for the first potential signal and the second potential signal supplied to the differential amplifier circuit 15 via each of the signal lines Soi and Sei can be secured, and the TFT 71 provided in the pixel unit 70 described later is turned on. If switched to the state, the first potential signal and the second potential signal can be collectively supplied from each pixel unit 70 to each differential amplifier circuit 15 via each of the signal lines Soi and Sei.

  Here, the first potential signal is a signal in which the inspection signal previously supplied to the pixel unit 70 is read from the pixel unit 70, and is different from the potential of the inspection signal in accordance with the malfunction occurring in the pixel unit 70. Is output. The potential of the second potential signal supplied to the differential amplifier circuit 15 through the signal line Sei simultaneously with the first potential signal is output at a potential equivalent to the intermediate potential previously applied to the signal line Sei. The intermediate potential is a reference potential to be compared when the differential amplifier circuit 15 determines the level of the potential of the first potential signal.

  The equalize circuit 23 includes an equalize signal supply line 43 and a pull-down circuit 33, and a precharge signal for switching on / off of the TFT 11 is supplied to the gate of the TFT 11 via the equalize signal supply line 43. The pull-down circuit 33 reduces fluctuations in the potential of the equalize signal supply line 43.

  The precharge circuit 25 includes a precharge signal supply line 44 electrically connected to the gates of the TFTs 12 a and 12 b and a pull-down circuit 34 electrically connected to the precharge signal supply line 44. The precharge signal supply line 44 is also electrically connected to the equalize signal supply line 43. The precharge signal supply line 44 supplies a precharge signal supplied from the outside to the gates of the TFTs 11, 12a, and 12b through the precharge terminal in order to switch on and off the TFTs 11, 12a, and 12b. The pull-down circuit 34 reduces fluctuations in the potential of the precharge signal supply line 44.

  The voltage application wiring 24 is electrically connected to the source of the TFT 12a and the drain of the 12b, and applies a precharge voltage to the TFTs 12a and 12b. The precharge voltage is set to an intermediate potential in advance and is supplied to the TFTs 12a and 12b. The precharge voltage is supplied to the TFTs 12a and 12b before the first potential signal and the second potential signal are supplied to the differential amplifier circuit 15 through the signal line Soi and the signal line Sei, respectively.

  The TFTs 11, 12a and 12b are turned on by a precharge signal, and the signal lines Soi and signal lines are supplied before the first potential signal and the second potential signal are supplied to the first signal line Soi and the second signal line Sei. The potentials of the signal line Soi and the signal line Sei are set so that the potential difference between Sei is eliminated. More specifically, the source and drain of the TFT F11, the drain of the TFT 12a, and the source of the TFT 12b are electrically connected to the signal line Soi and the signal line Sei, respectively, and the precharge signal is supplied to the gates of the TFTs 11, 12a, and 12b. Then, a precharge voltage is supplied between the respective sources and drains of the TFTs 12a and 12b. Thereby, a current flows between the source and drain of the TFT 11 and between the source and drain of each of the TFTs 12a and 12b so as to eliminate the potential difference between the signal line Soi and the signal line Sei, and the respective potentials of the signal line Soi and the signal line Sei. Becomes equal to the intermediate potential. Therefore, on the premise that the differential amplifier circuit 15 compares the first potential signal and the second potential signal, the potentials of the signal line Soi and the signal line Sei supplying these signals to the differential amplifier circuit 15 can be made uniform.

  When the first potential signal and the second potential signal are supplied to the differential amplifier circuit 15 through the signal line Soi and the signal line Sei having the same potential, the first potential signal output from the pixel unit 70 and The first potential signal and the second potential signal are supplied to the differential amplifier circuit 15 while maintaining the level relationship of the potential of the second potential signal. Therefore, it is possible to reduce the fluctuation in the level relationship between the potential of the first potential signal and the potential of the second potential signal due to the potential difference between the signal line Soi and the signal line Sei, and the first potential signal and the second potential signal It is possible to reduce the reversal of the potential relationship.

  The first drive signal supply circuit 21 includes a first drive signal supply line 41 and a pull-up circuit 31. The first drive signal supply line 41 is electrically connected to the gate of the TFT 13p, which is a switching element electrically connected to the differential amplifier circuit 15, and the first drive signal SApE supplied from the outside is supplied to the TFT 13p. Supply to the gate. The first drive signal is a sense amplifier drive signal for driving the sense amplifier. As will be described later, the differential amplifier circuit 15 is a signal having a high potential among signals input to the connection points So and Se. It functions as a sense amplifier that raises the potential of the lower signal and lowers the potential of the low signal. The TFT 13p is a p-channel TFT, and the TFT 13p is turned on when the first drive signal SApE is supplied to the gate, and supplies the power supply VDD to the connection terminal Sp of the differential amplifier circuit 15.

  Here, as shown in FIG. 6, the pull-up circuit 31 includes a p-channel TFT 131 whose gate is grounded. The TFT 131 supplies the power VDD to the first drive signal supply line 41.

  The second drive signal supply circuit 22 includes a second drive signal supply line 42 and a pull-down circuit 32. The second drive signal supply line 42 is electrically connected to the gate of the TFT 13n electrically connected to the differential amplifier circuit 15, and supplies the second drive signal SAnE supplied from the outside to the gate of the TFT 13n. . The TFT 13n is an n-channel TFT and is turned on when the second drive signal SAnE is supplied to the gate, and supplies the power supply VDD to the differential amplifier circuit 15. The pull-down circuit 32 maintains the potential of the second drive signal supply line 42.

  One differential amplifier circuit 15 is provided for each pair of signal lines each including the signal line Soi and the signal line Sei. When the transmission gate 6 is turned on, the first potential signal and the second potential signal are supplied from the signal line Soi and the signal line Sei to the connection points So and Se of the differential amplifier circuit 15, respectively. The differential amplifier circuit 15 compares the first potential signal and the second potential signal, and outputs a high potential signal or a low potential signal to the test circuit which is a determination unit via each of the signal lines Soi and Sei.

  Here, the detailed configuration of the differential amplifier circuit 15 will be described with reference to FIG. FIG. 4 is a circuit diagram showing an electrical configuration of the differential amplifier circuit 15.

  In FIG. 4, the differential amplifier circuit 15 is an amplifier circuit composed of four transistors. Specifically, the differential amplifier circuit 15 is a cross-coupled type including p-channel TFTs 51 and 52 and n-channel TFTs 53 and 54. This is a differential amplifier circuit. More specifically, a series circuit in which the TFTs 51 and 52 are electrically connected in series and a series circuit in which the TFTs 53 and 54 are electrically connected in series are electrically connected in parallel. The gate of the TFT 51 is electrically connected to the connection point So between the TFTs 52 and 54. The gate of the TFT 52 is electrically connected to the connection point Se between the TFTs 51 and 53. The gate of the TFT 53 is electrically connected to the connection point So between the TFTs 52 and 54. The gate of the TFT 54 is electrically connected to the connection point Se between the TFTs 51 and 53. The connection point So is electrically connected to the first signal line Soi, and the connection point Se is electrically connected to the second signal line Sei. The connection point Sp between the TFTs 51 and 52 is electrically connected to the drain of the TFT 13p. A connection point Sn between the TFTs 53 and 54 is electrically connected to the drain of the TFT 13n.

  When the first potential signal has a slightly higher potential than the second potential signal, the differential amplifier circuit 15 applies a high potential signal whose potential is higher than that of the first potential signal to the signal line Soi. To the test circuit which is an example of the determination means. Thus, according to the high potential signal whose potential is increased, it is possible to clarify that the potential of the first potential signal is higher than the potential of the second potential signal. When the first potential signal has a slightly lower potential than the second potential signal, the differential amplifier circuit 15 applies a low potential signal whose potential is lower than that of the first potential signal to the signal line Soi. Output via. According to such a low potential signal, it is possible to clarify that the potential of the first potential signal is lower than the potential of the second potential signal.

  The second potential signal supplied to the differential amplifier circuit 15 via the signal line Sei is a reference potential that serves as a reference when the potential of the first potential signal is increased or decreased. The first potential signal is a signal that reflects whether or not the pixel portion 70 electrically connected to the signal line Soi has a defect, that is, the quality of the pixel portion 70, and the second potential signal and the first potential signal. Is slightly smaller than the potential that fluctuates depending on the wiring capacitance of these signal lines. The differential amplifier circuit 15 outputs a high potential signal or a low potential signal so that the level relationship between the potential of the first potential signal and the second potential signal can be clearly determined.

  In addition, as will be described in detail later, the pixel portion 70 is electrically connected to a signal line Soi that is an example of one signal line, and is electrically connected to a signal line Sei that is an example of the other signal line. Not connected to. The second potential signal supplied to the differential amplifier circuit 15 via the signal line Sei is maintained at a potential equal to the intermediate potential, which is the reference potential, without being subjected to potential fluctuations due to the malfunction of the pixel unit 70. The signal is supplied to the differential amplifier circuit 15 as it is. Thereby, it can reduce that it is determined that the normal pixel unit 70 has a defect, and the inspection accuracy of the pixel unit 70 can be increased.

  A test circuit (not shown in FIG. 3) determines whether or not a defect has occurred in the pixel portion 70 electrically connected to the signal line Soi based on the voltage logic. The test circuit includes a level relationship between the potential of the inspection signal that is the source of the first potential signal supplied to the pixel portion in advance and the potential of the second potential signal, and the potential of the intermediate potential and the high potential signal or the potential of the low potential signal. It is determined whether or not a defect has occurred in the pixel portion 70 by comparing with information on the relationship between potential levels. More specifically, if the high-potential signal is output from the differential amplifier circuit 15 when the potential of the inspection signal that is the source of the first potential signal is higher than the intermediate potential, it is electrically connected to the signal line Soi. The test circuit determines that there is no malfunction in the pixel unit 70, that is, the pixel unit 70 to which the inspection signal that is the basis of the first potential signal is supplied. Similarly, when the potential of the inspection signal that is the source of the first potential signal is lower than the potential of the second potential signal, if the low potential signal is output from the differential amplifier circuit 15, it is electrically connected to the first signal line. The test circuit determines that a defect does not occur in the pixel unit 70 that has been supplied, that is, the pixel unit to which the inspection signal that is the basis of the first potential signal is supplied.

  If the low potential signal is output from the differential amplifier circuit 15 when the potential of the inspection signal that is the basis of the first potential signal is higher than the potential of the second potential signal, the pixel portion that is electrically connected to the signal line Soi 70, that is, the test circuit determines that some trouble has occurred in the pixel unit 70 to which the inspection signal that is the basis of the first potential signal is supplied. If the high potential signal is output from the differential amplifier circuit 15 when the potential of the inspection signal that is the basis of the first potential signal is lower than the potential of the second potential signal, the pixel unit 70 that is electrically connected to the signal line Soi. That is, the test circuit determines that some trouble has occurred in the pixel unit 70 to which the inspection signal that is the basis of the first potential signal is supplied.

  Here, a procedure in which the differential amplifier circuit 15 outputs a high potential signal or a low potential signal will be described with reference to FIGS. Here, a case where a first potential signal having a higher potential than the potential of the second potential signal having an intermediate potential is supplied to the differential amplifier circuit 15 will be described as an example.

  3 and 4, when the second drive signal SAnE is supplied from the second drive signal supply circuit 22 to the TFT 13n, the TFT 13n is turned on, and the potential at the connection point Sn approaches the ground potential via the TFT 13n. . Since the source potential of the TFT 53 is set to an intermediate potential, a current flows between the source and drain of the TFT 53, and the potential of the connection point Se decreases. At this time, since the gate of the p-channel TFT 52 is electrically connected to the connection point Se, the TFT 52 is switched to the on state when the potential at the connection point Se decreases. When the first drive signal SApE is supplied from the first drive signal supply circuit 21 to the TFT 13p, the TFT 13p is switched on, and the power supply VDD is supplied to the connection point Sp via the TFT 13p. Thereby, the power supply VDD is supplied to the connection point So through the TFTs 13p and 52, and the potential of the connection point So is increased.

  In this way, the differential amplifier circuit 15 increases the potential of the first potential signal and decreases the potential of the second potential signal. According to the differential amplifier circuit 15, when the first potential signal is higher than the intermediate potential, the first potential signal can be output to a determination unit such as a test circuit as a high potential signal having a higher potential. Therefore, the determination means such as a test circuit can clearly determine the level relationship between the reference signal having a potential lower than the intermediate potential and the high potential signal, and can determine the quality of the pixel unit 70 based on the voltage logic. When the potential of the first potential signal is lower than the potential of the second potential signal, the TFTs 51 and 54 operate similarly to the TFTs 52 and 53 described above, and a low potential signal is output based on the first potential signal. In this case, the second potential signal is set as an intermediate potential and the second potential signal is output as a reference signal with an increased potential, and the first potential signal is output as a low potential signal having a potential lower than that of the reference signal. . The reference signal is a signal output from the differential amplifier circuit 15 based on the second potential signal.

  Referring again to FIG. 3, the configuration of the TFT array substrate 10 will be described. The Y-driver circuit 104 sequentially supplies switching signals for each scanning line when the pixel unit 70 is inspected. Here, the switching signal is a signal different from an image display scanning signal supplied to the pixel unit 70 when displaying an image, and an inspection signal supplied in advance to the pixel unit 70 is output from the pixel unit 70. This is a signal for switching the switching element included in the pixel unit 70 to the ON state.

  The X-driver circuit 101 supplies a sampling signal to the sampling switch 111 that constitutes the sampling circuit 110, and switches the sampling switch 111 to an on state. Here, the “sampling signal” is different from the signal supplied from the X-driver circuit 101 to the sampling circuit 110 when displaying an image, and is based on the first potential signal output from the pixel unit 70 of each row. This is a signal for individually outputting a high potential signal or a low potential signal collectively output from the differential amplifier circuit 15 to an external test circuit for each pixel unit 70.

  The sampling circuit 110 individually outputs a first potential signal read for each row when the pixel unit 70 is inspected in correspondence with the pixel unit 70, and outputs a high potential to an external test circuit via the image signal supply line 112. A signal or a low potential signal is output. According to the sampling circuit 110, a high potential signal or a low potential signal output for each row of the pixel unit 70 can be output to the test circuit for each pixel unit 70 constituting this row, and the test circuit can check whether or not a defect has occurred. This can be determined for each pixel portion. Therefore, the quality of the pixel units 70 arranged in a matrix in the image display area can be accurately detected for each pixel unit. In addition, since the inspection accuracy can be increased by using existing circuits such as the sampling circuit 110 and the X-driver circuit 101, the manufacturing cost of the TFT array substrate 10 can be reduced while reducing the number of newly provided circuits. In addition, the yield can be improved.

  Next, the circuit configuration and arrangement of the pixel portion will be described with reference to FIGS. FIG. 5 is a circuit diagram of the pixel portion, and FIG. 8 is an arrangement diagram schematically showing the arrangement of the pixel portion, scanning lines, and signal lines in the image display region.

  In FIG. 5, the pixel portion 70 includes a TFT 73, which is an example of the “switching element” of the present invention, a liquid crystal element 72, and a storage capacitor 73. The TFT 73 and the storage capacitor 73 are examples of the “pixel circuit” of the present invention. Configure. Note that after the liquid crystal panel 100 is configured, a liquid crystal element may be included in a part of the pixel circuit.

  The TFT 71 has a source electrically connected to the signal line Soi and a gate electrically connected to the scanning line Gj. The TFT 71 is switched on and off by a switching signal supplied at the time of inspection, and the pixel unit 70 outputs a first potential signal to the signal line Soi. The liquid crystal element 72 has a liquid crystal injected between the TFT array substrate 10 and a counter substrate disposed so as to correspond to the TFT array substrate 10, and a pair of electrodes for sandwiching the liquid crystal. The storage capacitor 73 temporarily holds an image signal supplied to the pixel unit 70 when image display is performed, and enables active matrix driving of the plurality of pixel units 70.

  In FIG. 8, a plurality of scanning lines Gj, a plurality of signal lines Soi, and a plurality of signal lines Sei are arranged so as to intersect with each other in the image display region 10a. A set of signal lines each having Soi and Sei as one set is arranged in an intersection region Pji that intersects the scanning line Gj, and is electrically connected to the signal line Soi in the intersection region Pji.

  The signal line Soi and the signal line Sei are physically equivalent wirings. For example, at least one of physical components such as the width, thickness, and constituent material of the signal line Soi and the signal line Sei is equivalent. The signal line Soi and the signal line Sei are adjacent to each other along the direction in which the plurality of scanning lines Gj extend. Therefore, when noise is applied to the image display region 10a, noise having the same potential or waveform is applied to the adjacent signal line Soi and signal line Sei, and therefore the potential of the first potential signal caused by the noise and The variation in potential of the second potential signal is equivalent. Therefore, it is possible to reduce fluctuations in the level relationship between the potentials of the first potential signal and the second potential signal output via the signal lines Soi and Sei that are paired in the intersection region Pji due to noise. More specifically, the first potential signal and the second potential signal are connected to the signal lines Soi and Sei so that the potential of the first potential signal is slightly higher or lower than the potential of the second potential signal. To the differential amplifier circuit 15.

  In the present embodiment, the signal line Soi is selected as an example of “one signal line” in the present invention in all the intersecting regions Pji, but the signal line Sei may be selected as one signal line. Any one of the signal lines Soi and Sei only needs to be electrically connected to the pixel unit 70 in each intersection region Pji. More specifically, for example, when attention is paid to one set of signal lines Soi and Sei, in the intersection region P1i where the set intersects the scanning line G1, the signal line Soi is selected as one signal line. The signal line Sei may be selected as one signal line in the intersecting region Pji that intersects with another scanning line Gj.

  One pixel portion 70 is provided for each intersection region Pji where a pair of signal lines Soi and Sei intersects one scanning line Gj. The pixel unit 70 is electrically connected only to the signal line Soi among the first signal line Soi and the second signal line Sei included in the signal line set Pji. When the two signal lines Soi and Sei are arranged apart from each other with other signal lines interposed therebetween, the pixel unit 70 includes the signal lines Soi and Sei as the scanning lines Gj. It may be disposed in one of the intersecting regions and electrically connected to one of these signal lines.

  When attention is paid to one scanning line Gj, the signal line to which the pixel unit 70 is electrically connected in each intersection region Pji located along the scanning line Gj may be different for each intersection region Pij. Good. As will be described later, the first potential signal and the second potential signal are output for each row of the pixel unit 70 arranged in the image display area 10a. If the pixel portion is electrically connected to one of a pair of signal lines in the intersection region Pij located in each row and an intermediate potential is supplied to the other signal line, the first potential signal is generated for each intersection region Pji. The second potential signal can be output to the differential amplifier circuit 15.

  In FIG. 8, the pixel unit 70 is arranged at the intersection of the scanning line Gj and the signal line Soi for the sake of convenience in order to show the arrangement of the pixel unit 70. However, the pixel unit 70 is arranged in the intersection region Pji. What is necessary is just to arrange | position to the pixel area | region on the board | substrate prescribed | regulated by the scanning line Gj, the signal line Soi, and the signal line Sei so that it may distribute in matrix form in the image display area 10a.

  Next, a procedure for supplying the first potential signal and the second potential signal from the pixel unit 70 to the differential amplifier circuit 15 will be described with reference to FIGS. 3, 5, and 8.

  In FIG. 3, FIG. 5 and FIG. 8, first, a switching signal is supplied to each of the switching elements 71 provided in the plurality of pixel portions 70 electrically connected to the scanning line G1 via the scanning line G1. At this stage, the first potential signal is supplied to the differential amplifier circuit 15 from the pixel portion 70 electrically connected to the scanning line G1. At this time, the transmission gate 6 is switched on so that the first potential signal can be supplied to the differential amplifier circuit 15, and the signal line Soi is connected to each of the pixel portions 70 electrically connected to the scanning line G1. Thus, the first potential signal is supplied to the differential amplifier circuit 15. At this time, the second potential signal is also supplied to the differential amplifier circuit 15 through the signal line Sei. Subsequently, a switching signal is supplied to the pixel unit 70 electrically connected to the scanning line G2 through the second scanning line G2 of the plurality of scanning lines Gn, and the first potential signal is different from the pixel unit 70. This is supplied to the dynamic amplification circuit 15. The switching signal is output from the Y-driver circuit 104 to each scanning line Gj, but is different from the scanning signal supplied from the scanning line Gj to the pixel unit 70 when displaying an image. In this way, the switching signal is sequentially supplied to the pixel unit 70 electrically connected to the scanning line Gn in the last row, and each of the first potential signal and the second potential signal is supplied from each pixel unit 70 to the differential amplifier circuit. 15 is supplied.

  Next, a procedure for individually outputting the high potential signal or the low potential signal output from the differential amplifier circuit 15 to the determination unit will be described with reference to FIG.

  In FIG. 3, one end of the signal line Soi extends to the differential amplifier circuit 15, and the other end extends to the X-driver circuit 101. The signal line Soi is disposed so as to intersect with the plurality of scanning lines Gj in the image display region 10a, and the TFT 111 constituting the sampling circuit 110 is electrically connected in the middle of the signal line Soi. When displaying an image in the image display area 10 a, the signal line Soi functions as a data line for supplying an image signal to each pixel unit 70. That is, the signal line Soi is shared with a data line for supplying an image signal to the image display region 10a, and at the time of inspection, a high potential signal or a low potential output from the differential amplifier circuit 15 via the sampling circuit 110. Output the signal to the test circuit. In the present embodiment, the signal line Soi is electrically connected to each part so that the signal line Soi functions as a data line as it is. Since the signal line Sei is not electrically connected to the pixel portion 70, it does not function as a data line when displaying an image, but is electrically connected to the TFT 111 constituting the sampling circuit 110. Accordingly, when a high potential signal or a low potential signal is output from the signal line Soi paired with the signal line Sei to the test circuit, a reference signal to be compared with the high potential signal or the low potential signal is output to the test circuit. Is done. In addition, in each embodiment described later, when the pixel portion is electrically connected to the signal line Sei, the signal line Sei that is one signal line can be shared with the data line. In addition, when the signal lines selected as one signal line in each intersection region Pji are different from each other, as a result, both the signal lines Soi and Sei are shared with the data lines.

  According to the signal latitude Soi shared with the data line, it is not necessary to provide a signal line separately from the data line. Accordingly, it is possible to configure a circuit for outputting a high potential signal or a low potential signal in order to determine the quality of the pixel portion 70 without reducing the size of the opening region in the image display region 10a. Therefore, even when the pitch of the data lines is reduced as the density of the pixel portion is increased in order to improve the image quality, an inspection circuit 4 for inspecting the quality of the pixel portion without reducing the image quality of the pixel portion is provided on the substrate. Can be formed in a narrow region.

  According to the TFT array substrate 10, it is possible to individually determine the quality of a plurality of pixel portions that are electrically connected to one scanning line, and it is possible to identify a pixel portion in which a defect has occurred. When displaying an image, for example, if the transmission gate 6 is switched to the OFF state, the data line can be used to supply the image signal, and the image can be displayed without any problem in the image display area 10a.

  As described above, according to the TFT array substrate of the present embodiment, it is possible to detect whether or not a defect occurs in each pixel unit. In addition, the other signal line that outputs the second potential signal is not electrically connected to the other pixel portion in the intersecting region where the signal line intersects with one scanning line. Is not determined to have occurred. Therefore, according to the TFT array substrate of the present embodiment, it is possible to accurately detect a defect occurring in the pixel portion at the stage of manufacturing the TFT array substrate without omission, and accordingly, for example, a liquid crystal device or the like The yield of the electro-optical device can be increased, and the manufacturing cost of the device can be reduced.

  Next, the timing of various signals when a high potential signal or a low potential signal is output via the signal line Soi and the signal line Sei will be described with reference to FIG. FIG. 9 is a timing chart showing the timing of outputting various signals via the signal line Soi and the signal line Sei. Note that FIG. 9 shows an example in which the potential of the inspection signal supplied in advance to the pixel portion is higher than the intermediate potential, and the other two signal lines except for the signal line Soi and the signal line Sei. Each set also outputs each signal in the same timing chart.

  In FIG. 9, the inspection signal is supplied to the pixel unit 70 by the timing t1. The precharge circuit 25 supplies the precharge signal PCG to the gates of the TFTs 11, 12a and 12b via the precharge signal supply line 44 at timing t1. The TFTs 11, 12 a and 12 b are turned on, and a precharge voltage is applied to the signal line Soi and the signal line Sei through the voltage application wiring 24. Thereby, the potentials of the signal line Soi and the signal line Sei are set to an intermediate potential.

  After the transmission gate 6 is switched to the ON state, the scanning line G1 supplies a switching signal to the pixel unit 70 at the timing t3, and the first potential signal is transmitted to the differential amplifier circuit 15 via the signal line Soi in the intersection region P1i. To be supplied. Note that the scanning line G1 supplies a switching signal to all the pixel portions 70 electrically connected to the scanning line G1, and the TFT 71 included in the pixel portion 70 electrically connected to the scanning line G1 is switched on. It is done. The first potential signal is supplied from each of the plurality of pixel portions 70 electrically connected to the scanning line G1 to the differential amplifier circuit 15 corresponding to these pixel portions.

  Here, when there is no malfunction in the pixel portion 70, the first potential signal having a potential higher than the intermediate potential is different via the signal line Soi in the same manner as the potential of the inspection signal previously supplied to the pixel portion. This is supplied to the dynamic amplification circuit 15. At this time, the first potential signal has a potential slightly higher than the intermediate potential. The potential of the signal line Sei that outputs the second potential signal is a preset intermediate potential, which is slightly lower than the potential of the first potential signal. As described above, when there is no problem in the pixel unit 70, the level relationship between the potential of the inspection signal and the intermediate potential supplied in advance to the pixel unit 70 is the potential of the first potential signal and the second potential. The signal potential level is maintained as it is.

  When the drive signal SAnE is supplied from the second drive signal supply circuit 22 to the TFT 13n at the timing t4, the differential amplifier circuit 15 reduces the potential of the signal line Sei. As a result, the potential of the connection point Se having a lower potential than the potential of the connection point So to which the first potential signal is supplied is lowered to a potential lower than that at the time of supplying the second potential signal.

  At timing t5, when the first drive signal SApE is supplied from the first drive signal supply circuit 21 to the TFT 13p, the differential amplifier circuit 15 uses the potential of the connection point So to which the first potential signal is supplied as the second potential signal. It is higher than the potential at the time of supply.

  At each of timings t4 and t5, among the signals supplied to the differential amplifier circuit 15, the potential at the connection point Se to which the second potential signal having a low potential is supplied is lowered to a first potential having a high potential. The potential of the connection point So to which the signal is supplied is raised higher. Thereby, the level relationship of the potentials of the connection points So and Se is clarified. The differential amplifier circuit 15 outputs a high potential signal having the potential of the connection point So to a determination unit such as a test circuit via the signal line Soi. At the same time, the differential amplifier circuit 15 outputs a reference signal having the potential of the connection point Se to a determination unit such as a test circuit via the signal line Sei.

  The test circuit compares the high potential signal and the reference signal. Since the potential of the high potential signal is higher than that of the first potential signal and the potential of the reference signal is lower than the intermediate potential, the test circuit can detect the second potential signal and a potential slightly higher than the second potential signal. It can be clearly determined that the potential of the high potential signal is higher than the potential of the reference signal as compared with the case of comparing the first potential signals having. Here, since the level relationship between the potential of the inspection signal and the intermediate potential matches the level relationship between the potential of the high potential signal and the potential of the reference signal, the test circuit has a defect in the pixel portion to be inspected. Judge that there is no.

  Next, in order to determine whether the pixel portion electrically connected to the scanning line G2 is good or bad, a precharge voltage is supplied to the signal lines Soi and Sei between timings t6 and t7, and these signal lines are again set to the intermediate potential. Set to

  At timing t8, the scanning line G2 outputs a switching signal, and the switching signal is supplied to the pixel portion 70 that is electrically connected to the scanning line G2. The pixel unit 70 supplied with the switching signal outputs the first potential signal to the differential amplifier circuit 15 via the signal soi in the same manner as the pixel unit 70 electrically connected to the scanning line G1. The signal line Sei supplies the second potential signal to the differential amplifier circuit 15. Accordingly, the high potential signal or the low potential signal corresponding to the pixel portion 70 electrically connected to the scanning line G2 among the pixel portions 70 electrically connected to the signal line Soi in the same manner as the scanning line G1, and A reference signal is output from the differential amplifier circuit to the test circuit via each signal line, and the quality of the pixel unit 70 electrically connected to the scanning line G2 can be determined. In this way, it is possible to sequentially determine the quality of the pixel portion electrically connected to each of the scanning lines G3, G4,..., Gn. In addition, as described above, the high potential signal or the low potential signal output from each differential amplifier circuit 15 and the reference signal can be output to the test circuit for each differential amplifier circuit 15 via the sampling circuit 110. It is possible to determine pass / fail for each pixel portion, and it can be confirmed that no defect has occurred in each of the plurality of pixel portions arranged in the image display region 10a.

  Next, a case where a defect occurs in the pixel portion will be described with reference to FIG. An inspection signal having a potential higher than the intermediate potential is supplied to the pixel unit 70 in advance. At timing t3 when the switching signal is supplied from the scanning line G1 to the pixel portion, the pixel portion 70 supplies a first potential signal having a potential slightly lower than the intermediate potential to the differential amplifier circuit 15. Note that the potential of the connection point So to which the first potential signal having a potential lower than the intermediate potential is supplied is L0 indicated by a dotted line in the drawing. Here, the first potential signal having a potential lower than the intermediate potential corresponds to, for example, the case where the pixel portion includes a TFT in which current leakage occurs or a storage capacitor in which current leakage occurs. .

  When the second drive signal SAnE is supplied from the second drive signal supply circuit 22 to the TFT 13n at the timing t4, the differential amplifier circuit 15 connects the connection point So to which the first potential signal having a potential lower than the intermediate potential is supplied. Is lowered to a lower potential (indicated by a dotted line L1 in the figure). More specifically, the potential of the first potential signal supplied to the connection point So of the differential amplifier circuit 15 is slightly lower than the potential of the second potential signal supplied to the connection point Se of the differential amplifier circuit 15. Therefore, the differential amplifier circuit 15 compares the potentials of the first potential signal and the second potential signal, and lowers the potential of the signal line Soi to a lower potential. The differential amplifier circuit 15 outputs a low potential signal having a potential equal to the potential at the connection point So.

  At timing t5, when the first drive signal SApE is supplied from the first drive signal supply circuit 21 to the TFT 13p, the differential amplifier circuit 15 increases the potential of the second potential signal. Since the potential at the connection point Se is higher than the potential at the connection point So that has been lowered by the differential amplifier circuit 15, the differential amplifier circuit 15 increases the potential at the connection point Se to a potential higher than the intermediate potential. The differential amplifier circuit 15 outputs a reference signal having a potential equal to the potential of the connection point Se whose potential is higher than the intermediate potential.

  As a result, the test circuit detects the low potential signal and the reference signal that maintain the high and low relationship between the first potential signal and the second potential signal supplied to the signal line Soi and the signal line Sei, respectively. The test circuit can clearly detect that the potential of the first potential signal is lower than the intermediate potential by detecting the low potential signal whose potential is lower than that of the first potential signal. Note that the level relationship between the low potential signal and the intermediate potential is opposite to the level relationship of the potential of the inspection signal with respect to the potential of the intermediate potential. In such a case, the test circuit determines that a defect has occurred in the pixel portion. .

  As described above, according to the TFT array substrate 10 of the present embodiment, the potential relationship between the potential of the inspection signal and the intermediate potential supplied in advance to the pixel portion and the high potential signal or the low potential signal whose potential is compared in the test circuit. It can be determined whether or not a defect occurs in the pixel portion by determining whether or not the potential relationship of the reference signal and the potential of the reference signal match. In addition, since the pixel portion is not electrically connected to the signal line Sei that is used as another signal line in each crossing region, the signal line Sei is used as a set in the crossing region. By comparing the potentials of the two signals that are output, it can be determined that a defect has occurred in the normal pixel portion. Thereby, the quality of a pixel part can be determined reliably for every pixel part.

  Next, another arrangement example of the pixel portion will be described with reference to FIGS. Each of FIGS. 10 to 12 is an arrangement diagram schematically showing another arrangement example of the pixel portion. 10 to 12, the signal line Soi and the signal line Sei are physically equivalent signal lines arranged so as to be adjacent to each other along the direction in which the scanning line Gn extends.

  In FIG. 10, the pixel unit 70 is disposed one by one in a crossing region Pji where two signal lines Soi and a signal line Sei intersect the scanning line Gj, and the signal line Sei is connected to the signal line Sei in the crossing region Pji. Only electrically connected. In FIG. 10, the signal line Sei is selected as “one signal line” of the present invention, and all the pixel portions 70 arranged in the image display area are electrically connected to the signal line Sei. The pixel unit 70 supplies the first potential signal to the differential amplifier circuit 15 through the signal line Sei. As a result, similarly to FIG. 3, the differential amplifier circuit 15 outputs a high potential signal or a low potential signal to the determination means such as a test circuit via the signal line Sei.

  In FIG. 11, one pixel line 70 is arranged in a crossing region Pji where two signal lines Soi and one signal line Sei intersect with the scanning line Gj, and are selected as one signal line. The signal line is not fixed to one of the signal line Soi and the signal line Sei in the image display area. More specifically, for example, in the intersection region P1m, the pixel unit 70 is electrically connected to the signal line Sem, and in the intersection region P2m, it is electrically connected to the signal line Som.

  The pixel unit 70 only needs to be electrically connected to only one of the signal line Soi and the signal line Sei in each intersection region ji. The pixel portions 70 arranged one by one in each pair of signal lines in each intersection region Pji are electrically connected to one of the signal lines Soi and the signal lines Sei, thereby electrically connecting the pixel portions. The capacitance generated in each signal line is averaged over the entire image display area.

  More specifically, in the odd-numbered scanning line Gj from the upper side in the drawing, the pixel portion is electrically connected to the signal line Sei, and in the even-numbered scanning line Gj, it is electrically connected to the scanning line Soi. Has been. According to the pixel portion arranged in this way, when viewed in the entire image display area, the same number or the same number of pixel portions are electrically connected to each signal line. The resulting variation in capacity can be averaged over the entire image display area.

  As described above, according to the plurality of signal lines in which the pixel portions are electrically connected, it is possible to suppress the potential fluctuation between the signal lines, and to apply the precharge voltage to each of the signal line Soi and the signal line Sei. Thus, the potentials can be made uniform between these signal lines prior to the inspection. Therefore, it is possible to reduce the output of a signal having an incorrect potential to the test circuit due to fluctuations in the potential of these signal lines, and it is possible to accurately determine the quality of the pixel portion.

  It should be noted that the pixel portions are arranged in the same number or equivalent to each signal line in the entire image display area so that the capacitance generated in each signal line does not vary by electrically connecting the pixel portion to the signal line. Thus, the arrangement of the pixel portion in this example is not limited.

  In FIG. 12, one pixel portion 70 is disposed in each intersection region Pji, and is electrically connected to only one of the signal line Soi and the signal line Sei in the intersection region Pji. In addition, the signal line to which the pixel portion 70 is electrically connected is not fixed to one of the signal line Soi or the signal line Sei as in FIG. However, the pixel unit 70 is arranged so that the capacitance generated in each signal line by electrically connecting the pixel unit to each signal line is averaged in the image display region. More specifically, a total of four pixel portions are electrically connected to the signal line Soi in the drawing, and a total of four pixel portions are also electrically connected to the signal line Sei.

  According to such an arrangement of the pixel portion, the potential of various signals supplied or output through the signal line varies due to the variation in capacitance in the signal line, similarly to the arrangement of the pixel portion shown in FIG. Can be suppressed. Since the capacitance generated in the signal line is averaged in the image display region, the precharge voltage is applied to each of the signal line Soi and the signal line Sei to align the potential between these signal lines, thereby obtaining the first potential with respect to the intermediate potential. A high potential signal or a low potential signal that directly reflects the relative height of the potential of one potential signal can be output. Therefore, it is possible to reduce the output of a signal having an incorrect potential to the test circuit due to fluctuations in the potential of these signal lines, and it is possible to accurately determine the quality of the pixel portion.

  11 and 12, the first potential signal reflecting the quality of the pixel portion and the variation of the intermediate potential compared with the first potential signal can be reduced. Even when the one-potential signal has a slightly higher potential or a slightly lower potential, the potential of the first potential signal has a potential to be output with respect to the intermediate potential. The test circuit can determine whether the pixel portion is good or bad.

  In addition, the potential of one of the two terminals of the storage capacitor 73 that is common to the plurality of pixel portions is set to a predetermined potential, the potential of the other terminal and the potential of the inspection signal supplied to the pixel portion. By setting each of them with a predetermined potential as a reference, it is possible to determine the mode of at least one of the TFT and the storage capacitor.

  According to the arrangement of the pixel portion shown in FIGS. 8, 10, 11, and 12, the pixel portion is electrically connected to a signal line that is maintained at a reference intermediate potential when determining the quality of the pixel portion. Therefore, it is possible to determine pass / fail for each pixel portion electrically connected to the signal line that is maintained at the intermediate potential and the signal line that is paired with the signal line. Thereby, the yield of the electro-optical device can be increased and the manufacturing cost can be reduced. In addition, since the two signal lines are arranged adjacent to each other in the image display area, even if noise or the like is applied to these signal lines, the adjacent signal lines Noise having the same potential or waveform is applied, and there is no problem in inspection that reverses the potential difference for determining the quality of the pixel portion. Therefore, according to the electro-optical device substrate including the pixel unit arranged in this manner, the quality determination of the pixel unit is performed accurately and stably without being affected by noise applied to the signal line or the like. It is possible.

  Hereinafter, another embodiment of the substrate for an electro-optical device according to the first invention of the present invention and the embodiment of the substrate for an electro-optical device according to the second invention of the present invention will be sequentially described. In the following embodiments, portions common to the electro-optical device substrate of the first embodiment are denoted by common reference numerals, and detailed description thereof is omitted for convenience.

(Second Embodiment)
<Configuration of substrate for electro-optical device>
Another embodiment of the substrate for an electro-optical device according to the first aspect of the present invention will be described with reference to FIGS. FIG. 13 is a block diagram illustrating an example of a main circuit configuration of the electro-optical device substrate according to the present embodiment. FIG. 14 illustrates another example of the main circuit configuration of the electro-optical device substrate according to the present embodiment. It is the block diagram which showed. The substrate for an electro-optical device according to this embodiment includes a plurality of differential amplifier circuits that are electrically connected one by one for each of a plurality of signal line groups each including a plurality of sets of signal lines. In addition, since a plurality of transmission gates are individually switched on and off by a plurality of series of signals, a differential amplifier circuit can be electrically connected separately for each set of a plurality of signal lines included in the signal line group. This is different from the configuration of the electro-optical device substrate of the first embodiment. According to the electro-optical device substrate of the present embodiment, the first potential signal and the second potential signal are generated for each set of a plurality of signal lines included in the signal line group according to a plurality of series signals supplied at different timings. Are supplied to a plurality of differential amplifier circuits.

  In FIG. 13, the inspection circuit 204 provided by the TFT array substrate 210 includes a plurality of differential amplifier circuits 15, two transmission gates 16 a and 16 b, a plurality of signal lines Soi and a plurality of signal lines Sei, and “switching means” of the present invention. Are provided with a test signal supply circuit 130 and connection circuits 126a and 126b.

  The differential amplifier circuit 15 is disposed for each of a plurality of signal line groups D each including two sets of signal lines Soi and Sei. The signal line group Dk (k = 1, 2,..., L) includes two signal lines Soi and two signal lines Sei that are arranged adjacent to each other in the horizontal direction in the figure. Includes a set of signal lines. The signal line Soi extends toward the differential amplifier circuit 15 so as to be electrically connected to the connection point So of the differential amplifier circuit 15. Similarly, the signal line Sei extends toward the differential amplifier circuit 15 so as to be electrically connected to the connection point Se of the differential amplifier circuit 15. Each of the signal lines Soi and Sei included in one signal line group Dk joins while extending from the image display region 10a side to the differential amplifier circuit 15, and each of the connection points So and Se is connected as one wiring. They are electrically connected to each other.

  The test signal supply circuit 130 includes a test circuit connection gate terminal circuit 140 and a test gate decoder circuit 141, and is electrically connected to the connection circuits 126a and 126b via the TFTs 15a and 15b.

  The test circuit connection gate terminal circuit 140 supplies a signal for turning on the TFTs 15a and 15b to the gates of the TFTs 15a and 15b. The sources and drains of the TFTs 15 a and 15 b are electrically connected to the wirings 46 a and 46 b extending from the connection circuits 126 a and 126 b and the test gate decoder circuit 141. The test gate decoder circuit 141 supplies two series of signals for switching the transmission gates 16a and 16b to the two transmission gates 16a and 16b at different timings when the pixel portion is inspected. The transmission gates 16a and 16b are switched to the ON state in accordance with the two series of signals supplied from the test gate decoder circuit 141, and the first timing is different from each of the signal line groups included in the signal line group Dk. The potential signal and the second potential signal are supplied to the differential amplifier circuit 15.

  More specifically, for example, in the signal line group Dk, when a signal is supplied via the TFT 15b, the TFT 114b included in the transmission gate 16b is turned on, and the first from each of the signal line Soi and the signal line Sei. The telegraph signal and the second potential signal are supplied to the differential amplifier circuit 15. Further, when a signal is supplied via the TFT 15a, the TFT 114a included in the transmission gate 16a is turned on, and the first potential signal and the second potential signal are respectively transmitted from the signal line Soi-1 and the signal line Sei-1. Is supplied to the differential amplifier circuit 15. As described above, each pair of two signal lines included in one signal line group Dk outputs the first potential signal and the second potential signal at different timings. If one dynamic amplifying circuit 15 is allocated, one differential amplifying circuit 15 can be shared by these two sets of signal lines. In the present embodiment, the signal line group including two signal line groups is taken as an example, but it goes without saying that one signal line group may include three or more signal line groups. . Even in such a case, if a transmission gate corresponding to the number of signal lines is provided so that the group of signal lines included in the signal line group can be switched, one differential amplifier circuit can be used for each set of signal lines. Can be shared.

  Therefore, even when a plurality of pixel circuits are arranged at a narrow pitch in order to improve image quality, a differential amplifier circuit can be provided in a wider space than the pitch of signal lines, and a plurality of differential amplifier circuits can be provided. In the case of having a semiconductor element such as a transistor, these semiconductor elements can be formed easily and with high quality. The timing chart of various signals in each signal line set is the same as the timing chart shown in FIG.

  Since the two signal lines Soi and Sei are arranged adjacent to each other along the direction in which the scanning line Gj extends, noise is equally applied to these signal lines. In the signal lines Soi and Sei, potential fluctuations caused by noise are equal between these signal lines. Similar to the TFT array substrate 10 of the first embodiment, the TFT array substrate 210 has a relative potential level relationship between the potentials of the first potential signal and the second potential signal supplied via the signal lines Soi and Sei. Without changing, it is possible to determine the quality of the pixel portion based on the first potential signal reflecting the quality of the pixel portion and the second potential signal compared with the first potential signal.

  14, the inspection circuit 204 ′ provided by the TFT array substrate 210 ′ is a TFT array substrate shown in FIG. 13 in that a set of two signal lines is constituted by signal lines Soi and Sei that are not adjacent to each other. The configuration is different. In such a TFT array substrate, there may be some potential disturbance between these signal lines due to noise applied to the signal lines Soi and Sei, which are a set of two, but the TFT array shown in FIG. It is possible to determine the quality of the pixel portion stably in accordance with the substrate. In addition, a plurality of semiconductor elements such as TFTs constituting the differential amplifier circuit 15 can be formed with high quality.

  Of course, in the image display area 10a shown in FIGS. 13 and 14, the pixel portion is arranged in the same manner as in FIGS. 8, 10, 11 and 12 described in the first embodiment.

(Third embodiment)
<Configuration of substrate for electro-optical device>
Next, an embodiment of the electro-optical device substrate according to the second invention of the present invention will be described with reference to FIGS. FIG. 15 is a block diagram showing a main circuit configuration of a TFT array substrate 310 which is an example of the electro-optical device substrate of the present embodiment. FIG. 16 shows pixels in the image display area of the TFT array substrate of the present embodiment. It is the figure which showed typically arrangement | positioning of a part. The TFT array substrate of the present embodiment is connected to a plurality of signal lines of a differential amplifier circuit, and a set of two that supplies the first potential signal and the second potential signal to the differential amplifier circuit when inspecting the pixel circuit. Among the signal lines, a signal line to which the pixel portion is electrically connected can be selected. In each of the following examples, the timing chart for inspecting the pixel portion is the same as the timing chart shown in FIG.

  In FIG. 15, the inspection circuit 304 provided by the TFT array substrate 310 includes a plurality of differential amplifier circuits 15, four transmission gates 16 a, 16 b, 16 c and 16 d, and a plurality of “first signal lines” of the present invention. Signal line Soip (i = 1, 2,..., M; m is an integer greater than or equal to 2, p = 1, 2, 3, 4) and “second signal line” of the present invention. A plurality of signal lines Sei (i = 1, 2,..., M; m is an integer of 2 or more), a test signal supply circuit 330 that constitutes an example of the “switching means” of the present invention, and a connection circuit 126 are provided. ing. As will be described later, the TFT array substrate 310 includes a plurality of scanning lines arranged so as to intersect the signal lines Soip and Sei in the image display region 10a.

  The differential amplifier circuit 15 includes a plurality of signal lines Soip (p = 1, 2, 3, 4) and one signal line Sei (i = 1, 2,..., M; m is an integer of 2 or more). Are arranged for each of a plurality of signal groups Dk (k = 1, 2,..., M; m is an integer of 2 or more). The signal lines Soip join in the middle of extending from the image display region 10a side to the differential amplifier circuit 15, and are electrically connected to the connection point So as a single wiring. As will be described later, the signal line Soip is electrically connected to the pixel unit 70 in the image display region. Similarly, the connection point Se extends from the image display region side to the differential amplifier circuit 15 and is electrically connected to the connection point Se.

  The test signal supply circuit 330 includes a test circuit connection gate terminal circuit 140, a test gate decoder circuit 341, and TFTs 15a, 15b, 15c, and 15d.

  The test circuit connection gate terminal circuit 140 supplies a signal for turning on the TFTs 15a, 15b, 15c and 15d to the gates of the TFTs 15a, 15b, 15c and 15d. The sources and drains of the TFTs 15a, 15b, 15c and 15d are electrically connected to wirings 46a, 46b, 46c and 46d extending from the connection circuits 126a, 126b, 126c and 126d, respectively, and the test gate decoder circuit 341. . The test gate decoder circuit 341 supplies four series of signals for switching the transmission gates 16a, 16b, 16c, and 16d to each of the four transmission gates 16a, 16b, 16c, and 16d at different timings when inspecting the pixel portion. . The transmission gates 16a, 16b, 16c, and 16d are turned on at different timings according to the four series of signals, so that the first potential signal is different from each of the signal lines Sokp included in the signal line group Dk. It is supplied to the differential amplifier circuit 15 at timing.

  More specifically, for example, in the signal line group Dk located at the right end in the figure, when a signal is supplied via the TFT 15a, the TFT 114a included in the transmission gate 16a is switched on, and the first signal line Sok4 is connected to the first line. A telegraph signal is supplied to the differential amplifier circuit 15. At this time, in the other signal line group Di, the first telegraph signal is supplied to the differential amplifier circuit 15 through the TFT 114a electrically connected to the wiring 46a among the signal lines Soip included in the signal line group Di. The Therefore, the transmission gate 16a switched to the ON state is connected to the differential amplifier circuit 15 electrically connected to each signal line group Di via one signal line Soip included in each of the plurality of signal line groups Di. To supply the first potential signal. When a signal is supplied via the TFT 15b at a timing different from the timing at which the signal is supplied to the TFT 15a, the TFT 114b included in the transmission gate 16b is switched on, and the first potential signal is sent from the signal line Sok3 to the differential amplifier circuit 15. To be supplied. Also in this case, the first potential signal is supplied from the signal line Soip to the differential amplifier circuit 15 through the TFT 114b electrically connected to the transmission gate 16b in the other signal line group Dk. By sequentially switching the transmission gates 16a, 16b, 16c and 16d to the ON state in this way, the first potential signal can be supplied to the differential amplifier circuit 15 from the signal lines Sokp included in each signal line group Dk at different timings. If one differential amplifier circuit 15 is assigned to each signal line group Dk, one potential signal can be supplied to the differential amplifier circuit 15 at a different timing from each of the plurality of signal lines Sokp included in the signal line group. One differential amplifier circuit 15 can be shared by a plurality of signal lines Sokp included in the signal line group Dk. Therefore, even when a plurality of pixel circuits are arranged at a narrow pitch in order to improve image quality, a differential amplifier circuit can be provided in a wider space than the pitch of signal lines, and a plurality of differential amplifier circuits can be provided. In the case of having a semiconductor element such as a transistor, these semiconductor elements can be formed easily and with high quality. The second potential signal is supplied to the differential amplifier circuit 15 via the signal line Sek included in each signal line group Dk.

  Next, the arrangement of the signal lines and scanning lines and the arrangement of the pixel portions in the image display area 10a will be described in detail with reference to FIG. FIG. 16 is an arrangement diagram schematically showing the arrangement of signal lines, scanning lines, and pixel portions in a part of the image display area.

  In FIG. 16, the signal line group Dk includes a plurality of scanning lines Gj, signal lines Sok1, Sok2, Sok3, and Sok4 arranged adjacent to each other along the extending direction of the scanning line Gj, and the signal line group Dk. A signal line Sek provided at the left end in the figure is provided.

  Each of the signal lines Sok1, Sok2, Sok3, and Sok4, and the signal line Sek extends from the inspection circuit 304 to the image display area 10a and intersects the scanning line Gj. The pixel unit 70 is disposed in an intersection region between each scanning line Gj and the signal lines Sok1, Sok2, Sok3, and Sok4. When the pixel unit 70 is inspected, the signal line Sek constitutes a pair of signal lines Sok1, Sok2, Sok3, and Sok4, and the signal lines Sok1, Sok2, Sok3, and Sok4. A first potential signal is supplied to the differential amplifier circuit 15 from each of the pixel portions 70 electrically connected to the first and second signal lines Sok1, Sok2, Sok3, and Sok4.

  The pixel unit 70 has the same configuration as that of the first embodiment, and a TFT, which is an example of a switching element, is switched on by a switching signal supplied via the scanning line Gj. Thereby, the pixel unit 70 supplies the first potential signal to the differential amplifier circuit 15 through the signal line Sok.

  Since the signal line Sek included in each signal line group Dk is electrically connected to the connection point Se of the differential amplifier circuit 15 without being electrically connected to the transmission gates 16a, 16b, 16c and 16d, A second potential signal is supplied to the connection point Se of the differential amplifier circuit 15 from the signal line Sek maintained at the intermediate potential during the inspection of the pixel portion. Similar to the first and second embodiments, the differential amplifier circuit 15 compares the first potential signal and the second potential signal, and outputs a high potential signal or a low potential signal to the test circuit via the signal line Sokp. The pixel portion is not electrically connected to the signal line Sei, and is only electrically connected to the signal line Soip.

  The signal line Sei forms a set of two signal lines together with one of the signal lines Soip at the time of inspection, and is used as a dedicated signal line for maintaining the connection point Se of the differential amplifier circuit at an intermediate potential. According to the TFT array substrate 310 of this example, as in the TFT array substrate 10 of the first embodiment, the level relationship between the first potential signal and the second potential signal compared by the differential amplifier circuit 15 is clarified. Thus, it is possible to accurately determine the quality of the pixel portion without being affected by noise applied to each signal line.

  In this example, the signal line group Dk includes four signal lines Sokp. However, the signal line group Dk is not limited to four, and one signal line group may include two or more signal lines Sok. In such a case, one signal can be obtained by sequentially supplying the first potential signal via the signal lines Sokp at different timings by the same number of transmission gates as the number of signal lines Sok included in the signal line group Di. The differential amplifier circuit 15 can be shared by a plurality of signal lines Sokp included in the line group Dk.

  Next, a modification of the TFT array substrate of this embodiment will be described. FIG. 17 is a block diagram of a modification of the TFT array substrate of the present embodiment. FIG. 18 is a diagram schematically showing the arrangement of the pixel portions in the image display area of the TFT array substrate 410 of this example.

  In FIG. 17, the inspection circuit 404 provided by the TFT array substrate 410 includes a plurality of branch lines of the signal line Sei as a signal line for supplying the second potential signal to the differential amplifier circuit 15 when inspecting the pixel portion. The circuit configuration of the above-described TFT array substrate 310 is different in that it is provided with a SIP. Similar to the TFT array substrate 310, the TFT array substrate 410 has one differential amplifier circuit 15 assigned to one signal line group Dk, and includes a signal line Sokp and a branch line Sekp included in the signal line group Dk. It is shared by each set of two signal lines.

  In FIG. 18, the signal lines Sekp and the branch lines Sokp extending to the image display area are alternately arranged along the direction in which the scanning line Gj extends. The branch line Sekp and the signal line Soki are adjacent in the image display area, and the two adjacent signal lines constitute a set of two signal lines. When inspecting the pixel portion, the first potential signal is output to the differential amplifier circuit 15 through the signal line Soki constituting the set of two signal lines, and the second potential is output through the branch line Seki. The potential signal is supplied to the differential amplifier circuit 15. Note that the branch line Sekp is a branch line in which a signal line electrically connected to the connection point Se of the differential amplifier circuit 15 branches as a plurality of signal lines in the image display region. The pixel unit 70 is disposed in an intersecting region of the plurality of scanning lines Gj and the signal line Sokp and is electrically connected to the signal line Sokp.

  According to the TFT array substrate 410 of this example, the quality of the pixel unit 70 can be accurately determined in the same manner as the TFT array substrate 310. More specifically, since the signal line Sokp and the branch line Sekp are adjacent to each other, noise applied to the signal line Sokp that supplies the first potential signal and the branch line Sekp that supplies the second potential signal at the time of inspection. And the relative potential level relationship between the first potential signal and the second potential signal supplied to the differential amplifier circuit 15 does not change. Therefore, even if the potentials of the first potential signal output from the pixel unit 70 via the signal line Sokp and the second potential signal supplied to the differential amplifier circuit 15 via the branch line Sekp are small, there is a difference. The dynamic amplifier circuit 15 can output a high potential signal or a low potential signal to a determination means such as a test circuit in accordance with this slight potential difference.

  As an electro-optical device to which the present invention can be applied, in addition to the liquid crystal panel shown in the above-described embodiments, an organic EL device, an electrophoretic device, an electron emission device (Field Emission Display and Conduction Electron-Emitter Display), Examples thereof include DMD (Digital Micromirror Device) and LCOS (Liquid Crystal On Silicon) which is an example of a reflective liquid crystal device.

(Electronics)
Next, an example in which the above-described liquid crystal panel is applied to various electronic devices will be described with reference to FIGS. FIG. 19 is a perspective view of a mobile personal computer to which the above-described liquid crystal panel is applied. In FIG. 19, a computer 1200 includes a main body 1204 provided with a keyboard 1202 and a liquid crystal display unit 1206. The liquid crystal display unit 1206 is configured by adding a backlight to the back surface of the liquid crystal panel 1005.

  Further, an example in which the above-described liquid crystal panel is applied to a mobile phone will be described. FIG. 20 is a perspective view of a mobile phone to which the above-described liquid crystal panel is applied. In FIG. 20, a mobile phone 1300 includes a reflective liquid crystal device 1005 together with a plurality of operation buttons 1302. In the reflective liquid crystal device 1005, a front light is provided on the front surface thereof as necessary.

  According to each example of the electronic apparatus of the present embodiment, when a substrate for an electro-optical device, such as a TFT array substrate on which various elements such as TFTs are formed, is detected at the stage where the substrate is formed. Therefore, the yield of the electro-optical device can be increased and the base manufacturing cost can be reduced. In addition, since the quality of the pixel portion can be determined for each pixel portion, repair or the like can be easily performed.

According to the electronic apparatus according to the present invention, in addition to the electronic apparatus described with reference to FIGS. 19 to 20, a projection display device, a television set, a mobile phone, Various electronic devices such as an electronic notebook, a word processor, a viewfinder type or a monitor direct-view type video tape recorder, a workstation, a videophone, a POS terminal, and a touch panel can be realized. (The various devices shown here are classified as electro-optical devices. They are not included in electronic equipment.)
The present invention is not limited to the above-described embodiments, and can be appropriately changed without departing from the gist or concept of the invention that can be read from the claims and the entire specification. An apparatus substrate, an electro-optical device including the same, and an electronic apparatus including such an electro-optical device are also included in the technical scope of the present invention.

1 is a plan view illustrating a configuration of an electro-optical device substrate according to a first embodiment. It is the HH 'sectional view taken on the line of FIG. FIG. 3 is a block diagram illustrating a main circuit configuration of the electro-optical device substrate according to the first embodiment. It is a circuit diagram which shows the circuit structure of a differential amplifier circuit. It is a circuit diagram which shows the circuit structure of a pixel part. It is a circuit diagram which shows the circuit structure of a pull-up circuit. It is a circuit diagram which shows the circuit structure of a pull-down circuit. It is the arrangement figure which showed typically an example of arrangement of a pixel part, a signal line, and a scanning line in an image display field. 6 is a timing chart at the time of inspection in the electro-optical device substrate according to the first embodiment. It is the arrangement figure which showed typically other examples of arrangement of a pixel part, a signal line, and a scanning line in an image display field. It is the arrangement figure which showed typically other examples of arrangement of a pixel part, a signal line, and a scanning line in an image display field. It is the arrangement figure which showed typically other examples of arrangement of a pixel part, a signal line, and a scanning line in an image display field. FIG. 6 is a block diagram illustrating an example of a main circuit configuration of an electro-optical device substrate according to a second embodiment. FIG. 10 is a block diagram illustrating another example of the main circuit configuration of the electro-optical device substrate according to the second embodiment. FIG. 10 is a block diagram illustrating an example of a main circuit configuration of an electro-optical device substrate according to a third embodiment. It is the arrangement figure which showed typically an example of arrangement of a pixel part, a signal line, and a scanning line in an image display field. FIG. 12 is a block diagram illustrating another example of the main circuit configuration of the electro-optical device substrate according to the third embodiment. It is the arrangement figure which showed typically other examples of arrangement of a pixel part, a signal line, and a scanning line in an image display field. It is a perspective view of an example of the electronic device concerning the present invention. It is a perspective view of the other example of the electronic device which concerns on this invention.

Explanation of symbols

  10, 210, 310, 410 TFT array substrate, 4, 204, 204 ′, 304, 404 inspection circuit, 15 differential amplifier circuit, 70 pixel unit

Claims (15)

A substrate,
A plurality of scanning lines and a plurality of signal lines arranged to cross each other on the substrate;
One of the plurality of signal lines is provided corresponding to each intersection of the plurality of signal lines configured as a set of two signal lines and the plurality of scanning lines. A plurality of pixel circuits electrically connected to only one of the two signal lines corresponding to each of the two signal lines;
A first potential signal is supplied via the one signal line and a second potential signal is supplied via the other signal line of the two signal lines, and (i) the potential of the first potential signal is When the potential is lower than the potential of the second potential signal, a low potential signal having a potential lower than the potential of the first potential signal is transmitted via the one signal line, and (ii) the potential of the first potential signal is And amplifying means for outputting a high potential signal having a potential higher than the potential of the first potential signal through the one signal line when the potential is higher than the potential of the second potential signal. Electro-optic device substrate. Each of the plurality of pixel circuits has a switching element electrically connected to the one scanning line,
The first potential signal is supplied to the amplifying unit via the one signal line in a state where the switching element is turned on in response to the switching signal supplied via the one scanning line. The substrate for an electro-optical device according to claim 1. A transmission gate provided in a region near the amplifying means when viewed from the pixel circuit on the substrate surface of the substrate, and electrically connected in the middle of the pair of signal lines;
Switching means for switching the transmission gate on and off, and
The first potential signal and the second potential signal are supplied to the amplifying unit through the two signal lines in a state where the transmission gate is switched on by the switching unit. The substrate for an electro-optical device according to claim 1 or 2. The amplifying unit has a plurality of differential amplifier circuits electrically connected one by one for each set of the plurality of signal lines,
The transmission gate is a single transmission gate that is electrically connected in common to the set of the plurality of signal lines so as to be switched on and off by a series of signals supplied from the switching means,
The first potential signal and the second potential signal are supplied to the plurality of differential amplifier circuits in a state where the single transmission gate is switched on according to the one series of signals. The substrate for an electro-optical device according to claim 3. The amplifying means includes a plurality of differential amplifier circuits electrically connected one by one for each of a plurality of signal line groups each including a plurality of sets of the plurality of signal lines.
The transmission gate is electrically connected to each of a plurality of signal line groups included in the signal line group so as to be individually switched on and off by a plurality of series of signals supplied from the switching means. A transmission gate,
The first potential signal and the second potential signal may be transmitted from the plurality of transmission lines for each of a plurality of signal lines included in the signal line group in accordance with a plurality of series of signals supplied from the switching unit at different timings. The substrate for an electro-optical device according to claim 3, wherein the substrate is supplied to the plurality of differential amplifier circuits in a state where a gate is switched on. The one signal line is shared with a data line for supplying an image signal to the pixel circuit,
The high-potential signal or the low-potential signal is supplied to the determination unit for each pixel circuit in a state where a sampling circuit that samples the image signal on the data line is switched on. Item 6. The substrate for an electro-optical device according to any one of Items 1 to 5. The one signal line and the other signal line are adjacent to each other along a direction in which the plurality of scanning lines out of the plurality of signal lines extend. The substrate for an electro-optical device according to Item. The pixel circuit is arranged so that a variation in capacitance generated in the one signal line when the pixel circuit is electrically connected to the one signal line is averaged in the image display region. The substrate for an electro-optical device according to claim 1, wherein the substrate is an electro-optical device. A potential setting for setting the potentials of the two signal lines so that the potentials of the two signal lines are equalized before the first potential signal and the second potential signal are supplied to the amplification means. The substrate for an electro-optical device according to claim 1, further comprising means. A substrate,
A plurality of scanning lines arranged to extend to an image display area on the substrate;
A plurality of first signal lines arranged to intersect the plurality of scanning lines in the image display region;
A second signal line arranged for each signal line group including N (N is a natural number of 2 or more) first signal lines among the plurality of first signal lines;
A plurality of pixel circuits provided in each of a plurality of intersecting regions where the plurality of scanning lines and the plurality of first signal lines intersect, and electrically connected to each of the plurality of first signal lines;
A first potential signal is supplied from the pixel circuit via the first signal line and a second potential signal is supplied via the second signal line. (I) The potential of the first potential signal is the first potential signal. When the potential is lower than the potential of the two-potential signal, a low-potential signal having a potential lower than the potential of the first potential signal is transmitted via the first signal line, and (ii) the potential of the first potential signal is the second potential. When the potential is higher than the potential of the potential signal, a high potential signal having a potential higher than the potential of the first potential signal is output via the first signal line to a determination unit that determines whether the pixel circuit is good or bad by voltage logic. An electro-optical device substrate, comprising: Each of the plurality of pixel circuits has a switching element electrically connected to the one scanning line,
The first potential signal is supplied to the amplifying unit through the first signal line in a state where the switching element is turned on in response to the switching signal supplied through the one scanning line. The substrate for an electro-optical device according to claim 10. The second signal line is branched into a plurality of branch lines extending along a direction in which the first signal line extends so as to be adjacent to the plurality of first signal lines in the image display region. The substrate for an electro-optical device according to claim 11. A plurality of signal lines provided in a region near the amplifying means when viewed from the pixel circuit on the substrate surface of the substrate and electrically connected in common to a plurality of signal line groups each including a plurality of the first signal lines. The transmission gate of
Switching means for switching on and off the plurality of transmission gates;
The amplification means includes a plurality of differential amplifier circuits electrically connected one by one for each signal group,
The plurality of transmission gates are separately electrically connected to a plurality of first signal lines included in the signal line group,
The first potential signal includes a plurality of second signal lines included in the signal line group in a state in which the plurality of transmission gates are sequentially switched on according to a plurality of series of signals supplied from the switching unit at different timings. The substrate for an electro-optical device according to claim 11 or 12, wherein each signal line is supplied to the differential amplifier circuit at different timings. An electro-optical device comprising the electro-optical device substrate according to claim 1. An electronic apparatus comprising the electro-optical device according to claim 14.

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