JP2009192826A - Electro-optic device and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce sequential stripes on a display screen and to display high-quality images in an electro-optic device such as a liquid crystal device. <P>SOLUTION: The electro-optic device includes: a plurality of gate wiring lines (701) each being electrically connected to the gate of a selection switch (71) and to a corresponding one selection signal supply line in N pieces of selection signal supply lines (6) and having a gate wiring portion (701b) extending along a second direction (Y direction) intersecting a first direction (X direction); and a plurality of image signal lines (300) provided to the respective N pieces of selection switches corresponding to a data line group (6ag), each having an image signal line portion (320a) which is electrically connected to the source of the corresponding selection switch in the N pieces of switches and extends along the second direction and is formed with wiring width wider than the gate wiring portion. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a technical field of an electro-optical device such as a liquid crystal device, and an electronic apparatus such as a liquid crystal projector including the electro-optical device.

  In this type of electro-optical device, for example, as disclosed in Patent Document 1, a plurality of data lines are driven for each data line group including a group of N data lines (where N is an integer of 2 or more). For this purpose, a selection switch is provided for each data line. Each selection switch supplies an image signal for each data line group based on the selection signal. Patent Document 1 discloses a technique for making each wiring width equal to each other for each source line connected electrically to each source of a selection switch corresponding to each data line group. .

  Here, a driving method (that is, a demultiplexer method or a hybrid method) is adopted in which image signals to be supplied to the N data lines are input in a time division manner and N data lines are selected and supplied in a time division manner. May be. In an electro-optical device employing such a demultiplexer method, an image signal supplied from an image signal line is input to a plurality of selection switches. In each data line group, N data lines are selected by a selection switch based on one of N series of selection signals, and an image signal is supplied.

JP-A-5-307165

  However, in an electro-optical device driven by a hybrid system, in each selection switch driven by an N-sequence selection signal, noise may occur in the image signal for each N-sequence in the wiring connected to the source. . By supplying such an image signal from the selection switch to the data line, vertical streak-like unevenness along the data line for each of the N series (hereinafter referred to as “series streak”). May occur on the display screen and may be visually recognized. As a result, there arises a problem that display quality in the electro-optical device is deteriorated.

  The present invention has been made in view of the above problems, for example, and provides an electro-optical device capable of reducing series stripes and displaying a high-quality image, and an electronic apparatus including the electro-optical device. Is an issue.

  In order to solve the above problems, an electro-optical device of the present invention includes a plurality of pixel electrodes on a substrate, a plurality of scanning lines and a plurality of data lines intersecting each other in a pixel region provided with the plurality of pixel electrodes. One data line is provided for each data line in a peripheral area located around the pixel area, and each of the data lines includes N transistors (where N is an integer of 2 or more). For each group, a plurality of selection switches for selecting N data lines belonging to the data line group at different timings based on N series selection signals and outputting image signals, and the scanning lines in the peripheral region N selection signal supply lines for supplying the selection signal for each of the N series, a gate of the selection switch, and the N selection signal supply lines. Correspondence A plurality of gate lines each having a gate line portion extending along a second direction intersecting the first direction and N corresponding to the data line group. Provided for each of the selection switches and electrically connected to the sources of the N selection switches, extending along the second direction, and having a wiring width wider than the gate wiring portion. A plurality of image signal lines each having an image signal line portion.

  According to the electro-optical device of the present invention, during the operation, an image signal is supplied to an image signal line from an image signal supply circuit provided outside, for example, via an image signal terminal. The image signals supplied to the image signal lines are supplied to a plurality of selection switches corresponding to the number corresponding to the data line group, that is, every N selection switches. The plurality of selection switches are driven based on N series selection signals, respectively, and select data lines for each series to supply image signals. Thus, for each data line group, an image signal is supplied from each of the N selection switches to each of the N data lines based on the N series of selection signals, and is input to the corresponding pixel. At the same time, for example, a scanning signal is supplied to each pixel from the scanning line driving circuit via the scanning line. For example, a pixel switching transistor provided for each pixel selectively supplies an image signal to the pixel electrode in accordance with the scanning signal. As a result, active matrix driving is performed in the electro-optical device.

  In the electro-optical device of the present invention, N selection signal supply lines to which N series selection signals are supplied are provided along the first direction (in other words, the X direction), and the gates of the selection switches are provided at the gates of the selection switches. The selection signal is supplied from the selection signal supply line via the gate wiring portion for each of the N series. The gate wiring portion is branched from a selection signal supply line provided along the first direction, and is formed to extend along the second direction (that is, the direction intersecting the first direction, in other words, the Y direction). The An image signal is supplied to the source of each selection switch from an image signal line portion constituting a part of the corresponding image signal line. The image signal line portion is formed so as to extend along the second direction. Here, typically, the gate wiring portion and the image signal line portion that are respectively electrically connected to the same selection switch are at least partially adjacent to each other. Each of the plurality of image signal lines supplies an image signal to each of the N selection switches corresponding to the data line group.

  Particularly in the present invention, the image signal line portion is formed with a wider wiring width than the gate wiring portion. Therefore, for example, as compared with the case where the image signal line portion is formed with the same width as the gate wiring portion, the wiring resistance of the image signal line portion can be further reduced.

  For example, if no measures are taken and the gate wiring portion and the image signal line portion are arranged close to each other for each selection switch, the image signal line is caused by an electrical adverse effect between the gate wiring portion and the selection switch. There is a risk that noise may occur for each series in the image signal in the portion. However, according to the present invention, since the wiring resistance of the image signal line portion can be lowered as described above, it is possible to further reduce the adverse electrical effect between the image signal line portion and the gate wiring portion. In other words, according to the present invention, since the image signal line portion has a wider wiring width than the gate wiring portion, the image signal is changed as the potential of the gate wiring portion varies due to the supply of the selection signal. It is possible to suppress or prevent the potential of the line portion from fluctuating. Therefore, it is possible to further reduce the noise of the image signal in the image signal line portion, and it is possible to reduce or eliminate the series streak to such an extent that it is not noticeable on the display screen.

  Therefore, according to the electro-optical device of the present invention as described above, it is possible to display a high-quality image.

  In one aspect of the electro-optical device of the present invention, the image signal line portion is arranged on the same layer as the gate wiring portion.

  According to this aspect, for each selection switch, when the gate wiring portion and the image signal line portion are located in the same layer and close to each other, there is an electrical adverse effect between the image signal line portion and the gate wiring portion. This can be further reduced.

  In order to solve the above problems, an electronic apparatus according to the present invention includes the above-described electro-optical device according to the present invention (including various aspects thereof).

  According to the electronic apparatus of the present invention, since the above-described electro-optical device according to the present invention is provided, the series streaks on the display screen can be reduced. Therefore, a projection display device, television, mobile phone, electronic notebook, word processor, viewfinder type or monitor direct-view type video tape recorder, workstation, videophone, POS terminal, touch panel capable of high-quality display Various electronic devices such as can be realized. Further, as the electronic apparatus of the present invention, for example, an electrophoretic device such as electronic paper can be realized.

  The operation and other advantages of the present invention will become apparent from the best mode for carrying out the invention described below.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, an active matrix driving type liquid crystal device, which is an example of the electro-optical device of the present invention, is taken as an example.

  First, the overall configuration of the liquid crystal device according to the present embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view showing the overall configuration of the liquid crystal device according to the present embodiment, and FIG. 2 is a cross-sectional view taken along the line HH ′ of FIG.

  1 and 2, in the liquid crystal device 100 according to the present embodiment, the element substrate 10 and the counter substrate 20 are disposed to face each other. A liquid crystal layer 50 is sealed between the element substrate 10 and the counter substrate 20, and the element substrate 10 and the counter substrate 20 are positioned around an image display area 10a as an example of the “pixel area” according to the present invention. They are bonded to each other by a sealing material 52 provided in the sealing area. The sealing material 52 is made of an ultraviolet curable resin for bonding the two substrates together, and is applied on the element substrate 10 in the manufacturing process and then cured by ultraviolet irradiation. Further, a gap material (not shown) such as glass fiber or glass bead is sprayed in the sealing material 52 to set the distance between the element substrate 10 and the counter substrate 20 (inter-substrate gap) to a predetermined value. .

  In FIG. 1, a light-shielding frame light-shielding film 53 that defines the frame area of the image display region 10a is provided on the counter substrate 20 side in parallel with the inside of the seal region where the sealing material 52 is disposed. Of the peripheral region, an external circuit connection terminal 102 including an image signal terminal to which an image signal is supplied is provided along one side of the element substrate 10 in a region located outside the seal region where the sealing material 52 is disposed. ing. The demultiplexer 7 is provided so as to be covered with the frame light-shielding film 53 on the inner side of the seal region along one side. Further, the scanning line driving circuit 104 is provided so as to be covered with the frame light-shielding film 53 inside the seal region along two sides adjacent to the one side. On the element substrate 10, vertical conduction terminals 106 for connecting the two substrates with the vertical conduction material 107 are arranged in regions facing the four corner portions of the counter substrate 20. Thus, electrical conduction can be established between the element substrate 10 and the counter substrate 20.

  On the element substrate 10, lead wirings 90 are formed for electrically connecting the external circuit connection terminals 102 to the demultiplexer 7, the scanning line driving circuit 104, the vertical conduction terminals 106, and the like.

  In FIG. 2, a laminated structure in which wirings such as pixel switching TFTs, which are driving elements, scanning lines, and data lines are formed is formed on the element substrate 10. In the image display area 10a, a pixel electrode 9a is provided in an upper layer of wiring such as a pixel switching TFT, a scanning line, and a data line. An alignment film (not shown) is formed on the pixel electrode 9a. On the other hand, a light shielding film 23 is formed on the surface of the counter substrate 20 facing the element substrate 10. A counter electrode 21 made of a transparent material such as ITO (Indium Tin Oxide) is formed on the light shielding film 23 so as to face the plurality of pixel electrodes 9a. An alignment film (not shown) is formed on the counter electrode 21. Further, the liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several types of nematic liquid crystals are mixed, and takes a predetermined alignment state between the pair of alignment films.

  Although not shown here, on the element substrate 10, in addition to the demultiplexer 7 and the scanning line driving circuit 104, an inspection circuit for inspecting the quality, defects, etc. of the liquid crystal device during production or at the time of shipment, An inspection pattern or the like may be formed.

  Next, the electrical configuration of the liquid crystal device according to the present embodiment will be described with reference to FIG. FIG. 3 is a circuit diagram showing an electrical configuration of the liquid crystal device according to this embodiment.

  In FIG. 3, the liquid crystal device 100 includes a demultiplexer 7 and a scanning line driving circuit 104 on an element substrate 10. The image signal supply circuit 400 as an external circuit is electrically connected to the image signal terminal 102v among the external circuit connection terminals 102 on the element substrate 10.

  In the image display region 10a on the element substrate 10, 320 scanning lines 11a are provided so as to extend in the row direction (that is, the X direction), and four lines are grouped into each data line group 6ag. 480 (= 120 × 4) columns of data lines 6a are provided so as to extend in the column direction (that is, the Y direction) and to keep electrical insulation from each scanning line 11a. ing. The numbers of scanning lines 11a and data lines 6a are not limited to 320 and 480, respectively. The number of data lines constituting each data line group 6ag is “4” in the present embodiment, but may be “2” or more.

  The pixel electrodes 9a are respectively arranged corresponding to the intersections of 320 scanning lines 11a and 480 data lines 6a. Therefore, in the present embodiment, the pixel electrodes 9a are arranged in a matrix form with a predetermined pixel pitch of 320 rows by 480 columns. Although not shown here, between each pixel electrode 9a and the data line 6a, a pixel whose conduction state and non-conduction state are controlled according to a scanning signal supplied via the scanning line 11a. Capacitance wirings for storage TFTs that maintain the voltage applied to the switching TFT and the pixel electrode 9a for a long time are formed.

  Here, in this embodiment, in order to distinguish the four columns of data lines 6a constituting the data line group 6ag, they may be referred to as a, b, c, and d series in order from the left. Specifically, the a series is the data line 6a in the 1, 5, 9,..., 477th column, the b series is the data line 6a in the 2, 6, 10,. Is the data line 6a in the 3, 7, 11, ..., 479th column, and the d series is the data line 6a in the 4, 8, 12, ..., 480th column.

  3, the scanning line driving circuit 104 supplies scanning signals G1, G2, G3,..., G320 to the scanning lines 11a in the 1, 2, 3,. More specifically, the scanning line driving circuit 104 sequentially selects the scanning lines 11a in the first, second, third,..., 320th row over a period of one frame, and uses the scanning signal to the selected scanning line as a selection voltage. The scanning signal to other scanning lines is set to the L level corresponding to the non-selection voltage.

  The image signal supply circuit 400 has a separate configuration from the element substrate 10 and is electrically connected to the element substrate 10 via the image signal terminal 102v during a display operation. The image signal supply circuit 400 corresponds to the scanning line 11a selected by the scanning line driving circuit 104 and the data line 6a selected by the demultiplexer 7 among the four columns of data lines 6a belonging to each data line group 6ag. An image signal VIDi (i = 1,..., 120) having a voltage corresponding to the gradation of the pixel including the pixel electrode 9a is output to the pixel electrode 9a. The image signal VIDi supplied from the image signal supply circuit 400 to the image signal terminal 102v is supplied to the demultiplexer 7 through the image signal line 300.

  In the present embodiment, as described above, the number of columns of the data line 6a is “480”, and since these are grouped every four columns, the number of image signal terminals 102v is “120”. .

  The demultiplexer 7 includes a plurality of transistors 71 provided as an example of the “plurality of selection switches” according to the present invention, provided for each data line 6a.

  Here, the configuration of the transistor 71 will be described in more detail with reference to FIG. 4 in addition to FIG. 3. FIG. 4 is a circuit diagram showing in more detail the configuration focusing on the transistor corresponding to one data line group in the demultiplexer.

  3 and 4, in FIG. 3, among the first to 120th data line groups 6ag corresponding to the image signals VID1 to VID120, the mth data line group (where m is an integer from 1 to 120). Focusing on 6ag, in FIG. 4, the transistor 71 is, for example, an n-channel type, and each drain is electrically connected to one end of the data line 6 a via the drain wiring 705.

  The sources of the four transistors 71 corresponding to the data lines 6a belonging to the data line group 6ag are commonly connected to the image signal lines 300 corresponding to the data line group 6ag via the respective source lines 703. That is, the m-th data line group 6ag includes the (4m-3) th column of the a series, the (4m-2) th column of the b series, the (4m-1) th column of the c series, and the (4m) of the d series. It consists of the data line 6a of the column. The sources of the transistors 71 corresponding to the four columns of data lines 6a are electrically connected to the source wiring 703 in common, and the image signal VID (m) is supplied.

  Here, the image signal line 300 shown in FIG. 3 includes, for example, an image signal input line 310 to which the image signal VID (m) is input in FIG. Are connected electrically to the lead-out wiring 320 for commonly connecting the source wirings 703 of the transistors 71 corresponding to. As will be described later, the lead-out wiring 320 has four image signal line portions 320a (see FIGS. 5 and 6) branched toward the transistor 71 for connection to the source wiring 703 of the four transistors 71, respectively. Have.

  Also, four selection signals to which four series of selection signals Sel1 to Sel4 for selecting any of the data lines 6a of the a series, b series, c series, and d series are supplied on the element substrate 10. A supply line 6 is provided. Each of the four selection signal supply lines 6 is formed to extend along the Y direction. Each of the four selection signal supply lines 6 is wired in common to a plurality of transistors 71 to which the same selection signal is supplied for each of the four systems.

  The selection signal Sel1 is supplied from the selection signal supply line 6 through the gate wiring 701 to the gate of the transistor 71 corresponding to the data line 6a in the (4m-3) th column. Similarly, in the (4m-2) th column, Selection signals Sel2, Sel3, and Sel4 are supplied to the gates of the transistors 71 corresponding to the data lines 6a in the (4m-1) th column and the (4m) th column. The selection signals Sel1, Sel2, Sel3, and Sel4 are supplied via an external circuit connection terminal 102 from a timing control circuit as an external circuit (not shown). Each of the four selection signal supply lines 6 is routed from the corresponding external circuit connection terminal 102 onto the element substrate 10.

  Here, the operation of the liquid crystal device configured as described above will be described with reference to FIG.

  The scanning line driving circuit 104 sets the scanning signals G1,..., G320 to the H level (that is, the selection voltage) sequentially and exclusively every horizontal period over a period of one frame (nth frame).

  Here, in one horizontal period, the selection signals Sel1, Sel2, Sel3, and Sel4 supplied from the timing control circuit are exclusively H level in this order, and the image signal supply circuit 400 synchronizes with the supply. The image signals VID1, VID2, VID3,..., VID120 are supplied to the line 300. Here, the image signals VID1, VID2, VID3,..., VID120 output from the image signal supply circuit 400 are four series of data in each of the first, second, third,. Corresponding to the line 6a, there are data voltages time-series into four series. In the demultiplexer 7, the time series data voltages of the image signals VID 1, VID 2, VID 3,. As shown below, the data lines are grouped into four series of data lines 6a in each data line group 6ag.

  Specifically, the image signal supply circuit 400 determines that the jth row when the selection signal Sel1 is at the H level in the period when the scanning signal Gj (i = 1,..., 320) at the jth row is at the H level. Image signals VID1, VID2, VID3,..., VID120 that are higher or lower than the counter electrode potential LCCOM by a voltage corresponding to the gray level of the pixel corresponding to the intersection of the eye scanning line 11a and the a-series data line 6a. , 1, 2, 3,..., 120 at a time, corresponding to the 120th data line group 6ag. At this time, since only the selection signal Sel1 is at the H level, the a-series data line 6a is selected (that is, only the transistor 71 corresponding to the a-series data line 6a is turned on). As a result, the image signals VID1, VID2 , VID3,..., VID120 are respectively supplied to the data lines 6a of the a series (1, 5, 9,..., 477th column). On the other hand, when the scanning signal Gj is at the H level, the pixel switching TFT is turned on (conductive) in all the pixels located in the j-th row, and therefore the image signal VID1 supplied to the a-series data line 6a. , VID2, VID3,..., VID120 are applied to the pixel electrodes 9a of j rows and 1 column, j rows and 5 columns, j rows and 9 columns,.

  Next, when the selection signal Sel2 becomes H level, the image signal supply circuit 400 corresponds to the gradation of the pixel corresponding to the intersection of the j-th scanning line 11a and the b-series data line 6a. The voltage image signals VID1, VID2, VID3,..., VID120 are simultaneously output in correspondence with the first, second, third,. At this time, since only the selection signal Sel2 is at the H level, as a result of selecting the b-sequence data line 6a, the image signals VID1, VID2, VID3,..., VID120 are respectively b-sequence (2, 6, 10,. 478th) data line 6a and applied to the pixel electrode 9a of j row 2 column, j row 6 column, j row 10 column,..., J row 478 column, respectively.

  Similarly, the image signal supply circuit 400, when the selection signal Sel3 becomes H level during the period in which the j-th scanning signal Gj becomes H level, the j-th scanning line 11a and the c-series data line 6a. When the selection signal Sel4 attains an H level when the selection signal Sel4 becomes H level, an image of a voltage corresponding to the gradation of the pixel corresponding to the intersection of the j-th scanning line 11a and the d-series data line 6a Signals VID1, VID2, VID3,..., VID120 are simultaneously output in correspondence with the first, second, third,..., 120th data line group 6ag, and thereby the c series (3, 7, 11,. 479th column) data line 6a and applied to pixel electrode 9a of j row 3 column, j row 7 column, j row 11 column,..., J row 479 column, respectively, and d series (4 , 8, 12, ... 480th column Is supplied to the data line 6a of each j row 4 column, row j 8 column, row j 12 column, ..., it is applied to the pixel electrode 9a of the j rows 480 columns.

  Thereby, the operation of writing the voltage of the image signal corresponding to the gradation to the pixel in the j-th row is completed. Note that the voltage applied to the pixel electrode 9a is held by the liquid crystal capacitor until the next (n + 1) th frame writing even when the scanning signal Gj becomes L level.

  Next, an example of the configuration of the four transistors 71 corresponding to the mth data line group 6ag shown in FIG. 4 will be described with reference to FIGS. FIG. 5 is a plan view showing the configuration of two transistors adjacent to each other, and FIG. 6 is a cross-sectional view taken along line A-A ′ of FIG. 5. In FIGS. 5 and 6, the scale of each layer / member is different for each layer / member so that each layer / member can be recognized on the drawing. Further, in the cross-sectional portion of FIG. 6, the configuration is shown by paying attention only to the layers in which the main components shown in FIG. 5 are arranged.

  Here, the four transistors 71 shown in FIG. 4 have the same configuration. In the following, the configuration of the four transistors 71 will be described in more detail by focusing on two transistors 71 corresponding to the a-series and b-series data lines 6a in the m-th data line group 6ag.

  In FIG. 5, two transistors 71 each have a semiconductor layer 1a. For example, the semiconductor layer 1a is made of a polysilicon film. A first gate wiring portion 701a configured as the gate electrode 3a of the transistor 71 is disposed on the lowermost layer in FIG. 6 on the semiconductor layer 1a. The first gate wiring portion 701a is formed of, for example, a conductive polysilicon film. Note that the gate wiring 701 shown in FIG. 4 is constituted by the first gate wiring portion 701a and the second gate wiring portion 701b disposed on the upper layer side.

  In FIG. 5 or FIG. 6, the relay layers respectively formed from the first gate wiring 701 a via the insulating layer 12 (see FIG. 6) on the upper layer side, for example, with a conductive material containing aluminum (Al) or other metal film. 40, a selection signal supply line 6 and a source wiring 703 of the transistor 71 are provided. The relay layer 40 is electrically connected to the first gate wiring portion 701 a through a contact hole 86 opened in the insulating layer 12. In addition, the image signal input line 310 of the image signal line 300 and the drain wiring 705 of the transistor 71 in FIGS. 4 and 5 are also arranged in the same layer as the relay layer 40, the selection signal supply line 6, and the source wiring 703. Here, the “same layer” refers to a wiring or the like formed from the same conductive material and patterned at the same time.

  In FIG. 5 or FIG. 6, a conductive material or other metal film containing, for example, aluminum (Al) is provided above the relay layer 40, the selection signal supply line 6 and the source wiring 703 via the insulating layer 15 (see FIG. 6). The second gate wiring portion 701b and the lead-out wiring 320 for the image signal line 300, which are formed respectively by the above, are provided. The second gate wiring portion 701b is an example of the “gate wiring portion” according to the present invention. The second gate wiring portion 701b is electrically connected to each of the corresponding selection signal supply line 6 and relay layer 40 through contact holes 81 and 83 opened in the insulating layer 15, respectively. That is, the first gate wiring portion 701a and the second gate wiring portion 701b are electrically connected to each other through the contact holes 83 and 86 and the relay layer 40.

  Further, in the lead-out wiring 320, the image signal line portion 320a branched toward the transistor 71 (in other words, along the Y direction) is sourced through the contact hole 85 opened in the insulating layer 15 in FIG. It is electrically connected to the wiring 703. The second gate wiring portion 701 b and the lead wiring 320 and the conductive layer (not shown) above the second gate wiring portion 701 b and the lead wiring 320 are interlayer-insulated by the insulating layer 17.

  In the present embodiment, for each transistor 71, the second gate wiring portion 701 b and the image signal line portion 320 a are arranged in the same layer and arranged so as to run close to each other along the same direction (that is, the Y direction). Has been. Note that the configuration is not limited to the configuration illustrated in FIG. 5 or 6, and for example, the second gate wiring portion 701 b and the image signal line portion 320 a may be disposed in different layers.

  For each transistor 71, comparing the second gate wiring portion 701b and the image signal line portion 320a, as shown in FIG. 5, the width d1 of the image signal line portion 320a is wider than the width d2 of the second gate wiring portion 701b. It is formed to become. Therefore, the wiring resistance of the image signal line portion 320a can be further reduced as compared with the case where the image signal line portion 320a is formed with the same width as the second gate wiring portion 701b. Therefore, an electrical adverse effect between the second gate wiring portion 701b that runs close to each other in the same layer can be further reduced in the image signal line portion 320a.

  Therefore, for each of the two transistors 71, noise can be reduced for each series of the selection signals Sel1 and Sel2 in the image signal VID (m) supplied to the image signal line portion 320a, which is remarkable on the display screen. It is possible to reduce the series stripes to the extent that they are not visually recognized.

  In FIGS. 5 and 6, the description has been given focusing on the two transistors 71 among the four transistors 71 corresponding to the data line group 6ag, but preferably the other two transistors as well as the two transistors 71. 71 may also be configured. Therefore, also in the other two transistors 71, the noise can be reduced for each series of the selection signals Sel3 and Sel4 in the image signal VID (m) in the image signal line portion 320a.

  Therefore, according to the liquid crystal device 100 as described above, it is possible to display a high-quality image by the hybrid method.

  For the plurality of transistors 71 in the demultiplexer 7, the second gate wiring portion 701 b and the image signal line portion 320 a are only selected for the transistors 71 corresponding to the series in which the series stripes are significant among the four series of selection signals Sel 1 to Sel 4. May be formed as described above. In this case, the sequence line can be reduced more easily and effectively.

  Next, the case where the liquid crystal device which is the above-described electro-optical device is applied to various electronic devices will be described. FIG. 7 is a plan view showing a configuration example of the projector. Hereinafter, a projector using the liquid crystal device as a light valve will be described.

  As shown in FIG. 7, a projector 1100 includes a lamp unit 1102 made of a white light source such as a halogen lamp. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by four mirrors 1106 and two dichroic mirrors 1108 arranged in the light guide 1104, and serves as a light valve corresponding to each primary color. The light enters the liquid crystal panels 1110R, 1110B, and 1110G.

  The configurations of the liquid crystal panels 1110R, 1110B, and 1110G are the same as those of the liquid crystal device described above, and are driven by R, G, and B primary color signals supplied from the image signal processing circuit. The light modulated by these liquid crystal panels enters the dichroic prism 1112 from three directions. In the dichroic prism 1112, R and B light is refracted at 90 degrees, while G light travels straight. Therefore, as a result of the synthesis of the images of the respective colors, a color image is projected onto the screen or the like via the projection lens 1114.

  In addition to the electronic device described with reference to FIG. 7, a mobile personal computer, a mobile phone, a liquid crystal television, a viewfinder type, a monitor direct view type video tape recorder, a car navigation device, a pager, and an electronic notebook , Calculators, word processors, workstations, videophones, POS terminals, devices with touch panels, and the like. Needless to say, the present invention can be applied to these various electronic devices.

  In addition to the liquid crystal devices described in the above embodiments, the present invention can be applied to a reflective liquid crystal device (LCOS) or the like.

  The present invention is not limited to the above-described embodiments, and can be appropriately changed without departing from the spirit or concept of the invention that can be read from the claims and the entire specification. Electronic devices are also included in the technical scope of the present invention.

It is a top view which shows the whole structure of a liquid crystal device. It is sectional drawing in the HH 'line of FIG. It is a circuit diagram which shows the electrical structure of the liquid crystal device which concerns on this embodiment. FIG. 4 is a circuit diagram showing in more detail the configuration focusing on a transistor corresponding to one data line group in a demultiplexer. It is a top view which shows the structure of two transistors adjacent to each other. It is A-A 'sectional drawing of FIG. It is a top view which shows the structure of the projector which is an example of the electronic device to which a liquid crystal device is applied.

Explanation of symbols

  6 ... selection signal supply line, 6a ... data line, 9a ... pixel electrode, 7 ... demultiplexer, 10 ... element substrate, 10a ... image display area, 11a ... scanning line, 71 ... transistor, 320a ... image signal line portion, 701b ... Second gate wiring part

Claims (3)

On the board
A plurality of pixel electrodes;
A plurality of scanning lines and a plurality of data lines intersecting each other in a pixel region provided with the plurality of pixel electrodes;
One data line group is provided for each of the data lines in the peripheral area located around the pixel area, and each of the data lines includes N transistors (where N is an integer of 2 or more). A plurality of selection switches each for selecting N data lines belonging to the data line group at different timings based on N series selection signals and outputting image signals;
N selection signal supply lines that are formed along a first direction in which the scanning lines extend in the peripheral region and supply the selection signal for each of the N series;
A gate wiring portion that is electrically connected to a corresponding one of the selection switch gate and the N selection signal supply lines and extends along a second direction intersecting the first direction. A plurality of gate wirings each having
Provided for each of the N selection switches corresponding to the data line group, and electrically connected to the source of each of the N selection switches, extending along the second direction, and the gate wiring portion And a plurality of image signal lines each having an image signal line portion formed with a wider wiring width.   The electro-optical device according to claim 1, wherein the image signal line portion is disposed on the same layer as the gate wiring portion.   An electronic apparatus comprising the electro-optical device according to claim 1.

Images