JP2007240670A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce display unevenness generation corresponding to a video signal line to which an H switch is connected. <P>SOLUTION: A display device is equipped with video signal lines 250 which supply display signals to respective pixels and the H switches 240 which supply the display signals from the video signal lines 250 to data line 14 in corresponding columns in a display area. The plurality of video signal lines 250 are arranged side by side in a peripheral area of the display area and the H switches 240 electrically connect connection wiring lines 260 connected to the video signal lines 250 through contact holes according to data output control signals to the corresponding data lines 14 between the video signal lines 250 and display area. A contact hole h25 between a video signal line near the display area and a corresponding connection wiring line is formed in the display area on a far-end side about the line width center of the video signal line and a contact hole between a video signal line distant from the display area and a connection wiring line is formed in the display area on a near-end side of the video signal line to reduce a difference in writing delay quantity due to a wiring resistance difference. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a configuration around a video signal line of a display device using, for example, an organic electroluminescence (hereinafter, EL) element as a display element of each pixel.

  FIG. 12 shows a so-called active in which a plurality of pixels are arranged in a matrix in the display area, and each pixel is provided with a switch element (here, a thin film transistor: TFT) for individually controlling the display element of the pixel. 1 shows a schematic panel configuration of a matrix type display device. In FIG. 12, only four pixels are shown, and the display element of each pixel is a liquid crystal element.

  A gate line (selection line) GL is formed in the horizontal scanning direction of the display area, and a data line DL is formed in the vertical scanning direction. In addition, one of the first capacitor electrode and the second capacitor electrode constituting the storage capacitor Cs of each pixel is connected to a common capacitor line SL, and the capacitor line SL is selected in the example of FIG. It is formed in the horizontal scanning direction so as to be parallel to the line GL.

  In such an active matrix liquid crystal display panel, a drive circuit for controlling and driving the pixel circuit can be incorporated in the periphery of the display region 500 through the same process as the TFT of the pixel circuit or through the same process. In FIG. 12, a vertical scanning direction driving circuit (V system driver) 510 is provided along the vertical scanning direction around the display area 500, and a horizontal scanning direction driving circuit (H system driver) 620 is provided along the horizontal scanning direction. It has been. The V-system driver 510 sequentially outputs a selection signal to the gate lines GL in each row. The H system driver 620 includes an H system shift register 630, a switch circuit (H switch or sample hold circuit) 640, and a plurality of video signal lines (VL) provided between the H system shift register 630 and the switch circuit 640. ) 650.

  For example, display signals of colors (R, G, B) supplied from the outside of the panel are supplied to the respective video signal lines 650 for each color, and the video signal lines 650 are connected via corresponding H switches 640. It is connected to the data line DL of each column.

  The H switch 640 is composed of a pixel TFT, a TFT similar to the TFT constituting the V system and the H system drivers 510 and 620, and its gate electrode is connected to the output of the corresponding register stage of the H system shift register 630. Yes. One of the source and drain of the H switch 640 is connected to the corresponding video signal line 650 by a connection wiring 660. The other of the source and drain is connected to the corresponding data line DL.

  When the data output control signal is supplied from the H system shift register 630 to the gate electrode of the H switch 640, the H switch 640 is turned on. Therefore, the data line DL is electrically connected to the video signal line 650 via the connection wiring 660 connected to the corresponding video signal line 650 via a contact hole described later and the H switch 640 that is turned on. A display signal of the video signal line 650 is supplied to the data line DL.

  Since the video signal line 650 needs to supply a display signal to each data line DL in the display area 500 with as little signal delay as possible, a metal material such as low resistance Al is used as the wiring material. In this case, since the connection wiring 660 and the video signal line 650 not corresponding to the connection wiring 660 need to intersect with each other while maintaining insulation, the connection wiring 660 is formed of the same layer as the video signal line 650 as a material of the connection wiring 660. Metal wiring made of the same material is not used, and other conductive materials are used. Specifically, as the wiring material of the connection wiring 660, a conductive material different from the wiring material of the video signal line 650 can be used. However, a separate layer can be formed without adding a new layer formation process. In this case, the same metal layer as that of the gate line GL or a polycrystalline silicon layer used for the active layer of the TFT is used.

  However, the same metal layer and polycrystalline silicon layer as those of the gate lines GL have a larger resistance value than the video signal line 650. Further, a connection wiring 660 for connecting the video signal line 650 at a position close to the display area 500 and the corresponding H switch 640 and a connection for connecting the video signal line 650 at a position far from the display area 500 and the corresponding H switch 640. There is a large difference in wiring length between the wiring 660 and the wiring 660. Since the wiring length difference is large and the wiring resistance value of the wiring itself is large as described above, data writing due to the wiring resistance difference of the connection wiring causes variation display unevenness.

  In addition, as a document relevant to this invention, the following patent document 1 is mentioned.

Japanese Patent Laid-Open No. 1-289917

  In Patent Document 1, it is proposed to change the wiring length l of the connection wiring 660 in order to reduce the difference in wiring resistance of the connection wiring 660, but a specific wiring method is not disclosed.

  FIG. 13 shows a wiring structure conventionally used to equalize the wiring lengths of the connection wirings 660 connected to different video signal lines 650. As shown in FIG. 13, the connection wiring 660f connected to the video signal line 650f that is farthest from the display area 500, that is, far from the H switch 640 is wired in a straight line, but is higher than the video signal line 650f. The connection wirings 660m and 660n connected to the remaining video signal lines 650 formed at positions close to the switch 640 are designed to have the actual wiring length equal to the wiring length of the connection wiring 660f by meandering the wiring. Has been. By adopting such a layout, the difference in wiring resistance can be reduced.

  However, there is a strong demand for product development to be performed quickly and accurately on various models. However, when a wiring pattern as shown in FIG. 13 is adopted, the pattern must be designed for each connection wiring, and the resistance value between the two is minimized, considering the actual resistance value, and more than necessary. In addition, it takes time to design without reducing the wiring density.

  Further, as shown in FIG. 14, regardless of the separation distance between the H switch 640 and the corresponding video signal line 650, all the connection wirings 662 have the same pattern as the connection wiring with the longest wiring distance. A method of matching the overlapping area with the connection wiring 662, that is, the parasitic capacitance connected to each connection wiring 662, in each connection wiring is also conceivable. This method is easy to design because only the video signal line 650 connected to the connection wiring 662 is different. However, since the connection wiring 662 has an overlapping region with the video signal line 650 that does not need to be connected, it is necessary to consider the risk of a short circuit in the overlapping region. Further, a parasitic capacitance due to superposition with the connection wiring 662 is connected to each video signal line 650. Therefore, the waveform of the video signal output to the video signal line 650 is rounded, and the accuracy of the video signal supplied to each data line is lowered, resulting in display variations.

  Therefore, the present invention realizes a wiring layout that is easy to design and can reduce variations in wiring resistance.

  The present invention provides a display area having pixels arranged in a matrix, a video signal line for supplying a display signal to the plurality of pixels in the display area, and a column corresponding to the display area from the video signal line. A switch circuit for selectively supplying the display signal to a data line connected to the pixel of the display, wherein the video signal line is displayed in the peripheral area of the display area. A plurality of switch circuits are formed outside the region along the side of the display region, and the switch circuit is provided for each data line between the video signal line and the display region. In response to a data output control signal, a connection wiring connected to the corresponding video signal line through a contact hole is electrically connected to the corresponding data line and is closest to the display area. A video signal line, at the farthest video signal lines, forming positions of each signal line line width of the contact hole for connecting the connection wires to the video signal lines are different.

  In another aspect of the present invention, in the display device as described above, the contact hole between the video signal line closest to the display area and the corresponding connection wiring is at the center in the line width direction of the video signal line. The contact hole between the video signal line farthest from the display area and the corresponding connection wiring is formed on the far end side of the display area than the center in the line width direction of the video signal line. It is formed on the near end side of the display area.

  In another aspect of the present invention, in the display device, the video signal line is provided with an odd number of at least three or more, and a connection wiring corresponding to the video signal line disposed in a central portion of the video signal line is provided. The contact hole is formed in the central region in the line width direction of the video signal line.

  In another aspect of the present invention, in the display device, four or more video signal lines are provided, and two or more video signal lines formed in a central portion of the video signal lines and corresponding connection wirings are provided. The contact hole is formed in the central region in the line width direction of each video signal line.

  In another aspect of the present invention, in the above display device, 2n video signal lines are provided (where n is a natural number of 1 or more), and n video signal lines on the near side of the display area are compatible. Contact holes are formed on the far end side of the display area in the line width direction of each video signal line, and in the n video signal lines on the far end side of the display area, the corresponding connection lines and Are formed on the near end side of the display area in the line width direction of each video signal line.

  In another aspect of the present invention, a display region including pixels arranged in a matrix, a video signal line for supplying a display signal to the plurality of pixels in the display region, and the display region from the video signal line A switch circuit for selectively supplying the display signal to the data lines connected to the pixels in the corresponding column of the display device, wherein the video signal line is a peripheral region of the display region A plurality of lines are formed outside the display area along the side of the display area, and the switch circuit is provided for each data line between the video signal line and the display area. In response to the data output control signal, the switch circuit electrically connects a connection wiring connected to the corresponding video signal line through a contact hole to the corresponding data line, and A plurality of signal lines are provided for each color to form a video signal group for each color, and in the group closest to the display area among the plurality of video signal line groups, the contact hole includes each video signal. In the group farthest from the display area, the contact hole is formed nearer to the display area than the center in the line width direction of each video signal line. Formed on the side.

  In another aspect of the present invention, in any one of the above display devices, the connection wiring extends from a corresponding switch circuit toward a video signal line to be connected, and is far from the display area of the video signal line. It terminates before the adjacent video signal line forming region arranged on the end side.

  In another aspect of the present invention, in any one of the above display devices, when the diameter of the contact hole is indicated by L and the line width of the video signal line is indicated by w, 2L ≦ w is satisfied.

  In another aspect of the present invention, in any one of the above display devices, the contact hole is formed such that the position of the video signal line in the line width direction is 0 for the near end of the display area and 0 for the far end. If the diameter of the contact hole is represented by a natural number L smaller than w, the center of the contact hole formed on the near end side of the display area of each video signal line is represented by L / 2 to (w / 2-L / 2), and the center of the contact hole formed on the far end side of the display area of each video signal line is (w / 2 + L / 2) to (w−L / 2) Between.

  As described above, according to the present invention, when the connection wiring for supplying the video signal from the video signal line corresponding to the switch circuit connects the video signal lines having different distances from the switch circuit formation region, respectively. However, each wiring resistance can be made as close as possible. In addition, by adjusting the contact hole formation position, it is possible to reduce the difference in wiring length between adjacent connection wirings while minimizing the possibility of parasitic capacitance and short-circuiting. Variations in the signal supplied to can be reduced. Furthermore, a special design such as meandering in the middle of the wiring is unnecessary, and the wiring pattern can be designed accurately and quickly.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  In this embodiment, the display device is a so-called active matrix display device in which each pixel in the display region includes a switch element such as a transistor that controls the display element for each pixel. Further, a drive circuit for controlling each pixel is built in the periphery of the display area. Hereinafter, an active matrix EL display device using a current-driven electroluminescence (EL) element as a display element (driven element) of each pixel will be described as an example.

(Outline configuration of display device)
FIG. 1 is a diagram showing an equivalent circuit configuration of an active matrix EL display device according to this embodiment. FIG. 2 shows a wiring structure around the output section of the H driver (horizontal drive circuit) of FIG.

  In the display area 100 on the panel substrate 110 such as glass, a plurality of pixels are arranged in a matrix. Further, gate lines (selection lines) 10 (GL) to which selection signals are sequentially output are formed in the horizontal scanning (row) direction of the matrix of the display region 100, and data is displayed in the vertical scanning (column) direction. A data line 14 (DL) for outputting a signal and a power supply line 16 (PL) for supplying an operating power supply (PVDD) to an organic EL element as a display element are provided. Each pixel is generally configured in a region defined by these lines.

  As an example, the circuit configuration of each pixel includes an organic EL element EL as a display element, a pixel transistor, and a storage capacitor Cs that holds data (voltage) corresponding to contents to be displayed by the organic EL element for a predetermined period. The pixel transistor includes, for example, a selection transistor Tr1 composed of an n-channel TFT and an element drive transistor Tr2 composed of a p-channel TFT.

  The selection transistor Tr1 has a drain connected to the data line 14 for supplying a data voltage to the pixels arranged in the vertical scanning direction, and a gate electrode connected to the gate line 10 for selecting the pixels arranged on one horizontal scanning line. The source is connected to the gate electrode of the element driving transistor Tr2.

  The element drive transistor Tr2 has a source connected to the power supply line 16 and a drain connected to the anode (anode) of the organic EL element EL. The cathode (cathode) of the organic EL element EL is formed in common for each pixel and is connected to a cathode power source CV (not shown).

  The first electrode of the storage capacitor Cs is connected to the gate electrode of the element driving transistor Tr2 and the source of the selection transistor Tr1, and the second electrode of the storage capacitor Cs is connected to the capacitor line 12 (SL). The capacitor line 12 extends in the row direction in parallel with the selection line 10. The capacitor line 12 can hold necessary data by applying a predetermined constant voltage. However, in order to improve the afterimage in each pixel, a capacitor signal whose voltage fluctuates periodically is supplied. It is also possible.

  Each of the selection transistor Tr1 and the element driving transistor Tr2 uses a semiconductor material for the active layer, and uses crystalline silicon such as polycrystalline silicon that is polycrystallized by laser annealing or the like, and uses the gate electrode as a mask. It is possible to dope impurities in a self-aligned manner to form channel, source and drain regions of the transistor. As an impurity, an n-channel thin film transistor (TFT) doped with n-conductivity type and a p-channel TFT doped with p-conductivity type can be employed. It is also possible to employ amorphous silicon as the active layer of the pixel transistor. When the TFT using the crystalline silicon as the active layer as described above is adopted as the transistor of the pixel circuit, the crystalline silicon TFT is not only a pixel circuit but also a peripheral for sequentially selecting and controlling each pixel. It can also be used as a circuit element of a driver circuit.

  In the present embodiment, as described above, on the panel substrate 110 on which the display region 100 is formed, simultaneously with the manufacture of the pixel circuit transistor, a crystalline silicon TFT similar to the pixel circuit is formed outside the display region 100. The peripheral drive circuit 200 is incorporated. However, even if a crystalline silicon TFT is adopted as the circuit element of the peripheral drive circuit, the configuration is not necessarily limited to adopting crystalline silicon as the pixel transistor, and further, a crystal is formed in the active layer of the circuit element of the peripheral drive circuit. Semiconductor materials other than conductive silicon can also be used. In addition, some of the circuit elements of the peripheral drive circuit, for example, an H switch 240 described later is built in the board, or the V system driver 210 is also built on the board, and other H system drivers 220 are provided. The circuit may be configured to be executed by an external circuit.

  The peripheral driving circuit 200 includes a V-system driver (vertical driving circuit) 210 provided along the vertical scanning direction around the display area 100 and an H-system driver (horizontal driving circuit) provided along the horizontal scanning direction. 220). The V-system driver 210 generates a selection signal for turning on the first TFT r10 of the pixel corresponding to the data line 14 for each horizontal scanning (1H) period for the plurality of selection lines 10 extending in the row direction of the matrix. And output sequentially. The H system driver 220 outputs corresponding data signals to the plurality of data lines 14 extending in the column direction of the matrix.

  As shown in FIG. 2, the H system driver 220 includes an H system shift register 230 and an H switch (H system switch circuit) 240. The H-system shift register 230 includes shift registers (SR) having the number of stages corresponding to the number of columns of pixels, and transfers the horizontal start signal STH to the next-stage register according to the horizontal clock (pixel clock) CKH. Sequentially outputs data output control signals.

  The H switch 240 is provided corresponding to each data line 14, and the H switch 240 is provided between the shift register 230 and the display area 100 in the end portion (in the vertical scanning direction of the display area 100 ( In the example of FIG. 2, it is provided at a position equidistant from the upper side).

  Between the H switch 240 and the H system shift register 230, a plurality of video signal lines 250 are provided outside the display region 100 along the side of this region, specifically along the horizontal scanning direction. ing. Each video signal line 250 is supplied with a video signal from the outside. For example, the video signal line 250 is provided for each color. In the example of FIG. 2, R (red), G (green), B ( Blue) Each video signal line 250r, 250g, 250b for display is provided.

  Further, the H switch 240 can be formed using a thin film transistor formed over the substrate at the same time as the pixel portion transistor, a driving portion transistor constituting a shift register, or the like. The gate electrode of the thin film transistor constituting such an H switch 240 is connected to the output portion of each register of the H system shift register 230. One of the source and drain is connected to one of the R, G, and B video signal lines 250 via the connection wiring 260, and the other is connected to the corresponding data line 14. When a data output control signal is output from the corresponding register stage of the H system shift register 230, it is supplied to the gate electrode 118h of the H switch 240, the H switch 240 is turned on, and the source and drain are conducted. Accordingly, at this time, the data line 14 corresponding to the video signal line 250 to which one of the source and drain is connected is connected, and the data line 14 is changed according to the video signal voltage applied to the video signal line 250. The battery is charged and a data signal corresponding to the video signal is written to the data line 14.

  A contact portion (a contact hole h22 to be described later) that connects the other source / drain of each H switch 240 and the corresponding data line 14 is provided at a position equidistant from the end portion of the display region 100. The wiring resistance from the section to each data line 14 is equal to each other.

  On the other hand, in order to connect one of the source and drain of the corresponding H switch 240 and the video signal line 250, the connection wiring 260 has a plurality of video signal lines 250 extending in the horizontal scanning direction as described above. Has been. Therefore, when wiring is performed for each video signal line 250 at the shortest distance, the wiring length varies depending on the video signal line 250 to be connected, and a difference in wiring resistance occurs for each video signal line 250.

  In the present embodiment, the contact (contact) between the connection wiring 260 and the corresponding video signal line 250 so that the difference in wiring resistance from the video signal line 250 to the data line 14 does not increase for each video signal line 250. The position of the hole h25) is adjusted.

  Specifically, the video signal line 250n closest to the display area 100 (250b in the example of FIG. 2), the farthest video signal 250f (250r in the example of FIG. 2), and the corresponding connection wiring 260 are contacted. The holes h25 are provided at positions close to the central video signal line 250c (250g in the example of FIG. 2). The contact hole h25 for the central video signal line 250c is disposed at the center in the line width direction.

  Thereby, the wiring length of the connection wiring 260 with respect to the video signal line 250 on the far end side and the proximity side from the display area can be made closer to the wiring length of the connection wiring 260 with respect to the central video signal line 250. Thus, the difference in wiring resistance of the connection wiring 260 connected to the three video signal lines 250 can be reduced, and a large difference in display luminance can be prevented from occurring for each connected video signal line by a simple method. .

  FIG. 3 shows an example of a cross-sectional structure of the H switch 240 along the line AA in FIG. FIG. 4 shows an example of a schematic cross-sectional structure of the pixel selection transistor and element driving transistor corresponding to the data line to which the H switch 240 is connected.

In the example of FIGS. 3 and 4, a buffer layer 112 in which SiN and SiO ₂ are laminated in this order is formed on an insulating substrate 110 such as glass. An amorphous film formed on the buffer layer 112 is formed. Then, a polycrystalline silicon layer is formed by stacking crystalline silicon and crystallized by laser annealing or the like, and patterned into a necessary shape for the active layer 114 of each thin film transistor. A gate insulating film 116 is formed on the entire surface of the substrate so as to cover the polycrystalline silicon layer 114. As an example, the gate insulating film 116 has a laminated structure in which SiO ₂ and SiN are sequentially formed from the polycrystalline silicon layer 114 side.

  In a predetermined region on the gate insulating film 116, a refractory metal material layer such as Cr or Mo is patterned to control the potential of the gate electrode 118, the gate line 10, and one electrode of the storage capacitor of each pixel. The capacitor line 12 and the connection wiring 260 are formed.

  The gate electrode 118 is the gate electrodes 118s and 118d in the selection transistor Tr1 and the element driving transistor Tr2 in the pixel portion shown in FIG. Here, the gate line 10 is formed integrally with the gate electrode 118s of the selection transistor Tr1.

  On the other hand, in the H-system driver region, as shown in FIG. 3, the refractory metal material layer is patterned, and the video signal line 250 formed later in the upper layer, the drain (or source) of the H switch 240, And a gate electrode 118h connected to the output terminal of the corresponding register of the shift register of the H system driver.

  After forming the gate electrode 118 of each transistor, the polycrystalline silicon layer 114 in the formation region of each transistor is doped with an n-type or p-type impurity depending on the conductivity type of the transistor using the gate electrode 118 as a mask. For this reason, the region covered with the gate electrode 118 of the polycrystalline silicon layer 114 becomes an intrinsic channel region ch without being doped with impurities, and a source region s and a drain region d doped with impurities are respectively provided on both sides of the channel region ch. It is formed.

After the impurity doping, an interlayer insulating layer 120 in which SiN and SiO ₂ are stacked in this order is formed as an example on the entire surface of the substrate covering the gate electrode 118, the gate line 10, and the capacitor line 12.

  Next, in the pixel portion, contact holes that penetrate the interlayer insulating layer 120 and the gate insulating film 116 are formed at positions corresponding to the source region s and the drain region d of the transistor. Further, a metal wiring material layer having high conductivity such as Al is formed so as to fill the contact hole, and is patterned into a desired wiring shape. In the pixel portion shown in FIG. 4, this metal wiring material layer is a data line 14 connected to the drain (or source) of the selection transistor Tr1 through the contact hole h26 to supply a data signal. It is used as a wiring (not shown) for connecting the source (or drain) of the transistor Tr1 and the gate electrode 118d of the element driving transistor Tr2. The power source line 16 is connected to the source (or drain) of the element driving thin film transistor Tr2 and supplies a current from the power source (PVDD).

  On the other hand, in the H-based driver region, a contact hole h25 is formed through the interlayer insulating layer 120, and the contact region of the connection wiring 260 using the same refractory metal material as the gate electrode material is exposed. Therefore, the video signal line 250 is wired using the metal wiring material layer so as to fill the contact hole h25, so that the video signal line 250 is connected to the corresponding connection wiring 260 and the contact hole formed earlier. Connected via h25.

  In this embodiment, the drain region and the source region of the H switch 240 are both connected to the video signal line 250 via contact holes h21 and h22 formed through the interlayer insulating layer 120 and the gate insulating film 116. And a drain electrode and a source electrode formed by the same metal material layer as the data line 14 and the like. The drain electrode 130d (or the source electrode 130s) is connected to the connection wiring 260 through a contact hole h23 formed through the interlayer insulating layer 120, and the source electrode 130s (or the drain electrode 130d) is connected to the data. Connected to line 14.

  In principle, the source electrode 130s of the H switch 240 only needs to be electrically connected to the data line 14, and therefore the data line 14 can also serve as the source electrode 130s of the H switch 240. However, in this embodiment, as shown in FIG. 3, the source electrode 130s of the H switch 240 and the data line 14 both formed by patterning the same material are the same as the gate electrode or the like in the periphery of the pixel portion. They are connected via a data intermediate wiring 140 using a refractory metal material layer. In this manner, by providing an area that is connected to the data line 14 using a different layer between the data line 14 in the display area and the output wiring from the driver unit, the driver is connected until they are connected. And the display area connected to the data line can be electrically separated. Therefore, it is possible to prevent static electricity from entering the display region via the data line 14 during the manufacture of the above-described transistors and wirings on the substrate, and causing the selection transistor, the element driving transistor, and the like to be electrostatically damaged. For the same purpose, in the present embodiment, the gate line to which the gate signal is sequentially supplied from the V-system driver is also used by using a metal wiring different from the gate line as the gate intermediate wiring in the periphery of the display area. A configuration for connecting to a V-system driver is adopted. Specifically, a wiring layer obtained by simultaneously patterning a metal wiring layer used for the data line 14 or the like can be adopted as the other gate intermediate wiring. By adopting such a gate intermediate wiring configuration, it is possible to prevent static electricity from entering from the outside through the gate line until the gate line is connected to the V-system driver unit by this wiring.

  Note that after the connection wiring 250 of the H switch 240, the data line 14, the power supply line 16, and the like are formed, the first planarization insulating layer 120 made of an organic resin or the like is formed so as to cover them. In the first planarization insulating layer 120, a contact hole is formed in a portion corresponding to the drain electrode of the element driving transistor Tr2, and a first electrode 124 having an individual pattern is stacked for each pixel so as to fill the contact hole. Patterning. When the EL display device is a so-called bottom emission type in which the EL display device emits light from the EL element from the substrate 110 side, a transparent conductive metal oxide such as ITO (Indium Tin Oxide) can be used. it can. After the patterning of the first electrode 124, a second planarization insulating layer 126 made of an organic resin or the like is further formed so as to cover the edge portion of the first electrode 124 and the inter-pixel region. As shown in FIG. 4, the second planarization insulating layer 126 has an opening in the inner region of the first electrode 124 formation region, and this opening region substantially serves as a light emitting region of the EL element of each pixel. Stipulate.

  After the formation of the second planarization insulating layer 126, the light emitting element layer 300 is stacked by, for example, a vacuum evaporation method. The light emitting element layer 300 includes at least a light emitting layer 316 and adopts a single layer or a multilayer structure depending on the function of a light emitting material or the like. In the example of FIG. 4, the light emitting element layer 300 includes a hole injection layer 312, a hole transport layer 314, a light emitting layer 316, and an electron transport layer 318 from the first electrode 124 side. On this light emitting element layer 300, in this example, a second electrode 320 common to each pixel is formed. For example, the second electrode 320 includes a stacked structure of a very thin electron injection layer 322 made of LiF or the like and a thick metal layer 324 using Al or the like on the light emitting element layer 300 side. A protective film 340 is further formed on the entire surface of the substrate covering the second electrode 320 to protect the EL element from moisture and oxygen. In the example of FIG. 4, the light emitting layer 316 has a white light emitting function, and this white light is emitted to the outside as light of a desired color necessary for full color display such as R, G, and B by the color filter CF. Yes. The color filter CF can be provided on the emission side surface of the substrate 110, or can be formed between the substrate 110 and the first electrode 124 (in FIG. 4, between the interlayer insulating film 120 and the first planarization insulating layer 122). Can do. When the light emitting layer 316 directly emits light of a desired color for each pixel, at least the material used for the light emitting layer 316 is different. Therefore, the light emitting layer 316 uses a mask or the like at the time of film formation so as to have an individual pattern for each pixel To obtain a desired pattern. In the case of the individual light emission, the color filter CF can be omitted. In this manner, an organic EL element including the light emitting element layer 300 between the first electrode 124 and the second electrode 320 is formed on the upper layer of the previously formed transistor. One of the first electrode 124 and the second electrode 320 serves as an anode and the other serves as a cathode. For example, the lower first electrode 124 functions as an anode and the upper second electrode 320 functions as a common cathode. Then, electrons and holes are supplied to the light emitting layer 316 in a region where the first electrode 124 and the second electrode 320 face each other directly with the light emitting element layer 300 interposed therebetween, and light can be obtained.

(Description of contact position)
As described above, in this embodiment, by adjusting the contact position between the connection wiring 260 that connects the H switch 240 and the video signal line 250 and the corresponding video signal line 250, the H switch is switched from the video signal line 250. The wiring resistance values up to 240 are close. Note that the wiring distances from the H switch 240 to the display area of the corresponding data line are set to be equal in order to suppress variations in wiring resistance for each data line. Therefore, in this embodiment, only the wiring length of the connection wiring 260 differs depending on the position of the corresponding video signal line 250. Hereinafter, a specific method for adjusting the contact position and its effect will be described.

  The adjustment of the contact position between the video signal line and the connection wiring is not limited to the case where the number of the video signal lines 250 is three as described above, but two or more plural lines are arranged in parallel in the peripheral portion of the display area. It is applicable when Here, the line width of each video signal line is represented by w, and the diameter of the contact hole (diameter in the line width direction of the video signal line) for connecting the video signal line and the corresponding connection wiring is represented by L. In this embodiment, 2L ≦ w is satisfied. In other words, the diameter of the contact hole is set so as to satisfy the relationship that is smaller than half the line width w of the video signal line. Therefore, the contact hole position, that is, the contact position between the connection wiring 260 and the corresponding video signal line 250 can be easily adjusted according to the position of the video signal line 250 from the display area. As an example, the contact hole has a quadrangular shape as shown in FIG. 2, and the length (L) of one side can be about 10 μm. In this case, the width of the video signal line is set to 20 μm or more. Has been.

  The shape of the contact hole h25 is not particularly limited as long as its diameter is half or less than the wiring width as described above and the upper and lower layers can be electrically connected. However, a quadrangular shape can be adopted as shown in FIG. It is. Of course, it may be a circle having a diameter L.

  Further, when the near end of the display area in the line width direction of the video signal line is indicated by 0, the far end is indicated by w equal to the line width, and the diameter of the contact hole is indicated by a natural number L smaller than w as described above, The center of the contact hole formed on the near end side of the line display area is provided between L / 2 and (w / 2−L / 2). The center of the contact hole formed on the far end side of the display area of each video signal line is provided between (w / 2 + L / 2) to (w−L / 2). The center position of the contact hole depends on the difference between the maximum length and the shortest length of the distance from the H switch 240 to the connected video signal line 250 determined by the number of video signal lines 250 and the line width. It is preferable to determine which position from 2 to (w / 2−L / 2) and (w / 2 + L / 2) to (w−L / 2).

In the case of two video signal lines A case where two video signal lines 250 are arranged in parallel will be described. As shown in FIG. 5, when there are two video signal lines 250, the contact position between the video signal line 250n on the display area neighboring side and the connection wiring 260n, the video signal line 250f on the far end side of the display area and the connection wiring 260f. Is set at the middle of the two video signal lines 250. Specifically, for the near-side video signal line 250n, the display region is farther from the center in the line width direction, and as described above, (w / 2 + L / 2) to (w−L / A contact hole for connecting to the connection wiring 260n is formed so that the space between 2) is the center. Then, the connection wiring 260n that extends to at least the position of the contact hole and is exposed at the bottom of the contact hole is electrically connected to the near-end video signal line 250n.

  Conversely, the far-end video signal line 250f is centered between L / 2 and (w / 2−L / 2) on the display region closer side than the center in the line width direction. A contact hole for connecting to the connection wiring 260f is formed. As a result, the connection wiring 260f that extends to at least the contact hole position and is exposed at the bottom of the contact hole is electrically connected to the far-end video signal line 250f.

  Here, the contact position between the near-side video signal line 250n and the connection wiring 260n is (w−L / 2), and the contact position between the far-end video signal line 250f and the connection wiring 260f is the L / 2 position. Then, the difference in wiring resistance between the two connection wirings 260n and 260f can be minimized.

In the case of three video signal lines When three video signal lines 250 are arranged in parallel, as already described with reference to FIG. 2, only the central video signal line 250 is centered in the line width direction. Are connected to the corresponding connection wiring 260c, and the remaining two video signal lines 250 and the corresponding connection wiring are electrically connected in contact holes formed at positions close to the central video signal line 250, respectively. .

When there are four or more video signal lines and an even number, when four or more video signal lines are arranged in parallel, they are arranged as follows. In the case of 2n (n is a natural number of 1 or more), that is, when 4 or more even video signal lines are arranged, the contact position between the n video signal lines close to the display area and the corresponding connection wiring Is formed on the far end side of the display area in the line width direction of each video signal line. Conversely, the contact positions of the n video signal lines far from the display area and the corresponding connection wiring are formed on the near end side of the display area in the line width direction of the far-end video signal line. As described above, specific contact hole formation positions are (w / 2 + L / 2) to (w−L /) at the far end side of the display area in the line width direction of each video signal line in the adjacent video signal line group as described above. 2) and between L / 2 and (w / 2−L / 2) on the side close to the display area in the line width direction with respect to the far-end video signal line group. From a design point of view, contact holes h25 are formed at the same position in each signal line width direction for all the near-side video signal line groups, and each signal line line width direction for all of the far-end video signal line groups. Thus, it is easy to form the contact hole h25 at the same position. However, according to the distance of the video signal line from the display area, the center position of the contact hole is sequentially changed between (w / 2 + L / 2) and (w−L / 2) in the near video signal line group. However, in the far-end video signal line group, it may be sequentially changed between L / 2 and (w / 2−L / 2).

  FIG. 6 shows a schematic plan configuration around the H switch when four video signal lines are arranged in parallel. The four video signal lines are employed when, for example, a video signal line 250w for white (W) display is provided in addition to the three video signal lines for R, G, and B as described above. The In the display area 100, in addition to the R, G, B display pixels, white (W) display pixels are provided, and the video signal line 250w for supplying a data signal to the corresponding white display pixels includes the R, G , B video signal lines 250r, 250g, 250b. Note that the W display pixel emits light when displaying a large amount of white components such as a display luminance, particularly a natural image, so that in the case of W display, R, G, B display that normally requires light emission at the maximum luminance. The display luminance can be improved while reducing the load on the pixel. The contact positions of the video signal lines 250r, g, b, and w and the corresponding connection wirings 260 correspond to the display area rather than the center in the line width direction according to the wiring positions of the video signal lines 250r, g, b, and w. It is determined whether it is near end or far end. That is, the contact position between any video signal and the connection wiring is formed close to the center position side of the second and third video signal lines of the four lines.

  Here, as the video signal line closest to the H switch 240, that is, the display area, a signal line to which a video signal having the largest amplitude is supplied is adopted when the amplitude of the video signal Vsig supplied to each video signal line is different. It is preferable to do. In the case where a signal of a corresponding color is supplied to each video signal line, for example, when the B emission luminance is the lowest among R, G, and B due to the characteristics of the organic EL element, an accurate white is displayed. In order to achieve this, it is necessary to increase the luminance of the B display pixels by increasing the B video signal Vsig to the maximum. In this case, it is preferable to arrange the B video signal line 250b in the position closest to the display area among the video signals arranged in parallel.

  As described above, even if the contact position with the connection wiring 260 is adjusted according to the distance from the display area of the video signal line, the wiring resistance to the data line 14 is completely the same for each video signal line. Don't be. Therefore, if the video signal line 250 having the largest amplitude of the applied video signal is arranged closest to the display area in consideration of this slight wiring resistance difference, the video signal is passed through the H switch 240. A difference in writing time when writing to the corresponding data line 14 can be reduced, and a video signal having a large amplitude can be reliably supplied to the data line 14. Further, by disposing the video signal line 250 having the smallest amplitude of the applied video signal Vsig at a position farthest from the display area, it is possible to reduce the difference in writing time corresponding to the difference in the amplitude of the video signal Vsig. It is possible to write display data with no variation in the data line in a shorter time.

  In the example of FIG. 6, the B video signal Vsigb has the largest amplitude and the W video signal Vsigw has the smallest amplitude. Therefore, the B video signal line 250b is wired closest to the display area. The W video signal line 250w is wired at the farthest position. As for the G video signal line 250g and the R video signal line 250r, the G video signal line 250g is arranged on the display region side in the example of FIG. In addition, the present invention is not limited to the case of four colors. For example, even when video signal lines of R, G, and B colors as shown in FIG. 2 are provided, this signal is similar to the above according to the amplitude of the applied signal. It is preferable to determine a video signal line to which is applied. In this manner, by determining the video signal line to be applied depending on the position of the video signal line, white balance and the like can be adjusted, which can contribute to improvement in display quality.

When the number of video signals is four or more and odd number When four or more odd number of video signal lines are arranged in parallel, only the contact position between the video signal line 250c at the middle position and the corresponding connection wiring 260c is provided. The video signal line 250c is set at the center in the line width direction. The contact positions of the far-end video signal lines in the other display areas and the connection wires corresponding to the far-end video signal lines are provided at positions close to the central video signal line 250c as described above.

Other example 1 in case of 4 or more video signal lines
In the case where four or more video signal lines are arranged in parallel, as shown in FIG. 7, only a video signal line 250n closest to the display area and only a connection wiring 260 corresponding to the farthest video signal line are used. A contact hole may be formed at a position near the video signal line on the center side of the signal line 250. In this case, the contact position between the remaining video signal line 250c and the corresponding connection wiring 260 is the center in the line width direction of each signal line.

Other example 2 in case of 4 or more video signal lines
When a video signal line 250 is provided for each display color of R, G, B, etc., and two or more video signal lines are provided for each color, a contact position adjusting method as shown in FIG. Can be adopted.

In the example of FIG. 8, four video signal lines 250 _r1 to _r4 , 250 _g1 to _g4 , and 250 _b1 to _b4 are provided for R, G, and B, respectively. Among them, the B video signal lines 250 _b1 to _b4 are arranged closest to the display area, and the R video signal lines 250 _r1 to _r4 are arranged farthest from the display area. Note that the arrangement order of the video signal line groups for each color is preferably determined according to the magnitude of the amplitude of the applied video signal as described above.

  The contact position (h25n) between the video signal line group 256n closest to the display area and the connection wiring 260n corresponding thereto is the far end side of the display area of each signal line (in this example, the center is It is provided at a position in the vicinity of w- (L / 2) of the wiring. Conversely, the contact position (h25f) between the video signal line group 256f farthest from the display area and the connection wiring 260f corresponding to each of the video signal line group 256f is the near end of the display area of each signal line (in this example, The center is provided at a position in the vicinity of L / 2 of each wiring. The contact position (h25c) between the central video signal line group 256c and the corresponding connection wiring 260c is provided at the center in the line width direction of each signal line. Even when a plurality of video signal lines are provided for each color video signal, it is easy to design and maintain a difference in wiring resistance by adjusting the contact position with the connection wiring with such regularity. The difference in the data writing time (delay time) due to can be minimized.

  Next, in the case of the panel of this embodiment in which the contact position is adjusted as shown in FIG. 8 and the comparative example panel in which the contact position is not adjusted as shown in FIG. A comparison result of the write delay time will be described.

  In the panel of the comparative example, as shown in FIG. 9, the contact position between any video signal line and the connection wiring is set at the center of each signal line. Other conditions are the same as in the case of the panel according to the present embodiment. The video signals of R, G, and B are four phases, and the video signal lines for B, G, and R are respectively connected from the display area side. Four of them are arranged in parallel with the same line width, and the size of the contact portion with the corresponding video signal line of the connection wiring is 10 μm square (the length of the contact hole in the line width direction of the video signal line).

  The comparison result is as shown in FIG. 10, and when the wiring width w of the video signal line is 1.0 (arbitrary unit au), the panel according to the present embodiment in which the contact position is adjusted and the panel in the comparative example that is not adjusted Thus, there is almost no difference in the delay time for writing the video signal to the data line.

  However, when the line width w of each video signal line 250 is increased five times, in the panel of this embodiment, the video signal line for R supplied to the video signal line at the farthest position from the display area is connected to the data line. The writing time (delay time) is shorter than that of the comparative panel. Conversely, the writing time (delay time) of the B video signal supplied from the display area to the video signal line at the nearest position to the data line is longer than that of the panel of the comparative example. Specifically, when the wiring width w of the video signal line is 5.0, in the panel according to the present embodiment, the delay time difference is reduced by about 10% compared to the panel of the comparative example. As described above, by adjusting the contact position as in the present embodiment, the write delay from the video signal farthest from the display area to the data line and the write delay from the video signal at the latest position to the data line are reduced. The effect of reducing the difference increases as the wiring width of the video signal line increases.

  In FIG. 10, the writing time to the data line when the wiring width w of the video signal line is increased is evaluated. However, even when the number of video signal lines is increased, the maximum display area is obtained. Since the distance between the far position and the nearest position becomes large, the data lines from the video signal lines on the far end side and the near side are adjusted by adjusting the contact position between the video signal line and the connection wiring as in this embodiment. A high effect of alleviating the difference in signal writing time to can be obtained.

  As the number of panels becomes higher, the screen is enlarged, and the number of colors is increased, the number of video signal lines and the line width of video signal lines are increased. Therefore, by adjusting the contact position as in this embodiment, the difference in writing time can be reduced, that is, the writing variation can be reduced, so that unevenness in display luminance can be prevented for each data line. Can be maintained and improved.

  In the above description, each video signal line 250 is supplied with a video signal for a corresponding color among a plurality of video signals corresponding to the display color, and the connection wiring 260 and the H switch 240 are connected to the video signal line 250. A video signal of a specific color is supplied to the data line 14 connected thereto. In such a case, corresponding color pixels are connected to each data line 14 in the display area regardless of whether the pixel arrangement is a so-called stripe arrangement or delta arrangement. On the other hand, when the pixel connected to the data line 14 is a pixel having a different color for each row, the video signal line 250 to which the data line 14 is connected to the H switch 240 via the connection wiring 260 has a corresponding pixel. A plurality of video signals are sequentially supplied. Even in such a case, in order to realize a display that executes parallel data writing to a plurality of data lines for high-speed driving, a plurality of video signal lines 250 are arranged in parallel and used. Therefore, even when the video signal lines 250 to which video signals of a plurality of display colors are supplied are arranged in parallel, the contact position between the corresponding video signal line 250 and the connection wiring 260 is adjusted as described above. Further, it is possible to prevent a large difference in the write delay amount for each data line, and it is possible to obtain a display with high display quality by suppressing display unevenness.

  Further, the display color assigned to each pixel has been described for the case of the above R, G, B, or even W, but of course it is not limited to this, and other colors or colors other than the three primary colors may be used. This is also applicable to a configuration in which additional pixels are employed and pixels and video signal lines corresponding thereto are provided.

(Connection wiring terminal position)
Next, the termination position of the connection wiring will be described. In the above description, the connection wiring 260 extending from the H switch 240 is terminated at the connection position with the corresponding video signal line 250, that is, at the position where the contact hole h25 is formed. However, as shown in FIG. 11, it may be formed to extend to the termination region of the video signal line connected via the contact hole (the far end region from the display region of the video signal line). In this way, the end position of the connection wiring extends to the periphery of the far end portion of the video signal line to be connected, and in particular, the wiring of the connection wiring connected to the video signal line arranged on the far end side from the pixel region. The area can be improved. That is, this connection wiring is connected to the video signal line by a contact hole formed on the side close to the display area of the video signal line in accordance with the above-mentioned rules, but the connection wiring layer further extends from the contact hole formation area. As a result, the wiring area can be increased and the wiring resistance can be reduced.

  Even in this case, when there is a video signal line further adjacent to the far end side of the display area, the video signal line is formed before the adjacent far end video signal line forming area. The connection wiring is preferably terminated. Thereby, it is possible to prevent the connection wiring and the video signal line not to be connected from being short-circuited (adjacent video signal lines are short-circuited) due to insulation failure of the interlayer insulating layer 120 or the like. Further, since the number of intersections between the connection wiring and the video signal line which is not necessary can be reduced, the parasitic capacitance is minimized and the writing speed to the data line is improved.

  As shown in FIG. 10, by extending the end position of the connection wiring from the contact position, the connection wiring area between the video signal line located on the far end side from the display area and the corresponding H switch can be increased, and the resistance of the connection wiring can be reduced. It becomes possible to reduce. In addition, it is possible to expand an allowable range with respect to a displacement of a contact hole formation position for connecting a video signal line located on the far end side from the display area and the connection wiring.

1 is a diagram showing an equivalent circuit configuration of an active matrix EL display device according to an embodiment of the present invention. It is a figure which shows the wiring structure around the output part of the H type | system | group driver of FIG. It is a figure which shows an example of the cross-section of the H switch 240 along the AA line of FIG. It is a figure which shows an example of schematic sectional structure of the selection transistor and element drive transistor of a pixel corresponding to the data line to which H switch 240 is connected. It is a figure which shows schematic plan structure of H switch periphery when four video signal lines are arranged in parallel. It is a figure which shows the contact position adjustment method different from FIG. 5 when four video signal lines are arranged in parallel. It is a figure which shows the adjustment method of a contact position different from FIG. 6 when four video signal lines are arranged in parallel. It is a figure explaining the contact position of the video signal line | wire and connection wiring in the panel of embodiment. It is a figure explaining the contact position of the video signal line and connection wiring in the panel of a comparative example. It is a figure which shows the comparison result of write delay amount with the panel of this embodiment, and the panel of a comparative example. It is a figure explaining the other extension structure of the connection wiring which concerns on embodiment of this invention. It is a figure which shows the wiring structure of the H switch area | region concerning a prior art. It is a figure which shows the wiring structure of the H switch area | region for reducing the difference of the wiring resistance concerning a prior art. It is a figure which shows the wiring structure different from FIG. 13 of the H switch area | region for reducing the difference of the wiring resistance concerning a prior art.

Explanation of symbols

  10 selection lines, 12 capacitance lines, 14 data lines, 16 power supply lines, 100 display areas, 110 panel substrates, 112 buffer layers, 114 active layers (polycrystalline silicon layers), 116 gate insulation films, 118 gate electrodes, 120 interlayer insulation Layer, 130s source electrode, 130d drain electrode, 140 data intermediate wiring, 200 driver (peripheral drive circuit), 210 V system driver, 220 H system driver, 240 H switch, 250, 250r, 250g, 250b, 250w video signal line, 260 connection wiring, 260c center connection wiring, 260f far end side connection wiring, 260n proximity side connection wiring.

Claims (12)

A display area comprising pixels arranged in a matrix;
A video signal line for supplying a display signal to the plurality of pixels in the display area;
A switch circuit for selectively supplying the display signal from the video signal line to a data line connected to a pixel in a corresponding column of the display area;
A display device comprising:
The video signal lines are formed on the outside of the display area along a side of the display area and aligned with each other.
The switch circuit is provided for each data line between the video signal line and the display area, and the switch circuit is connected to the corresponding video signal line via a contact hole in accordance with a data output control signal. Electrically connected to the corresponding data line,
The video signal line closest to the display region and the farthest video signal line have different formation positions in the signal line line width direction of the contact hole connecting the connection wiring to the video signal line. apparatus. A display area comprising pixels arranged in a matrix;
A video signal line for supplying a display signal to the plurality of pixels in the display area;
A switch circuit for selectively supplying the display signal from the video signal line to a data line connected to a pixel in a corresponding column of the display area;
A display device comprising:
The video signal lines are formed on the outside of the display area along a side of the display area and aligned with each other.
The switch circuit is provided for each data line between the video signal line and the display area, and the switch circuit is connected to the corresponding video signal line via a contact hole in accordance with a data output control signal. Electrically connected to the corresponding data line,
A contact hole between at least the video signal line closest to the display area and the corresponding connection wiring is formed on the far end side with respect to the display area from the center in the line width direction of the video signal line,
At least the contact hole between the video signal line farthest from the display area and the corresponding connection wiring is formed nearer to the display area than the center in the line width direction of the video signal line. Characteristic display device. The display device according to claim 1 or 2,
The video signal line is provided with an odd number of at least three or more, and a contact hole between the video signal line disposed in the center and a corresponding connection wiring is in a line width direction of the video signal line. A display device characterized in that it is formed in the central region. The display device according to claim 1 or 2,
Four or more video signal lines are provided, and a contact hole between the two or more video signal lines formed in the center and the corresponding connection wiring is in the line width direction of each video signal line. A display device characterized in that it is formed in the central region. The display device according to claim 1 or 2,
2n video signal lines are provided (where n is a natural number of 1 or more),
A contact hole between the n video signal lines on the proximity side of the display area and the corresponding connection wiring is formed on the far end side of the display area in the line width direction of each video signal line,
A contact hole between the n video signal lines on the far end side of the display area and the corresponding connection wiring is formed on the near end side of the display area in the line width direction of each video signal line. Display device. A display area comprising pixels arranged in a matrix;
A video signal line for supplying a display signal to the plurality of pixels in the display area;
A switch circuit for selectively supplying the display signal from the video signal line to a data line connected to a pixel in a corresponding column of the display area;
A display device comprising:
The video signal lines are formed on the outside of the display area along the side of the display area, side by side,
The switch circuit is provided for each data line between the video signal line and the display area, and the switch circuit is connected to the corresponding video signal line via a contact hole in accordance with a data output control signal. Electrically connected to the corresponding data line,
A plurality of video signal lines are provided for each color to constitute a video signal group for each color,
In the group closest to the display region among the plurality of video signal line groups, the contact hole is formed on the far end side of the display region from the center in the line width direction of each video signal line,
In the group farthest from the display area, the contact hole is formed closer to the display area than the center of each video signal line in the line width direction. The display device according to claim 6,
Among the plurality of video signal line groups, in the video signal line group arranged in the center, contact holes between the respective video signal lines and the corresponding connection wirings are arranged in the line width direction of the video signal lines. A display device formed in a central region. In the display device according to any one of claims 1 to 7,
The connection wiring extends from the corresponding switch circuit toward the video signal line to be connected, and is in front of the adjacent video signal line forming region disposed on the far end side of the display region of the video signal line. A display device characterized in that it is terminated with. The display device according to any one of claims 1 to 8,
When the diameter of the contact hole is indicated by L and the width of the video signal line is indicated by w,
A display device satisfying 2L ≦ w. The display device according to any one of claims 1 to 8,
The formation position of the contact hole indicates the position in the line width direction of the video signal line by 0 which is the near end of the display area and w which is equal to the line width of the display area, and the contact hole diameter is a natural number smaller than w. L
The center of the contact hole formed on the near end side of the display area of each video signal line is
Provided between L / 2 and (w / 2−L / 2),
The center of the contact hole formed on the far end side of the display area of each video signal line is
A display device provided between (w / 2 + L / 2) and (w−L / 2). In the display device according to any one of claims 1 to 10,
The display device, wherein the pixel is provided with a current-driven electroluminescence element as a display element. In the display device according to any one of claims 1 to 11,
A video signal for each corresponding display color is supplied to each of the plurality of video signal lines,
A display device characterized in that a signal having the largest amplitude among the video signals for each display color is supplied to a video signal line closest to the display area in the video signal line.

Images