CN108172120B

CN108172120B - Pixel array substrate

Info

Publication number: CN108172120B
Application number: CN201711283695.9A
Authority: CN
Inventors: 陈雅柔; 谢腾毅; 庄博钧
Original assignee: E Ink Holdings Inc
Current assignee: E Ink Holdings Inc
Priority date: 2016-12-07
Filing date: 2017-12-07
Publication date: 2020-05-19
Anticipated expiration: 2037-12-07
Also published as: TW201821886A; TWI625581B; CN108172120A

Abstract

The invention discloses a pixel array substrate, which comprises a display area with a plurality of pixel areas, a plurality of signal lines, a plurality of transmission lines, a plurality of selection lines and a plurality of jumper wires. The signal lines and the transmission lines are staggered to form pixel regions. The selection lines pass through the pixel regions and are interlaced with the signal lines to form a plurality of interlaced regions. The selection line is provided with a plurality of first contacts, a plurality of second contacts and a plurality of third contacts which are adjacent to the first contacts. The first contact is located on the staggered area and between the second contact and the third contact. The first contact of the first portion is passed by a straight line of the display area. The jumper wires respectively pass through the first connecting points, and two ends of each jumper wire are respectively positioned on one of the second connecting points and one of the third connecting points. The jumper wire of the first part is electrically connected with the first contact of the first part and the second contact of the first contact of the adjacent first part, but is electrically insulated from the third contact of the first contact of the adjacent first part. The design can avoid the condition of uneven diagonal brightness of the display area when the picture is displayed.

Description

Pixel array substrate

Technical Field

The invention relates to a pixel array substrate.

Background

As display panels are widely used in various displays, for example: televisions, notebook computers, tablet computers, electronic paper (e-paper) books, mobile phones, and the like. Displays of Narrow bezel (Narrow bezel) design are a current trend in the display industry.

In order to realize a narrow bezel design of a display, in a pixel array, signal lines (scan lines or data lines) may extend in a horizontal direction, and select lines may extend in a vertical direction and be connected to the signal lines with contacts to transmit signals from the select lines to the signal lines. In this way, when the signal is transmitted, the signal can be transmitted from the selection line in the vertical direction to the signal line in the horizontal direction, and further transmitted to the pixel region in the same column through which the signal line passes. The circuit layout can be called as T-wired design, and the circuit can enter and exit the pixel area from the same side of the display panel, so that the traditional circuit design of entering and exiting the pixel area from the two adjacent sides of the display panel is replaced, and the area covered by the frame can be reduced.

However, in the T-wired design, due to the capacitive coupling effect between the select lines and the pixel electrodes, the panel may have uneven diagonal brightness (Mura) when displaying the image, which may further affect the image quality of the display.

Disclosure of Invention

The present invention is directed to a pixel array substrate, which can avoid the uneven brightness of the diagonal line of the display area when displaying the image.

According to an embodiment of the present invention, a pixel array substrate includes a display area, a plurality of signal lines, a plurality of transmission lines, a plurality of selection lines, and a plurality of jumper lines. The display area has a plurality of pixel areas therein. The signal lines and the transmission lines are staggered to form pixel regions. The selection lines pass through the pixel regions and are interlaced with the signal lines to form a plurality of interlaced regions. The selection line is provided with a plurality of first contacts, a plurality of second contacts and a plurality of third contacts which are adjacent to the first contacts. The first contacts are respectively located on the staggered areas. Each first contact is located between one of the second contacts and one of the third contacts. The first contact of the first portion is passed by a straight line of the display area. The jumper wires respectively pass through the first connecting points, and two ends of each jumper wire are respectively positioned on one of the second connecting points and one of the third connecting points. The jumper wire of the first part is electrically connected with the first contact of the first part and the second contact of the first contact of the adjacent first part, but is electrically insulated from the third contact of the first contact of the adjacent first part.

In an embodiment of the invention, the pixel array substrate further includes an insulating layer. The insulating layer covers the selection lines and is provided with a plurality of openings. The first contact of the first part and the second contact adjacent to the first contact are positioned in the opening, and the jumper wire of the first part is contacted with the first contact and the second contact in the opening.

In an embodiment of the invention, the pixel array substrate further includes a plurality of insulators. The insulator is arranged between the insulating layer and the jumper wire of the first part, and the position of the insulator corresponds to the position of a third contact adjacent to the first contact of the first part.

In one embodiment of the present invention, the width of the insulator is substantially the same as the width of the opening.

In an embodiment of the invention, the first contact of the second portion is located on one side of the straight line, and the jumper of the second portion electrically connects the second contact and the third contact adjacent to the first contact of the second portion, but is electrically insulated from the first contact of the second portion.

In an embodiment of the invention, the pixel array substrate further includes an insulating layer. The insulating layer covers the selection lines and is provided with a plurality of openings. The second and third contacts adjacent the first contacts of the second portion are located in the openings and the jumper wires of the second portion contact the second and third contacts in the openings.

In an embodiment of the invention, the pixel array substrate further includes a plurality of insulators. The insulator is positioned between the insulating layer and the jumper wire of the second part, and the position of the insulator corresponds to the position of the first contact of the second part.

In an embodiment of the invention, the first contact of the third portion is located on one side of the straight line, and the jumper of the third portion is electrically insulated from the first contact of the third portion, and the second contact and the third contact of the first contact of the adjacent third portion.

In an embodiment of the invention, the pixel array substrate further includes an insulating layer and a plurality of insulators. The insulating layer covers the selection lines. The insulator is positioned between the insulating layer and the jumper wire of the third part, and the position of the insulator corresponds to the position of the first contact of the third part, and the positions of the second contact and the third contact which are adjacent to the first contact of the third part.

In an embodiment of the present invention, the signal lines are data lines or scan lines.

In the above embodiments of the present invention, although the diagonal line (i.e., the straight line) of the display area passes through the first contact, the selection line further has the second contact and the third contact adjacent to the first contact, so that the jumper line can electrically connect the first contact and the second contact but is electrically insulated from the third contact. Therefore, the signal transmitted by the selection line can be transmitted to the first contact through the second contact and the jumper wire, and the first contact is positioned in the staggered area of the selection line and the signal line, so that the signal can be transmitted to the signal line. Because the third contact adjacent to the first contact through which the diagonal line passes is electrically insulated from the jumper wire, the selection line on one side of the diagonal line of the display area can not transmit signals, the condition (Mura) that the diagonal line of the display area has uneven brightness when the pixel array substrate displays the picture can be avoided, and the picture quality of the display is improved.

Drawings

Fig. 1 is a partially enlarged view of a display region of a pixel array substrate according to an embodiment of the invention.

Fig. 2 is a cross-sectional view of the pixel array substrate of fig. 1 along line 2-2.

Fig. 3 is a cross-sectional view of the pixel array substrate of fig. 1 along line 3-3.

Fig. 4 is a cross-sectional view of the pixel array substrate of fig. 1 along line 4-4.

Fig. 5 is a partially enlarged view of a display region of a pixel array substrate according to an embodiment of the invention.

Detailed Description

In the following description, numerous implementation details are set forth in order to provide a thorough understanding of various embodiments of the invention. It should be understood, however, that these implementation details are not to be interpreted as limiting the invention. That is, in some embodiments of the invention, such implementation details are not necessary. In addition, for the sake of simplicity, some conventional structures and elements are shown in the drawings in a simple schematic manner.

Fig. 1 is a partially enlarged view of a display region 110 of a pixel array substrate 100 according to an embodiment of the invention. As shown, the pixel array substrate 100 includes a display region 110, a plurality of signal lines 120, a plurality of transmission lines 180, a plurality of selection lines 130, and a plurality of

jumper lines

140a, 140b, and 140 c. The display area 110 has a plurality of pixel areas 112 therein, and the plurality of pixel areas 112 are formed by a plurality of signal lines 120 and a plurality of transmission lines 180 in an interlaced manner. The selection lines 130 pass through the pixel regions 112 and are interleaved with the signal lines 120 to form a plurality of interleaved regions P. For example, the select line 130 is substantially perpendicular to the signal line 120. The selection line 130 has a plurality of

first contacts

132a, 132b, 132c, a plurality of second contacts 134, and a plurality of third contacts 136. The first contact 132a of the first portion is passed by the diagonal line L of the display area 110, the first contact 132b of the second portion is located on one side of the diagonal line L of the display area 110 (e.g., on the lower side or the right side of the diagonal line L), and the first contact 132c of the third portion is located on the other side of the diagonal line L of the display area 110 (e.g., on the upper side or the left side of the diagonal line L). In addition, each of the

first contacts

132a, 132b, 132c is adjacent to the second contact 134 and the third contact 136, and is located between the second contact 134 and the third contact 136. The

first contacts

132a, 132b, 132c are respectively located on the crossing regions P of the selection lines 130 and the signal lines 120. The diagonal line L of the preferred embodiment may be defined as a straight line passing through a respective one of the first contacts 132a of each of the adjacent select lines 130 in the display area 110.

The first portion of the jumper 140a passes through the first contact 132a, the second portion of the jumper 140b passes through the first contact 132b, and the third portion of the jumper 140c passes through the first contact 132 c. In this context, "the jumper passes through the first contact" means that the jumper passes over the first contact, and it is possible for the jumper to be electrically connected to or electrically insulated from the first contact. In addition, two ends of each

jumper wire

140a, 140b, 140c are respectively located on the second contact 134 and the third contact 136. The jumper 140a electrically connects the first contact 132a with the second contact 134 adjacent to the first contact 132a, but the jumper 140a is electrically insulated from the third contact 136 adjacent to the first contact 132 a. In fig. 1, the oblique lines indicate electrical connection with the jumper, and the blank lines indicate electrical insulation from the jumper.

In the pixel array substrate 100, although the diagonal line L of the display region 110 passes through the first contact 132a, the selection line 130 further has a second contact 134 and a third contact 136 adjacent to the first contact 132a, so that the jumper line 140a can electrically connect the first contact 132a and the second contact 134 but is electrically insulated from the third contact 136. In this way, the signal transmitted by the selection line 130 in the direction D1 can be transmitted to the first contact 132a through the second contact 134 and the jumper 140a, and the first contact 132a is located in the crossing region P of the selection line 130 and the signal line 120, so that the signal can be transmitted to the signal line 120, and the signal line 120 can transmit the signal to the pixel regions 112 in the same column in the directions D2 and D3. Since the third contact 136 adjacent to the first contact 132a passing through the diagonal line L is electrically insulated from the jumper 140a, the select line 130 on one side of the diagonal line L (e.g., the upper side or the left side of the diagonal line L) of the display area 110 does not transmit a signal in the direction D1, so that the uneven brightness (Mura) of the diagonal line L of the display area 110 can be avoided when the pixel array substrate 100 displays a picture, and the picture quality of the display can be improved.

When the pixel array substrate 100 is inspected by an Automated Optical Inspection (AOI) machine, the machine compares whether the line structures near the interleaving region P are consistent, and if the line structures are inconsistent, it is determined that a Defect (Defect) occurs in the line structure. In the present embodiment, the jumper wire 140b electrically connects the second contact 134 and the third contact 136 adjacent to the first contact 132b, but is electrically insulated from the first contact 132 b. The jumper 140c is electrically insulated from the first contact 132c, and the second contact 134 and the third contact 136 adjacent to the first contact 132 c. In this way, the circuit structures of each pixel region 112 have the same design, for example, each pixel region 112 has one signal line 120 and one selection line 130 staggered, and three adjacent contacts and one jumper are disposed near each staggered region P, so that the circuit structures near the staggered positions of the signal lines 120 and the selection lines 130 are the same, and the machine interpretation errors can be avoided through automatic optical inspection, thereby ensuring the qualified rate of the pixel array substrate 100.

In the present embodiment, the signal line 120 is electrically connected to the gate of the pixel array substrate 100, and therefore the signal line 120 is a scan line (or gate line). The signal line 120 is electrically connected to the selection line 130 by the first contact 132a to transmit a signal to the gate.

It should be understood that the connection relationship between the elements already described will not be repeated and will be described in the first place. In the following description, a cross-sectional structure of the pixel array substrate 100 will be described.

Fig. 2 is a cross-sectional view of the pixel array substrate 100 of fig. 1 along the line 2-2. Referring to fig. 1 and 2, the pixel array substrate 100 further includes an insulating layer 160. The insulating layer 160, the selection lines 130 and the signal lines 120 are disposed on the substrate 150. The insulating layer 160 covers the selection line 130, and the insulating layer 160 has a plurality of

openings

162 and 164. The selection line 130 is exposed from the

openings

162 and 164 to serve as the first contact 132a and the second contact 134 of fig. 1, respectively. That is, the first contact 132a is located in the opening 162 of the insulating layer 160, and the second contact 134 adjacent to the first contact 132a is located in the opening 164 of the insulating layer 160. The jumper 140a contacts the first contact 132a in the opening 162 and the second contact 134 in the opening 164.

In addition, the pixel array substrate 100 further includes a plurality of insulators 170a, and the insulators 170a are located between the insulating layer 160 and the jumper wires 140 a. The insulator 170a is positioned to correspond to the position of the third contact 136 adjacent to the first contact 132 a. That is, the insulator 170a serves as the third contact 136 of fig. 1, which is not electrically conducted with the jumper line 140a and the select line 130, and serves as a dummy contact. In the present embodiment, the width W2 of the insulator 170a is substantially the same as the width W1 of the

openings

162, 164.

In the present embodiment, the substrate 150 may have flexibility, which includes a polymer material. An electronic ink layer and a front panel may be disposed above the pixel array substrate 100, and may be applied to a flexible display device, such as an electronic paper (e-paper) display device.

Fig. 3 is a cross-sectional view of the pixel array substrate 100 of fig. 1 along line 3-3. Referring to fig. 1 and 3, the insulating layer 160 has a plurality of

openings

166 and 168. The selection line 130 is exposed from the

openings

166 and 168 to serve as the second contact 134 and the third contact 136 adjacent to the first contact 132b in fig. 1, respectively. That is, the second contact 134 adjacent to the first contact 132b is located in the opening 166 of the insulating layer 160, and the third contact 136 adjacent to the first contact 132b is located in the opening 168 of the insulating layer 160. The jumper 140b contacts the second contact 134 in the opening 166 and the third contact 136 in the opening 168.

In addition, the pixel array substrate 100 further includes a plurality of insulators 170b, and the insulators 170b are located between the insulating layer 160 and the jumper wires 140 b. The position of the insulator 170b corresponds to the position of the first contact 132 b. That is, the insulator 170b serves as the first contact 132b of fig. 1, which is not electrically conducted with the jumper line 140b and the select line 130, as a dummy contact. In the present embodiment, the width W2 of the insulator 170b is substantially the same as the width W1 of the

openings

166, 168.

Fig. 4 is a cross-sectional view of the pixel array substrate 100 of fig. 1 along the line 4-4. Referring to fig. 1 and 4, the pixel array substrate 100 further includes a plurality of

insulators

170c, 170d, and 170 e. The

insulators

170c, 170d, and 170e are disposed between the insulating layer 160 and the jumper 140c, and the insulator 170c is disposed at a position corresponding to the first contact 132c, the insulator 170d is disposed at a position corresponding to the second contact 134 adjacent to the first contact 132c, and the insulator 170e is disposed at a position corresponding to the third contact 136 adjacent to the first contact 132 c. That is, the

insulators

170c, 170d, and 170e serve as the first contact 132c, the second contact 134 adjacent to the first contact 132c, and the third contact 136 adjacent to the first contact 132c of fig. 1, respectively. The

insulators

170c, 170d, and 170e are not electrically connected to the jumper line 140c and the selection line 130, and serve as dummy contacts. In the present embodiment, the

insulators

170c, 170d, and 170e have the same width W2.

Fig. 5 is a partially enlarged view of the display region 110 of the pixel array substrate 100a according to an embodiment of the invention. The pixel array substrate 100a includes a display region 110, a plurality of signal lines 120a, a plurality of selection lines 130a, and

jumper lines

140a, 140b, and 140 c. The difference from the embodiment of fig. 1 is that the signal line 120a is electrically connected to the source of the pixel array substrate 100, and thus the signal line 120a is a data line. The signal line 120a is electrically connected to the selection line 130a by the first contact 132a to transmit a signal to the source.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A pixel array substrate, comprising:

a display area having a plurality of pixel areas therein;

the plurality of signal lines and the plurality of transmission lines are staggered to form the plurality of pixel areas;

a plurality of selection lines passing through the plurality of pixel regions and crossing the plurality of signal lines to form a plurality of crossing regions, the plurality of selection lines having a plurality of first contacts and a plurality of second contacts and a plurality of third contacts adjacent to the plurality of first contacts, wherein the plurality of first contacts are respectively located on the plurality of crossing regions, each of the first contacts is located between the second contact and the third contact adjacent thereto, and a first portion of the plurality of first contacts passes through a straight line of the display region; and

and a plurality of jumper wires, which pass through the plurality of first contacts respectively, and both ends of each of the plurality of jumper wires are located on one of the plurality of second contacts and one of the plurality of third contacts respectively, wherein the plurality of jumper wires of the first portion are electrically connected with the plurality of first contacts of the first portion and the plurality of second contacts adjacent to the plurality of first contacts of the first portion, but the plurality of jumper wires of the first portion are electrically insulated from the third contacts adjacent to the plurality of first contacts of the first portion.

2. The pixel array substrate of claim 1, further comprising:

and the insulating layer covers the plurality of selection lines and is provided with a plurality of openings, wherein the plurality of first contacts of the first part and the plurality of second contacts adjacent to the first contacts are positioned in the plurality of openings, and the plurality of jumper wires of the first part are in contact with the plurality of first contacts and the plurality of second contacts in the plurality of openings.

3. The pixel array substrate of claim 2, further comprising:

and a plurality of insulators between the insulating layer and the plurality of jumper wires of the first portion, and the positions of the insulators correspond to the positions of the plurality of third contacts adjacent to the plurality of first contacts of the first portion.

4. The pixel array substrate of claim 3, wherein a width of the plurality of insulators is the same as a width of the plurality of openings.

5. The pixel array substrate of claim 1, wherein the first contacts of the second portion are located on one side of the straight line, and the jumpers of the second portion electrically connect the second contacts and the third contacts adjacent to the first contacts of the second portion, but are electrically insulated from the first contacts of the second portion.

6. The pixel array substrate of claim 5, further comprising:

an insulating layer covering the plurality of selection lines and having a plurality of openings, wherein the plurality of second contacts and the plurality of third contacts adjacent to the second portion of the plurality of first contacts are located in the plurality of openings, and the plurality of jumper lines of the second portion contact the plurality of second contacts and the plurality of third contacts in the plurality of openings.

7. The pixel array substrate of claim 6, further comprising:

and the insulators are positioned between the insulating layer and the jumpers of the second part, and the positions of the insulators correspond to the positions of the first contacts of the second part.

8. The pixel array substrate of claim 1, wherein the first contacts of the third portion are located on one side of the straight line, and the jumpers of the third portion are electrically insulated from the first contacts of the third portion, and the second contacts adjacent to the first contacts of the third portion are electrically insulated from the third contacts.

9. The pixel array substrate of claim 8, further comprising:

an insulating layer covering the plurality of selection lines; and

and a plurality of insulators positioned between the insulating layer and the plurality of jumper wires of the third portion, wherein the positions of the insulators correspond to the positions of the plurality of first contacts of the third portion, and the positions of the plurality of second contacts and the plurality of third contacts adjacent to the plurality of first contacts of the third portion.

10. The pixel array substrate of claim 1, wherein the plurality of signal lines are data lines or scan lines.