JP2009205097A - Electro-optical device and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To allow a common electrode in part of a display area to have the same potential with respect to an electro-optical device such as a liquid crystal device which adopts common COM division driving. <P>SOLUTION: The electro-optical device (100) includes: a connection circuit (113) for connecting a first voltage supply line (ZH) and a second voltage supply line (ZL)to the common electrode so that a first voltage (VOCMH) and a second voltage (VCOML) may be alternately supplied to adjoining two common electrodes out of a plurality of common electrodes (11, COM1 to COMn) which are formed corresponding to a pixel electrode for each of one or more horizontal lines; and a control circuit (112) for controlling the connection circuit so that only either of the first voltage supply line or the second voltage supply line may be connected to the common electrode corresponding to the part of display area. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a technical field of an electro-optical device such as a liquid crystal device and an electronic apparatus including such an electro-optical device.

  An example of this type of electro-optical device is a liquid crystal device in which a liquid crystal, which is an example of an electro-optical material, is sandwiched between a pair of element substrates and a counter substrate. In a display region (pixel region) in which a plurality of pixels are arranged on the element substrate, a pixel portion including a pixel electrode corresponding to the intersection of the scanning line and the data line is formed, so that the plurality of pixel portions are They are arranged in a matrix form on a plane. Each pixel unit includes, for example, a thin film transistor (hereinafter referred to as “TFT” as appropriate) as a pixel switching element. When the electro-optical device is driven, when a pixel switching element is turned on by supplying a scanning signal from the scanning line in each pixel unit, an image signal is supplied from the data line to the pixel electrode via the pixel switching element. . Further, typically, a common electrode (or a counter electrode) is formed in a solid shape in common with the plurality of pixel portions in almost the entire display area corresponding to the plurality of pixel electrodes. When the liquid crystal device is driven, an applied voltage based on a potential difference between the pixel electrode and the common electrode is applied to the liquid crystal. As a result, the orientation and order of the liquid crystals are controlled, and image display is possible.

  In such a liquid crystal device, in recent years, in order to realize low power consumption of the liquid crystal device, the common electrode is divided into one horizontal line (one row) (for example, divided along a direction parallel to the scanning line). Voltage of a certain potential level (for example, relatively high level) is supplied to the common electrode of the same row, and voltages of different potential levels (for example, relatively low level) are common to adjacent rows. While being supplied to the electrodes, driving is performed in which the potential level of the voltage is inverted by one row every horizontal scanning period (hereinafter, such driving is appropriately referred to as “COM divided driving”) (see Patent Document 1). . As a result, it is possible to reduce power consumption compared to a driving mode in which the voltage level of all the common electrodes is supplied to all the common electrodes and the potential levels of all the common electrodes are collectively reversed every horizontal scanning period. Electricity can be achieved.

  On the other hand, partial driving (partial display driving) may be used as another driving mode for reducing power consumption in such a liquid crystal device. In a liquid crystal device adopting partial drive, black display (in the normally black mode) or white in a non-display area where display is not performed, that is, a part of the display area, where the liquid crystal drive is stopped. Display (in normally white mode). On the other hand, a significant image is displayed as information only in another part of the display area. Thereby, low power consumption is realized. Such partial drive is used, for example, when displaying a standby screen of a mobile phone.

Japanese Patent Application No. 2006-183051

  Incidentally, in order to perform black display or white display, it is necessary to make the potential difference applied to the liquid crystal the same in the entire non-display area. In other words, it is necessary to make the potential of the pixel electrode corresponding to the non-display area constant and make the potential of the common electrode constant.

  On the other hand, in the above-described COM division driving, different voltages are supplied to the common electrodes of adjacent horizontal lines. For this reason, in order to further apply the partial drive to the liquid crystal device adopting the COM split drive, it is necessary to change the drive method of the COM split drive. Here, in the COM divided drive, a high level voltage supply line connected to a high level voltage source for supplying a relatively high level voltage, and a low level for supplying a relatively low level voltage. By connecting the low level voltage supply line connected to the voltage source alternately to each common electrode (in other words, a common wiring for supplying a common voltage to each common electrode), the adjacent horizontal lines Different voltages are supplied to the common electrode of the line. For this reason, in order to make the potential of the common electrode corresponding to the non-display area constant, a low level voltage source is newly connected to the high level voltage supply line, or the low level voltage supply line is connected. One method is to connect a new high-level voltage source. Accordingly, the COM divided drive is performed without largely changing the timing at which the common electrode and the voltage supply line are connected (in other words, without greatly changing the circuit configuration for connecting the common electrode and the voltage supply line). It is considered that partial driving can be further applied to the liquid crystal device to be employed.

  However, in this method, since it is necessary to provide a new voltage source, the power consumption of the entire drive circuit for supplying the common voltage increases, or the circuit scale / area / cost, etc. of the drive circuit increases. The technical problem of increasing will arise.

  In addition to the partial drive, a similar technical problem occurs in a liquid crystal device that is driven while providing a non-display area in which black display (in the normally black mode) or white display (in the normally white mode) is performed. It will occur.

  The present invention has been made in view of, for example, the above-described conventional problems. For example, the potential of the common electrode in a part of the display region is set to the same potential as that of an electro-optical device such as a liquid crystal device employing COM division driving. It is an object of the present invention to provide an electro-optical device including a driving device that can be used, and an electronic apparatus including such a driving device.

(Electro-optical device)
The electro-optical device of the present invention includes a plurality of pixel electrodes constituting a display region, a plurality of common electrodes formed corresponding to pixel electrodes for each of one or more horizontal lines, the plurality of pixel electrodes, and the plurality of pixel electrodes. An electro-optical device including an electro-optical material driven in accordance with an electric field applied between the first electrode and the common electrode adjacent to each other among the plurality of common electrodes. And a first voltage supply line to which the first voltage is supplied or a second voltage supply to which the second voltage is supplied so that a second voltage different from the first voltage is alternately supplied every predetermined period. A connection circuit for alternately connecting a line to each of the plurality of common electrodes, and the plurality of common electrodes corresponding to a part of the display region of the display region, the first voltage supply line and the Only one of the second voltage supply lines is fixedly connected And a control circuit for controlling the connection circuit so as to.

  According to the electro-optical device of the present invention, the electro-optical device can be driven by supplying a voltage to the common electrode provided in the electro-optical device such as a liquid crystal device through the common wiring. The electro-optical device to be driven by the electro-optical device according to the present invention includes, for example, a plurality of pixel electrodes provided so as to correspond to intersections between data lines to which image signals are supplied and scanning lines to which scanning signals are supplied. And a plurality of common electrodes provided for each of one or more horizontal lines (in other words, provided for each one scanning line or for each of two or more scanning lines). In other words, in the present invention, the common electrode that is normally formed in a solid shape is one horizontal line (for example, along a scanning line) or two or more horizontal lines (for example, along two or more scanning lines). It is divided electrically. Then, for each horizontal line, a voltage resulting from a potential difference between a part of the plurality of pixel electrodes belonging to each horizontal line and the common electrode is applied to the electro-optical material, whereby image display or the like is performed.

  In order to drive such an electro-optical device (in particular, to supply a voltage to the common electrode), the electro-optical device according to the present invention includes a connection circuit. At this time, the connection circuit drives the electro-optical device using COM division driving.

  Specifically, the connection circuit supplies a voltage to each of the plurality of common electrodes included in the electro-optical device, for example, via a plurality of common wires formed corresponding to the plurality of common electrodes. Here, the connection circuit according to the present invention supplies different voltages (that is, the first voltage and the second voltage) to two common electrodes adjacent to each other among the plurality of common electrodes. The first voltage supply line or the second voltage supply line is electrically connected to each of the plurality of common electrodes. In other words, the connection circuit inverts the polarity of the voltage supplied to the common electrode corresponding to the odd line (odd row) and the polarity of the voltage supplied to the common electrode corresponding to the even line (even row) to each other. As described above, the first voltage supply line or the second voltage supply line is electrically connected to each of the plurality of common electrodes. Specifically, the connection circuit has one of a first voltage (for example, a relatively high level voltage) and a second voltage (for example, a relatively low level voltage) with respect to one common electrode. One of the first voltage supply line and the second voltage supply line is electrically connected to the one common electrode so as to be supplied. Meanwhile, the connection circuit supplies the first voltage supply line and the second voltage supply so that the other of the first voltage and the second voltage is supplied to the other common electrode adjacent to the one common electrode. The other end of the line is electrically connected to the other common electrode.

  In addition, the connection circuit is configured so that the voltage supplied to the common electrode of each horizontal line is switched from the first voltage to the second voltage or from the second voltage to the first voltage every predetermined period. The first voltage supply line or the second voltage supply line is electrically connected to each of the plurality of common electrodes. For example, one of the first voltage supply line and the second voltage supply line and the one common electrode are electrically connected so that one of the first voltage and the second voltage is supplied to one common electrode in one predetermined period. The other one of the first voltage supply line and the second voltage supply line is connected so that the other one of the first voltage and the second voltage is supplied to one common electrode in another predetermined period following one predetermined period. The common electrode is electrically connected. The “predetermined period” means a period set in advance corresponding to the driving method as a period for switching from the first voltage to the second voltage or from the second voltage to the first voltage. An example is a vertical scanning period, a frame period, a field period, and the like.

  The electro-optical device according to the present invention further includes a control circuit. The control circuit supplies the first voltage supply line to all of the common electrodes corresponding to a part of the display region (for example, a non-display region where a valid image is not displayed or a supply of a valid image signal is stopped). And the connection circuit is controlled so that only one of the second voltage supply lines is connected. That is, different voltage supply lines for each horizontal line are not connected to the common electrode corresponding to a part of the display region. For this reason, the voltage of the common electrode corresponding to a part of the display region is fixed to the first voltage or the second voltage. At this time, the control circuit applies the first voltage supply line and the second voltage to all of the common electrodes corresponding to a part of the display area other than the part of the display area. The connection circuit may or may not be controlled so that any of the supply lines is connected.

  For this reason, even in an electro-optical device that employs COM division driving, all the potentials of the common electrode corresponding to a part of the display region can be made the same potential. Accordingly, black display (in the normally black mode) or white display (in the normally white mode) can be performed on a part of the display area. For this reason, for example, a part of the display area can be set as a non-display area, so that power consumption can be reduced.

  In particular, according to the present invention, the first voltage source for supplying the first voltage is connected to the first voltage supply line, and the second voltage source for supplying the second voltage is connected to the second voltage supply line. If so, all the potentials of the common electrode corresponding to a part of the display region can be made the same potential. In other words, in order to make all the potentials of the common electrode corresponding to a part of the display region part the same potential, a voltage source for supplying the second voltage to the first voltage supply line is newly provided and There is no need to connect a new voltage source to the first voltage supply line. Similarly, a voltage source for supplying a first voltage to the second voltage supply line is newly provided in order to make all the potentials of the common electrode corresponding to a part of the display region the same potential, and There is no need to connect a new voltage source to the second voltage supply line. Accordingly, partial driving or the like can be employed in an electro-optical device that employs COM split driving without significantly increasing the power consumption of the electro-optical device. Furthermore, partial driving or the like can be employed in an electro-optical device that employs COM split driving without significantly increasing the cost of the electro-optical device.

  In one aspect of the electro-optical device of the present invention, the electro-optical device further includes a latch circuit that holds a polarity signal for selecting the first voltage or the second voltage, and the control circuit is held by the latch circuit. The first voltage supply to the common electrode corresponding to the partial display area portion based on the polarity signal and the reference signal indicating whether or not the partial display area portion is scanned. The connection circuit is controlled so that only one of the line and the second voltage supply line is fixedly connected.

  With this configuration, the control circuit can detect the polarity signal that is normally referred to by the connection circuit and the reference signal that indicates the scanning timing for a part of the display region where the common electrode potential is set to the same potential (for example, one When the partial drive for performing black display or white display is performed on the display area portion of the part, a signal indicating whether or not the partial drive is performed is referred to) Can be controlled. For this reason, all the potentials of the common electrodes corresponding to a part of the display region can be made the same without affecting the normal operation of the COM division driving.

  In the aspect of the electro-optical device in which the control circuit controls the connection circuit based on each of the polarity signal and the reference signal as described above, the control circuit is provided so as to correspond to either the even line or the odd line, A first control circuit unit that outputs the polarity signal held by the latch circuit or a fixed signal having a fixed signal level according to the signal level of the reference signal, and one of the even line and the odd line. And a second control circuit unit that outputs the inverted signal of the polarity signal or the fixed signal held by the latch circuit according to the signal level of the reference signal.

  With this configuration, when scanning a part of the display area, signals having the same signal level in the odd lines and the even lines can be supplied from the control circuit to the connection circuit. On the other hand, when scanning with respect to a part of the display area other than a part of the display area part, the signals in which the polarity is inverted between the odd lines and the even lines (that is, the polarity signal and the inverted signal of the polarity signal). ) From the control circuit to the connection circuit. Therefore, it is possible to make all the potentials of the common electrode corresponding to a part of the display region the same potential without affecting the normal operation of the COM division driving.

  Alternatively, in the aspect of the electro-optical device in which the control circuit controls the connection circuit based on each of the polarity signal and the reference signal as described above, the control circuit is provided so as to correspond to either the even line or the odd line. A first control circuit unit that outputs the polarity signal (or its inverted signal) held by the latch circuit or a fixed signal having a fixed signal level according to the signal level of the reference signal; and the even line And the polarity signal (or its inverted signal) or the inverted signal of the fixed signal that is provided corresponding to the other of the odd lines and is held by the latch circuit according to the signal level of the reference signal May be configured to include a second control circuit unit that outputs.

  Even with this configuration, all the potentials of the common electrode corresponding to a part of the display region can be made the same potential.

  In the aspect of the electro-optical device in which the control circuit includes the first control circuit unit and the second control circuit unit as described above, the reference signal is at a low level at the timing when the partial display region is scanned. The polarity of the polarity signal held by the latch circuit is changed to a high level at a timing when scanning is performed on a display area portion other than the partial display area portion of the display area. And a NAND circuit that outputs a NAND signal of the reference signal and an inverting circuit that inverts the polarity of the NAND signal, and the second control circuit unit holds the polarity held by the latch circuit You may comprise so that the negative OR circuit which outputs the negative OR signal of a signal and the inversion signal of the said reference signal may be provided.

  With this configuration, when the reference signal is at a low level (that is, when scanning is performed on a part of the display area), the first control circuit unit (particularly, the negative logic included in the first control circuit unit). A relatively low level fixed signal is output from the product circuit. Further, a relatively low level fixed signal is output from the second control circuit unit (particularly, a negative OR circuit included in the second control circuit unit). Therefore, signals having the same signal level in the odd lines and the even lines can be supplied from the control circuit to the connection circuit. On the other hand, when the reference signal is at a high level (that is, when scanning is performed on the other part of the display area), the first control circuit unit (particularly, the NAND circuit included in the first control circuit unit) ) Outputs a polarity signal. Further, an inverted signal of the polarity signal is output from the second control circuit unit (particularly, a negative OR circuit included in the second control circuit unit). Therefore, a signal in which the polarity is inverted between the odd line and the even line can be supplied from the control circuit to the connection circuit. Thereby, without affecting the normal operation of the COM division driving, it is possible to make all the potentials of the common electrodes corresponding to a part of the display region portions the same potential.

  In the aspect of the electro-optical device in which the control circuit includes the first control circuit unit and the second control circuit unit as described above, the reference signal is at a low level at the timing when the partial display region is scanned. The polarity of the polarity signal held by the latch circuit is changed to a high level at a timing when scanning is performed on a display area portion other than the partial display area portion of the display area. And a negative OR circuit that outputs a negative logical sum signal of the inverted signal of the reference signal and an inverting circuit that inverts the polarity of the negative logical sum signal, and the second control circuit unit is held by the latch circuit. A NAND circuit that outputs a NAND signal of the polarity signal and the reference signal may be provided.

  With this configuration, when the reference signal is at a low level (that is, when scanning is performed on a part of the display area), the first control circuit unit (particularly, the negative logic included in the first control circuit unit). A relatively high level fixed signal is output from the sum circuit. Further, a relatively high level fixed signal is output from the second control circuit unit (particularly, a NAND circuit provided in the second control circuit unit). Therefore, signals having the same signal level in the odd lines and the even lines can be supplied from the control circuit to the connection circuit. On the other hand, when the reference signal is at a high level (that is, when scanning is performed on the other part of the display region), the first control circuit unit (particularly, the negative OR circuit included in the first control circuit unit) ) Outputs a polarity signal. Further, an inverted signal of the polarity signal is output from the second control circuit unit (particularly, a NAND circuit provided in the second control circuit unit). Therefore, a signal in which the polarity is inverted between the odd line and the even line can be supplied from the control circuit to the connection circuit. Thereby, without affecting the normal operation of the COM division driving, it is possible to make all the potentials of the common electrodes corresponding to a part of the display region portions the same potential.

  In another aspect of the electro-optical device according to the aspect of the invention, the control circuit may perform a partial drive for stopping the display in the partial display area portion with respect to the common electrode corresponding to the partial display area portion. Then, the connection circuit is controlled so that only one of the first voltage supply line and the second voltage supply line is fixedly connected.

  According to this aspect, even when black display or white display is performed in a part of the display area by performing partial driving, the above-described various effects can be suitably enjoyed.

  Here, “stop display” means not only the state in which driving is stopped by stopping the supply of image signals and scanning signals, and the display is literally stopped, but also the supply cycle of image signals and scanning signals. A state in which (writing cycle) is reduced, a state in which black or white display is performed by writing an off-potential of the liquid crystal (the same potential as the common electrode) to the pixel, and an image display by stopping the supply of a meaningful image signal It is a broad purpose including a state that does not contribute to the situation. That is, if the display of the part of the display area seems to be stopped, it corresponds to “stop display”.

  In another aspect of the electro-optical device according to the aspect of the invention, the control circuit may perform (i) a period in which scanning is performed in the partial display region portion, with respect to the common electrode corresponding to the partial display region portion Controlling the connection circuit so that only one of the first voltage supply line and the second voltage supply line is connected; and (ii) other than the part of the display area of the display area The connection circuit is configured so that the first voltage supply line or the second voltage supply line is alternately connected to a common electrode corresponding to the other display area portion during a period of scanning in the display area portion of To control.

  According to this aspect, it is possible to perform a normal image display operation using another part of the display area part while setting a part of the display area part as a non-display area.

  In another aspect of the electro-optical device according to the aspect of the invention, the electro-optical device is disposed so as to face the first substrate on which the plurality of pixel electrodes and the plurality of common electrodes are respectively formed. The electro-optic material is sandwiched between the first substrate and the second substrate.

  According to this aspect, for example, the above-described various effects can be obtained in an electro-optical device of a lateral electric field drive method such as an FFS method or an IPS method.

  Note that the plurality of common electrodes may be formed on the second substrate side.

  As described above, in the electro-optical device including the first substrate on which the plurality of pixel electrodes and the plurality of common electrodes are formed, the control circuit and the connection circuit are formed on the first substrate. Also good.

  According to this aspect, the control circuit and the connection circuit are formed by system-on-glass (SOG) technology in which circuit integration is performed on the glass substrate that forms the substrate using the low-temperature polysilicon technology on the substrate of the electro-optical device. , Formed on the same glass substrate as the first substrate on which the pixel electrodes are formed. As a result, the number of semiconductor components can be reduced, the assembly can be simplified, the external circuit board can be reduced, and the entire electro-optical device can be reduced in size, weight, and cost.

(Electronics)
In order to solve the above problems, an electronic apparatus according to the present invention includes the above-described electro-optical device according to the present invention (including various aspects thereof).

  According to the electronic apparatus of the present invention, since the electro-optical device (or various aspects thereof) of the present invention described above is provided, the same effects as those received by the electro-optical device of the present invention described above can be obtained. Can do. In other words, the projection display device, television, mobile phone, electronic notebook, portable audio player, word processor, digital camera, viewfinder type that can enjoy the same effects as those obtained by the electro-optical device of the present invention described above. Alternatively, various electronic devices such as a monitor direct-view video recorder, a workstation, a videophone, a POS terminal, and a touch panel can be realized.

  The operation and other advantages of the present invention will become more apparent from the embodiments described below.

  The best mode for carrying out the present invention will be described below with reference to the drawings. In the following description, a liquid crystal device is used as an example of the electro-optical device according to the invention.

(1) Basic Configuration of Liquid Crystal Device First, the configuration of the liquid crystal device according to the present embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view showing the configuration of the liquid crystal device according to this embodiment, and FIG. 2 is a cross-sectional view taken along the line HH ′ of FIG.

  1 and 2, in the liquid crystal device 100 according to the present embodiment, the TFT array substrate 10 as an example of the “first substrate” according to the present invention and the counter substrate 20 as an example of the “second substrate” according to the present invention. Are arranged opposite to each other. A liquid crystal layer 50 is sealed between the TFT array substrate 10 and the counter substrate 20, and the TFT array substrate 10 and the counter substrate 20 are in a frame-shaped or frame-shaped seal region located around the image display region 10a. The sealing material 52 provided is bonded to each other.

  The sealing material 52 is made of, for example, an ultraviolet curable resin, a thermosetting resin, or the like for bonding the two substrates, and is applied on the TFT array substrate 10 in the manufacturing process and then cured by ultraviolet irradiation, heating, or the like. It is. In the sealing material 52, spacers such as glass fibers or glass beads for dispersing the distance between the TFT array substrate 10 and the counter substrate 20 (inter-substrate gap) to a predetermined value are dispersed.

  A light-shielding frame light-shielding film 53 that defines the frame area of the image display area 10a is provided on the counter substrate 20 side in parallel with the inside of the seal area where the sealing material 52 is disposed. A data line driving circuit 101 and an external circuit connection terminal 102 are provided along one side of the TFT array substrate 10 in a region located outside the sealing region in which the sealing material 52 is disposed in the peripheral region. However, the data line driving circuit 101 may be provided inside the seal region so that the data line driving circuit 101 is covered with the frame light shielding film 53. The scanning line driving circuit 104 and the common wiring driving circuit 110 are provided so as to be covered with the frame light-shielding film 53 inside the seal region along two sides adjacent to the one side.

  In FIG. 2, on the TFT array substrate 10, there is formed a laminated structure in which pixel switching TFTs (Thin Film Transistors), which are driving elements, and wirings such as scanning lines and data lines are formed. Specifically, in the image display area 10a, the common electrode 11, the insulating layer 12, and the pixel electrode 9a are formed in this order on the upper layer of the pixel switching TFT, the scanning line, the data line, and the like. That is, the liquid crystal device 100 according to the present embodiment has a lateral electric field driving method (particularly, FFS (Fringe Field Switching) method) that controls the alignment state of the liquid crystal layer 50 by an electric field generated between the pixel electrode 9a and the common electrode 11. Is adopted. Here, the pixel electrodes 9a are provided in a matrix so as to form each pixel constituting the image display region 10a. On the other hand, in the common electrode 11, the common electrode corresponding to the pixel electrode 9a belonging to one row is divided for each data line arranged for each scanning line arranged for each horizontal line. The common electrode 11 may be divided into a plurality of lines, that is, may be formed corresponding to one or more horizontal pixel electrodes. In the present embodiment, the common electrode 11 and the common wiring COM are integrally formed by the same process. On the other hand, a light shielding film 23 is formed on the surface of the counter substrate 20 facing the TFT array substrate 10. The light shielding film 23 is formed of, for example, a light shielding metal film or the like, and is patterned, for example, in a lattice shape in the image display region 10a on the counter substrate 20. A color filter 8 is formed on the light shielding film 23. The liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several types of nematic liquid crystals are mixed, and takes a predetermined alignment state between a pair of substrates.

  Although not shown here, in addition to the data line driving circuit 101 and the scanning line driving circuit 104, the TFT array substrate 10 is used for inspecting the quality, defects, and the like of the liquid crystal device during manufacturing or at the time of shipment. An inspection circuit, an inspection pattern, or the like may be formed.

(2) Detailed Configuration of Liquid Crystal Device Next, with reference to FIG. 3, an electrical configuration of a main part of the liquid crystal device 100 according to the present embodiment will be described. FIG. 3 is a block diagram conceptually showing the electrical configuration of the main part of the liquid crystal device 100 according to this embodiment.

  In FIG. 3, the liquid crystal device 100 according to the present embodiment includes a scanning line driving circuit 104, a data line driving circuit 101, and a common wiring driving circuit in a peripheral region located around the image display region 10a on the TFT array substrate 10. A drive circuit such as 110 is formed.

  The scanning line driving circuit 104 sequentially supplies scanning signals to the scanning lines Y1 to Yn (where n is an integer of 1 or more). For example, when a high level scanning signal is supplied to a certain scanning line Ya (where a is an integer satisfying 1 ≦ a ≦ n), all TFTs 116 connected to the scanning line Ya are turned on, and this scanning is performed. All the pixel portions 70 corresponding to the line Ya are selected.

  The data line driving circuit 101 sequentially supplies an image signal to the data lines X1 to Xm (where m is an integer equal to or greater than 1), and an image voltage based on the image signal is supplied to the pixel electrode 9a via the TFT 116 in the on state. Write.

  As will be described in detail later, the common line driving circuit 110 is configured to use a first voltage VCOMH or a second voltage VCOML having a lower potential than the first voltage VCOMH (in other words, a predetermined reference potential (for example, an image voltage based on an image signal). A first voltage VCOMH (for example, 5 V) having a positive polarity with respect to the central potential of the image voltage based on the signal) or a second voltage VCOML (for example, 0 V) having a negative polarity with respect to a predetermined reference potential). To COMn. More specifically, the common line drive circuit 110 alternately supplies the first voltage VCOMH and the second voltage VCOML to the common line COMa in the a-row every frame period. For example, when the first voltage VCOMH is supplied to the common wiring COMa in one frame period, the common wiring driving circuit 110 supplies the second voltage VCOML to the common wiring COMa in the next one frame period. On the other hand, when the second voltage VCOML is supplied to the common wiring COMa in one frame period, the common wiring driving circuit 110 supplies the first voltage VCOMH to the common wiring COMa in the next one frame period. Further, the common wiring drive circuit 110 supplies different voltages to the common wiring COMa-1 and the common wiring COMa that are adjacent to each other. In other words, the common line drive circuit 110 supplies the first voltage VCOMH (or the second voltage VCOML) to the common line COMa-1, while the second voltage VCOML (to the common line COMa adjacent to the common line COMa-1). Alternatively, the first voltage VCOMH) is supplied. The configuration and detailed operation of the common wiring drive circuit 110 will be described later in detail (see FIGS. 4 to 7).

  In the present embodiment, a configuration in which one common wiring driving circuit 110 is provided on either the left or right side of the image display area 10a is illustrated. However, the common wiring driving circuit 110 is provided on each of the left and right sides of the image display area 10a. You may comprise so that it may be provided. The two common wiring drive circuits 110 have the same configuration and perform the same operation (the same signal and voltage are input and the same signal and voltage are output to the common wiring COMa at the same timing). For this reason, in the following description, when the “common line driving circuit 110” is simply referred to, each of the two common wiring driving circuits 110 is shown.

  The liquid crystal device 100 according to the present embodiment is further provided with a plurality of pixel units 70 arranged in a matrix in the image display region 10 a occupying the center of the TFT array substrate 10.

  The pixel unit 70 includes a pixel switching TFT 116, a liquid crystal capacitor 118, and a storage capacitor 119.

  The TFT 116 has a source terminal electrically connected to one of the data lines X1 to Xm, a gate terminal electrically connected to one of the scanning lines Y1 to Yn, and a drain terminal electrically connected to the pixel electrode 9a. Has been. The pixel switching TFT 116 is switched between an on state and an off state by a scanning signal supplied from the scanning line driving circuit 104.

  The liquid crystal capacitor 118 includes a pixel electrode 9 a, a common electrode 11, and a liquid crystal positioned between the pixel electrode 9 a and the common electrode 11. The pixel electrode 9a is electrically connected to one of the data lines X1 to Xm through the TFT 116. The common electrode 11 is electrically connected to any one of the common wirings COM1 to COMn. The pixel electrode 9a and the common electrode 11 are both provided on the TFT array substrate 10 as described above. During the operation of the liquid crystal device 100, the pixel electrode 9a having the potential of the image signal supplied from the data lines X1 to Xm and the TFT 116, and the first voltage VCOMH or the second voltage supplied from the common lines COM1 to COMn. A lateral electric field along the substrate surface of the TFT array substrate 10 is generated between the common electrode 11 having a potential of VCOML. The liquid crystal is modulated in accordance with the lateral electric field, that is, by changing the orientation and order of the molecular assembly in accordance with the lateral electric field, thereby enabling gradation display.

  The storage capacitor 119 is added in parallel with the liquid crystal capacitor 118 in order to prevent the held image signal from leaking. One electrode constituting the storage capacitor 119 is electrically connected to the pixel electrode 9 a, and the other electrode is electrically connected to the common electrode 11. In the present embodiment, the common wiring COMa is integrally formed with the common electrode 11 divided for each horizontal line.

  The above liquid crystal device 100 operates as follows.

  First, by supplying a high level scanning signal from the scanning line driving circuit 104 to the scanning line Ya, all the TFTs 116 connected to the scanning line Ya are turned on, and all the pixel units 70 related to the scanning line Ya are turned on. select.

  Further, in synchronization with the selection of the pixel portion 70 related to the scanning line Ya, the positive polarity image signal and the negative polarity image signal from the data line driving circuit 101 to the data lines X1 to Xm and the potentials of the common lines COM1 to COMn. An image signal is alternately supplied every horizontal scanning period. Specifically, if the potential of the common wiring COMa is the first voltage VCOMH, an image signal having a negative polarity with respect to a predetermined reference potential is supplied to the data lines X1 to Xm. On the other hand, if the potential of the common wiring COMa is the second voltage VCOML, a positive image signal with respect to a predetermined reference potential is supplied to the data lines X1 to Xm.

  As a result, image signals are supplied from the data line driving circuit 101 to the pixel units 70 selected by the scanning line driving circuit 104 via the data lines X1 to Xm and the TFT 116, and an image voltage based on this image signal is applied to the pixels. It is written in the electrode 9a. Thereby, a potential difference is generated between the pixel electrode 9a and the common electrode 11, and a driving voltage is applied to the liquid crystal.

  In particular, the liquid crystal device 100 according to the present embodiment can perform partial driving. That is, the liquid crystal device 100 according to the present embodiment performs image display using only a part of the image display area 10a (hereinafter, referred to as “effective display area” as appropriate) and another part of the image display area 10a. In the following (hereinafter referred to as “non-display area”), black display (for example, in a normally black mode) or white display (for example, in a normally white mode) is performed.

  Here, in order to perform partial driving (that is, to perform black display or white display in the non-display area), when scanning the non-display area, at least the common electrode 11 corresponding to the non-display area. It is necessary to supply the same voltage. On the other hand, when scanning the effective display area, it is necessary to supply different voltages to the common wiring COMa-1 and the common wiring COMa adjacent to each other at least in the effective display area. Therefore, the common wiring drive circuit 110 included in the liquid crystal device 100 according to the present embodiment has a configuration described in detail below, and the common wiring COMa-1 and the common wiring COMa that are adjacent to each other while performing partial driving. Are supplied with different voltages.

(3) Specific Configuration and Operation of Common Wiring Drive Circuit Next, a specific configuration and operation of the common wiring drive circuit 110 will be described with reference to FIG. FIG. 4 is a block diagram conceptually showing the configuration of the common wiring drive circuit 110. As shown in FIG.

  As shown in FIG. 4, the common wiring driving circuit 110 includes a latch circuit 111, a control signal output circuit 112 constituting a specific example of the “control circuit” in the present invention, and a specific example of the “connection circuit” in the present invention. The voltage selection circuit 113 which comprises an example is provided.

  Next, the configuration of the latch circuit 111 included in the common wiring driving circuit 110 will be described with reference to FIG. FIG. 5 is a block diagram conceptually showing the configuration of the latch circuit 111 provided in the common wiring driving circuit 110.

  As shown in FIG. 5, the latch circuit 111 includes first latch circuit units 111-1 # 1 and 111-1 #n provided corresponding to the common wiring COM <b> 1 in the first row and the common wiring COMn in the n-th row. And second latch circuit portions 111-2 # 2 to 111-2 # n-1 (ie, the common line COMb) provided corresponding to the common lines COM2 to COMn-1 in the second to n-1th rows. (Where b is an integer satisfying 2 ≦ b ≦ n−1) and the second latch circuit portion 111-2 # b) provided corresponding to the second latch circuit portion 111-2 # b).

  The second latch circuit unit 111-2 # b includes a NOR circuit U11, a first inverter U12, a second inverter U13, a first clocked inverter U14, and a second clocked inverter U15.

  The two input terminals of the NOR circuit U11 have scanning lines at the previous stage of the common wiring line COMb corresponding to the second latch circuit unit 111-2 # b (that is, the previous row and the (b-1) th row), respectively. Yb-1 is electrically connected to the scanning line Yb + 1 at the subsequent stage of the common wiring line COMb corresponding to the second latch circuit unit 111-2 # b (that is, the subsequent row and the (b + 1) th row). .

  The output terminal of the NOR circuit U11 is electrically connected to the input terminal of the first inverter U12, the inverting input control terminal of the first clocked inverter U14, and the non-inverting input terminal of the second clocked inverter U15. . The output terminal of the first inverter U12 is electrically connected to the non-inverting input control terminal of the first clocked inverter U14 and the inverting input terminal of the second clocked inverter U15.

  The polarity signal POL is input to the input terminal of the first clocked inverter U14. The polarity signal POL is a signal for switching the potential level from the high level to the low level or from the low level to the high level every vertical scanning period (for example, one field period or one frame period). The output terminal of the first clocked inverter U14 is electrically connected to the output terminal of the second clocked inverter U15 and the input terminal of the second inverter U13. The output terminal of the second inverter U13 is electrically connected to the input terminal of the second clocked inverter U15.

  The second latch circuit unit 111-2 # b described above operates as follows.

  First, when a high level scanning signal is supplied to at least one of the scanning line Yb-1 and the scanning line Yb + 1, the high level scanning signal is input to the NOR circuit U11. As a result, a low level signal is output from the output terminal of the NOR circuit U11. The low level signal that is the output of the NOR circuit U11 is input to the inverting input control terminal of the first clocked inverter U14. Further, the low level signal that is the output of the NOR circuit U11 is inverted in polarity by the first inverter U12 and converted into a high level signal, and the high level signal is controlled by the non-inverted input control of the first clocked inverter U14. Input to the terminal. Therefore, the first clocked inverter U14 is turned on and outputs an inverted polarity signal / POL that is a signal obtained by inverting the polarity of the polarity signal POL. The inverted polarity signal / POL output from the first clocked inverter U14 is inverted again by the second inverter U13 to return to the polarity signal POL, and is output as the latch signal LATb.

  On the other hand, when a low level scanning signal is supplied to both the scanning line Yb-1 and the scanning line Yb + 1, the low level scanning signal is input to the NOR circuit U11. As a result, a high level signal is output from the output terminal of the NOR circuit U11. The high level signal that is the output of the NOR circuit U11 is input to the non-inverting input control terminal of the second clocked inverter U15. The high-level signal that is the output of the NOR circuit U11 is converted into a low-level signal by inverting the polarity by the first inverter U12, and the low-level signal is converted to the inverting input control terminal of the second clocked inverter U15. Is input. For this reason, the second clocked inverter U15 is turned on and outputs a signal obtained by inverting the polarity of the polarity signal POL output from the second inverter U13 (that is, the inverted polarity signal / POL). The inverted polarity signal / POL output from the second clocked inverter U15 is inverted again by the second inverter U13 to return to the polarity signal POL, and the polarity signal POL is output as the latch signal LATb.

  That is, the second latch circuit unit 111-2 # b takes in the polarity signal POL when a high level scanning signal is supplied to at least one of the scanning line Yb-1 and the scanning line Yb + 1, and the taken polarity signal. POL is output as the latch signal LATb. Further, when a low level scanning signal is supplied to both the scanning line Yb-1 and the scanning line Yb + 1, the second latch circuit unit 111-2 # b outputs the latch signal LATb to the second inverter U13 and the second clock signal. The output is held while being held by the inverter U15. That is, the second latch circuit unit 111-2 # b receives the polarity signal POL acquired at the time when the high-level scanning signal is input to at least one of the scanning line Yb-1 and the scanning line Yb + 1, for at least one vertical scanning period. Can continue to output during

  Next, the first latch circuit units 111-1 # 1 and 111-1 # n will be described. Compared with the second latch circuit unit 111-2 # b, the first latch circuit units 111-1 # 1 and 111-1 # n replace the NOR circuit U11 with the low potential power supply VLL of the first inverter U12. The difference is that the input terminal, the inverting input control terminal of the first clocked inverter U14, and the non-inverting input terminal of the second clocked inverter U15 are electrically connected. The operations of the first latch circuit units 111-1 # 1 and 111-1 # n are the same as the operations of the second latch circuit unit 111-2 # b. That is, in the first latch circuit units 111-1 # 1 and 111-1 # n, the first clocked inverter U14 is always turned on, and the captured polarity signal POL can be continuously output.

  Next, the configuration of the control signal output circuit 112 included in the common wiring drive circuit 110 will be described with reference to FIG. FIG. 6 is a block diagram conceptually showing the structure of the control signal output circuit 112 provided in the common wiring drive circuit 110.

  As shown in FIG. 6, the control signal output circuit 112 includes odd-numbered lines of common wiring COMi (where i is an odd number that satisfies 1 ≦ i ≦ n, specifically 1, 3,... K. −1,..., N−1) and the first control signal output circuit unit 112-1 # i provided in correspondence with the even-numbered row common wiring COMj (where j is 1 ≦ i ≦ n). The second control signal output circuit unit 112-2 # j provided corresponding to 2, 4,..., K,. . FIG. 6 illustrates an example in which k is an even number.

  The first control signal output circuit unit 112-1 # i includes a NAND circuit U21 and an inverter U22. The latch signal LATi and the partial drive signal PSL are input to the two input terminals of the NAND circuit U21, respectively. The output terminal of the NAND circuit U21 is electrically connected to the input terminal of the inverter U22.

  The partial drive signal PSL constitutes one specific example of the “reference signal” in the present invention, and is a signal indicating whether or not partial drive is performed. Specifically, the partial drive signal PSL is, for example, a signal having a low level signal level while scanning the non-display area, and a high level signal level while scanning the effective display area. is there. For example, when image display is performed using only the effective display areas corresponding to the scanning lines Y1 to Y30 and black display or white display is performed for the non-display areas corresponding to the scanning lines Y31 to Yn, partial driving is performed. The signal PSL has a low level signal level during the period when the high level scanning signal is supplied to the scanning lines Y1 to Y30, while the high level scanning signal is supplied during the period when the high level scanning signal is supplied from the scanning lines Y31 to Yn. The signal has a signal level of.

  The first control signal output circuit unit 112-1 # i described above operates as follows.

  First, when the partial drive signal PSL is a high level signal, the NAND circuit U21 outputs an inverted latch signal / LATi (that is, an inverted polarity signal / POL) that is a signal obtained by inverting the polarity of the latch signal LATi. . The polarity of the inverted latch signal / LATi output from the NAND circuit U21 is inverted in the inverter U22. As a result, the latch signal LATi (that is, the polarity signal POL) is output from the inverter U22 as the control signal Si. On the other hand, when the partial drive signal PSL is a low level signal, the NAND circuit U21 does not depend on whether the latch signal LATi is a high level signal or a low level signal, and the high level. The signal is output. The polarity of the high level signal output from the NAND circuit U21 is inverted in the inverter U22. As a result, a low level signal is output as a control signal Si from the inverter U22.

  Subsequently, the second control signal output circuit unit 112-2 # j includes an inverter U23 and a NOR circuit U24. The latch signal LATj is input to the input terminal of the inverter U23. Further, the output of the inverter U22 and the partial drive signal PSL are input to the two input terminals of the NOR circuit U24, respectively.

  The second control signal output circuit unit 112-2 # j described above operates as follows.

  First, when the partial drive signal PSL is a high level signal, the NOR circuit U21 controls the inverted latch signal / LATi (that is, the inverted polarity signal / POL), which is a signal obtained by inverting the polarity of the latch signal LATi. Output as Sj. On the other hand, when the partial drive signal PSL is a low level signal, the NOR circuit U23 does not depend on whether the latch signal LATi is a high level signal or a low level signal. Is output as the control signal Sj.

  Next, the configuration of the voltage selection circuit 113 provided in the common wiring drive circuit 110 will be described with reference to FIG. FIG. 7 is a block diagram conceptually showing the configuration of the voltage selection circuit 113 provided in the common wiring drive circuit 110.

  As shown in FIG. 7, the voltage selection circuit 113 includes a voltage selection circuit section 113-1 # a (a is an integer satisfying 1 ≦ a ≦ n) provided corresponding to the common lines COM1 to COMn. Contains.

  The voltage selection circuit unit 113-1 # a includes an inverter U31, a TFT U32, and a TFT U33. The input terminal of the inverter U31 has a first control signal output unit 112-1 # a (provided that a is an odd number) or a second control signal output unit 112-2 # a (provided that a is an even number). ) Is output from the control signal Sa. The output terminal of the inverter U31 is electrically connected to each of the non-inverting input gate terminal of the TFT U32 and the inverting input gate terminal of the TFT U33. A first voltage supply line ZH to which a first voltage VCOMH is supplied is electrically connected to the source terminal of the TFT U33. Further, the second voltage supply line ZL to which the second voltage VCOML is supplied is electrically connected to the source terminal of the TFT U32. In addition, each of the drain terminal of the TFT U32 and the drain terminal of the TFT U33 is electrically connected to the common wiring COMa.

  The voltage selection circuit unit 113-1 # a described above operates as follows.

  First, the latch signal LATa is output as the control signal Sa from the first control signal output circuit unit 112-1 # a (provided that a is an odd number) or the second control signal output circuit unit 112-2 #. A case where the inverted latch signal / LATa is output as the control signal Sa from a (where a is an even number) will be described. That is, when the partial drive signal PSL is a high level signal and the polarity signal POL is output as the control signal Sa from the first control signal output circuit unit 112-1 # a (provided that a is an odd number). Alternatively, a case where the inverted polarity signal / POL is output as the control signal Sa from the second control signal output circuit unit 112-2 # a (provided that a is an even number) will be described. In the following, in order to make the explanation clearer, a case where a is an odd number (that is, a = i) and a case where a is an even number (that is, a = j). Each will be described.

  First, when a is an odd number, the polarity signal POL is output as the control signal Sa from the first control signal output circuit unit 112-1 # a. The polarity signal POL is inverted by the inverter U31 and then input to the non-inverting input gate terminal of the TFT U32 and the inverting input gate terminal of the TFT U33. For this reason, when the polarity of the polarity signal POL is at a low level, the TFT U32 is turned on and the TFT U33 is turned off. As a result, the second voltage supply line ZL that supplies the second voltage VCOML and the scanning line COMa are electrically connected via the TFT U32. On the other hand, when the polarity of the polarity signal POL is high, the TFT U32 is turned off and the TFT U33 is turned on. As a result, the first voltage supply line ZH that supplies the first voltage VCOMH and the scanning line COMa are electrically connected via the TFT U33.

  On the other hand, when a is an even number, the inverted control signal / POL is output as the control signal Sa from the second control signal output circuit unit 112-2 # a. The inverted polarity signal / POL is inverted by the inverter U31 and then input to each of the non-inverted input gate terminal of the TFT U32 and the inverted input gate terminal of the TFT U33. For this reason, when the polarity of the polarity signal POL is low level, the TFT U32 is turned off and the TFT U33 is turned on. As a result, the first voltage supply line ZH that supplies the first voltage VCOMH and the scanning line COMa are electrically connected via the TFT U33. On the other hand, when the polarity of the polarity signal POL is high, the TFT U32 is turned on and the TFT U33 is turned off. As a result, the second voltage supply line ZL that supplies the second voltage VCOML and the scanning line COMa are electrically connected via the TFT U32.

  Thus, when the partial drive signal PSL is a high level signal (that is, when scanning is performed on the effective display area), the common wiring COMa-1 and the common wiring COMa that are adjacent to each other are mutually connected. Different voltages are supplied. In this case, the data signals corresponding to the image to be displayed are supplied from the data line driving circuit 101 to the data lines X1 to Xm. Therefore, a normal image display operation is performed in the effective display area.

  Subsequently, whether the latch signal LATi is a high level signal or a low level signal from the first control signal output circuit unit 112-1 # a or the second control signal output circuit unit 112-2 # a. A case where a low-level signal is output as the control signal Sa without depending on it will be described. That is, a case where the partial drive signal PSL is a low level signal will be described.

  First, when a is an odd number, a low level signal is output as the control signal Sa from the first control signal output circuit unit 112-1 # a. The low level signal is inverted by the inverter U31 and then input to the non-inverting input gate terminal of the TFT U32 and the inverting input gate terminal of the TFT U33. For this reason, the TFT U32 is turned on and the TFTU33 is turned off. As a result, the second voltage supply line ZL that supplies the second voltage VCOML and the scanning line COMa are electrically connected via the TFT U32.

  On the other hand, when a is an even number, the second control signal output circuit unit 112-2 # a outputs a low level signal as the control signal Sa. The low level signal is inverted by the inverter U31 and then input to the non-inverting input gate terminal of the TFT U32 and the inverting input gate terminal of the TFT U33. For this reason, the TFT U32 is turned on and the TFTU33 is turned off. As a result, the second voltage supply line ZL that supplies the second voltage VCOML and the scanning line COMa are electrically connected via the TFT U32.

  As described above, when the partial drive signal PSL is a low level signal (that is, when scanning is performed on the non-display area), the second voltage is applied to all the common lines COM corresponding to the non-display area. VCOML is supplied. In this case, the second voltage VCOML is supplied from the data line driving circuit 101 to the data lines X1 to Xm. Accordingly, black display or white display is performed in the non-display area.

  Here, the operation of the common wiring drive circuit 110 that performs the above operation will be described in more detail with reference to FIG. FIG. 8 is a timing chart showing the operation of the common wiring drive circuit 110. In FIG. 8, black display or white display is performed on the non-display areas corresponding to the scanning lines Y1 to Y29 and Y130 to Yn, and only the effective display area corresponding to the scanning lines Y30 to Y129 is used. An example of performing display will be described. An example in which the scanning direction is the forward direction (that is, an example in which scanning is sequentially performed from the scanning lines Y1 to Yn) will be described.

  As shown in FIG. 8, it is assumed that the polarity signal POL is inverted from a low level to a high level at time t1. Since the polarity signal POL is switched to the high level, the second line VCOML is supplied (or should be supplied) in the previous frame (frame # 1). ,..., N−1), the first voltage VCOMH is supplied in the next frame (frame # 2). Similarly, the common line COMj (where j = 2, 4,..., N) of the even-numbered row to which the first voltage VCOMH was supplied (or to be supplied) in the previous frame has the following The second voltage VCOML is supplied in the frame.

  Here, since the display area corresponding to the scanning lines Y1 to Y29 is a non-display area, the partial drive signal PSL is at the low level while the high level scanning signal is supplied to each of the scanning lines Y1 to Y29. Signal. Accordingly, the odd-numbered common wiring COMi that is electrically connected to the second voltage supply line ZL in the previous frame (frame # 1) remains in the state of being electrically connected to the second voltage supply line ZL as it is. Will continue. For the even-numbered common wiring COMi electrically connected to the first voltage supply line ZH in the previous frame (frame # 1), at the timing when the partial drive signal PSL is switched from the high level to the low level. The state is switched from the state electrically connected to the first voltage supply line ZH to the state electrically connected to the second voltage supply line ZL.

  Thereafter, after the scanning with respect to the scanning lines Y1 to Y29 is completed, the partial drive signal PSL becomes a high level signal. Specifically, the partial drive signal PSL is a high level signal while a high level scan signal is supplied to each of the scan lines Y30 to Y129. Accordingly, for the odd-numbered common wiring COMi (particularly, i is 31, 33,..., 129), when the high level scanning signal is supplied to the scanning line Yi-1 in the preceding row, The state is switched from the state electrically connected to the two voltage supply lines ZL to the state electrically connected to the first voltage supply line ZH. In addition, since the common lines COMj (especially j = 30, 32, 34,..., 128) in even rows are already electrically connected to the second voltage supply line ZL, the second voltage supply is performed as it is. The state of being electrically connected to the line ZL is maintained.

  Thereafter, after the scanning of the scanning lines Y30 to Y129 is completed, the partial drive signal PSL becomes a low level signal. Specifically, the partial drive signal PSL is a low level signal while a high level scan signal is supplied to each of the scan lines Y130 to Yn. Therefore, the odd-row common wiring COMi (particularly, i is 1, 3,..., 29, 131, 133,...) Is already electrically connected to the second voltage supply line ZL. Therefore, the state of being electrically connected to the second voltage supply line ZL as it is is continued. Further, the odd-numbered common wiring COMi (particularly, i is 31, 33,..., 129) is electrically connected to the first voltage supply line ZH at the timing when the partial drive signal PSL is switched from the high level to the low level. The state is switched from the state of being electrically connected to the state of being electrically connected to the second voltage supply line ZL. In addition, since the even-numbered common wiring COMj is already electrically connected to the second voltage supply line ZL, the state of being electrically connected to the second voltage supply line ZL is maintained as it is.

  As described above, according to the liquid crystal device 100 according to the present embodiment, while scanning the effective display area, while supplying different voltages to the two common lines COM adjacent to each other, the non-display area is also supplied. During the scanning, all the potentials of the common wiring COM can be set to the second potential VCOML. That is, in the effective display area, different voltages are supplied to the common electrodes 11 in two adjacent rows, while in the non-display area, all the potentials of the common electrode 11 are set to the second potential VCOML. be able to. Accordingly, black display (in the normally black mode) or white display (in the normally white mode) can be performed on the non-display area portion while performing normal image display using the effective display area. Thus, part of the image display area 10a can be set as a non-display area, so that the power consumption of the liquid crystal device 100 can be reduced.

  In addition, according to the liquid crystal device 100 according to the present embodiment, the first voltage source that supplies the first voltage VCOMH is connected to the first voltage supply line ZH and the second voltage VCOML for supplying the second voltage VCOML. If the voltage source is connected to the second voltage supply line ZL, all the potentials of the common line COM corresponding to the non-display area can be set to the second voltage VCOML. In other words, in order to make all the potentials of the common wiring line COM corresponding to the non-display area the same potential, a voltage source for supplying the second voltage VCOML to the first voltage supply line ZH is newly provided. It is not necessary to connect a new voltage source to the first voltage supply line ZH. Similarly, a voltage source for supplying the first voltage VCOMH to the second voltage supply line ZL is newly provided in order to make all the potentials of the common wiring line COM corresponding to the non-display area the same potential. It is not necessary to connect a new voltage source to the second voltage supply line ZL. That is, it is not necessary to provide a new voltage source in order to perform partial driving. As a result, partial driving or the like is adopted in the liquid crystal device 100 that employs the COM divided driving without significantly increasing the power consumption of the liquid crystal device 100 (particularly, the power consumption of the common wiring driving circuit 110 including the voltage source). Can do. Furthermore, partial driving or the like is employed in the liquid crystal device 100 that employs COM division driving without significantly increasing the manufacturing cost of the liquid crystal device 100 (particularly, the manufacturing cost of the common wiring driving circuit 110 including the voltage source). be able to.

  In the above-described embodiment, the latch signal LATi (that is, the polarity signal POL) or the low level signal is output as the control signal Si from the first control signal output circuit unit 112-1 # i in the odd rows, and the even rows. An example of the control signal output circuit 112 in which the inverted latch signal / LATj (that is, the inverted polarity signal / POL) or the low level signal is output as the control signal Sj from the second control signal output circuit unit 112-2 # j of FIG. is doing. However, it goes without saying that the control signal output circuit 112 is not limited to this. For example, when the partial drive signal PSL is a high level signal, each of the odd-numbered first control signal output circuit unit 112-1 # i and the even-numbered second control signal output circuit unit 112-2 # j, respectively. Output signals whose polarities are inverted from each other (for example, the polarity signal POL and the inverted polarity signal / POL), and the partial drive signal PSL is a low level signal, the first control signal output circuit unit in the odd-numbered rows A fixed signal having a fixed signal level may be output from both the 112-1 # i and the second control signal output circuit unit 112-2 # j in even rows. Even if comprised in this way, the effect mentioned above can be enjoyed suitably. However, as shown in FIG. 6, each control signal output circuit section in the control signal output circuit 112 has a different configuration for odd rows and even rows (that is, first control signal output circuit portions 112-1 # for odd rows). i and even-numbered second control signal output circuit section 112-2 # j), the voltage selection circuit sections 113-1 # 1 to 113-1 # in the voltage selection circuit 113 as shown in FIG. It is preferable that n has a common configuration.

  On the other hand, the voltage selection circuit units 113-1 # 1 to 113- # n in the voltage selection circuit 113 may have different configurations in the odd and even rows. An example of the voltage selection circuit 113 having such a configuration will be described with reference to FIG. FIG. 9 is a block diagram conceptually showing the structure of the voltage selection circuit 113a according to the modification.

  For example, as illustrated in FIG. 9, the voltage selection circuit 113a according to the modification is replaced with an inverter U31 in place of the voltage selection circuit unit 113-1 # i in the odd-numbered row as compared with the voltage selection circuit 113 illustrated in FIG. Is different in that the voltage selection circuit unit 113a-1 # i is provided in the odd-numbered row from which is removed. Further, in the voltage selection circuit 113a according to the modification, the inverter U31 is removed instead of the voltage selection circuit unit 113-1 # j in the even-numbered row, and the source of the TFT U33 is compared with the voltage selection circuit 113 shown in FIG. The second voltage supply line ZL is electrically connected to the terminal, and the source terminal of the TFT U32 includes an even-numbered voltage selection circuit unit 113a-2 # j to which the first voltage supply line ZH is electrically connected. It is different in point.

  As described above, when the voltage selection circuit units 113-1 # 1 to 113- # n in the voltage selection circuit 113 have different configurations in the odd rows and the even rows, the control signals in the control signal output circuit 112 are displayed. The output circuit section preferably has a common configuration in all rows. In the control signal output circuit 112, when the partial drive signal PSL is a high level signal, the odd-numbered first control signal output circuit unit 112-1 # i and the even-numbered second control signal output circuit. When the signals having the same polarity (that is, one of the polarity signal POL and the inverted polarity signal / POL) are output from each of the units 112-2 # j, and the partial drive signal PSL is a low level signal, The fixed signal having the fixed signal level and the polarity is inverted from each of the first control signal output circuit unit 112-1 # i in the odd row and the second control signal output circuit unit 112-2 # j in the even row. It is preferably configured to be output. An example of the control signal output circuit 112 having such a configuration will be described with reference to FIG. FIG. 10 is a block diagram conceptually showing the structure of the control signal output circuit 112a according to the modification.

  As shown in FIG. 10, the control signal output circuit 112a according to the modified example is replaced with the first control signal output circuit unit 112-1 # i in the odd-numbered row as compared with the control signal output circuit 112 shown in FIG. The difference is that the inverter U22 includes the first control signal output circuit unit 112a-1 # i in the odd-numbered rows from which the inverter U22 is removed. Note that the second control signal output circuit unit 112-2 # j in the even-numbered rows is not changed.

  When the partial drive signal PSL is a high level signal, the first control signal output circuit unit 112a-1 # i outputs the inverted polarity signal / POL as the control signal Si, while the partial drive signal PSL. Is a low level signal, a high level signal is output as the control signal Si. Further, as described above, when the partial drive signal PSL is a high level signal, the second control signal output circuit unit 112-2 # j outputs the inverted polarity signal / POL as the control signal Sj. On the other hand, when the partial drive signal PSL is a low level signal, the low level signal is output as the control signal Sj.

  In this case, the voltage selection circuit 113a according to the modification operates as follows.

  First, the case where the partial drive signal PSL is a high level signal will be described. In this case, the inverted polarity signal / POL is input to each of the non-inverting input gate terminal of the TFT U32 and the inverting input gate terminal of the TFT U33 in the voltage selection circuit units 113a-1 # i in the odd rows. For this reason, when the polarity of the polarity signal POL is at a low level, the TFT U32 is turned on and the TFT U33 is turned off. As a result, the second voltage supply line ZL that supplies the second voltage VCOML and the scanning line COMi are electrically connected via the TFT U32. On the other hand, when the polarity of the polarity signal POL is high, the TFT U32 is turned off and the TFT U33 is turned on. As a result, the first voltage supply line ZH that supplies the first voltage VCOMH and the scanning line COMi are electrically connected via the TFT U33. In the even-numbered voltage selection circuit portions 113a-2 # i, the inverted polarity signal / POL is input to each of the non-inverting input gate terminal of the TFT U32 and the inverting input gate terminal of the TFT U33. For this reason, when the polarity of the polarity signal POL is at a low level, the TFT U32 is turned on and the TFT U33 is turned off. As a result, the first voltage supply line ZH that supplies the first voltage VCOMH and the scanning line COMj are electrically connected via the TFT U32. On the other hand, when the polarity of the polarity signal POL is high, the TFT U32 is turned off and the TFT U33 is turned on. As a result, the second voltage supply line ZL that supplies the second voltage VCOML and the scanning line COMj are electrically connected via the TFT U33.

  Thus, when the partial drive signal PSL is a high level signal (that is, when scanning is performed on the effective display area), the common wiring COMa-1 and the common wiring COMa that are adjacent to each other are mutually connected. Different voltages are supplied. In this case, the data signals corresponding to the image to be displayed are supplied from the data line driving circuit 101 to the data lines X1 to Xm. Therefore, a normal image display operation is performed in the effective display area.

  Next, the case where the partial drive signal PSL is a low level signal will be described. In this case, high-level signals are input to the non-inverting input gate terminal of the TFT U32 and the inverting input gate terminal of the TFT U33 in the voltage selection circuit units 113a-1 # i in the odd-numbered rows. For this reason, the TFT U32 is turned on and the TFTU33 is turned off. As a result, the second voltage supply line ZL that supplies the second voltage VCOML and the scanning line COMi are electrically connected via the TFT U32. In the even-numbered voltage selection circuit portions 113a-2 # j, a low level signal is input to each of the non-inverting input gate terminal of the TFT U32 and the inverting input gate terminal of the TFT U33. Therefore, the TFT U32 is turned off and the TFT U33 is turned on. As a result, the second voltage supply line ZL that supplies the second voltage VCOML and the scanning line COMj are electrically connected via the TFT U33.

  As described above, when the partial drive signal PSL is a low level signal (that is, when scanning is performed on the non-display area), the second voltage is applied to all the common lines COM corresponding to the non-display area. VCOML is supplied. In this case, the second voltage VCOML is supplied from the data line driving circuit 101 to the data lines X1 to Xm. Accordingly, black display or white display is performed in the non-display area.

  Therefore, even if it comprises as shown in FIG.9 and FIG.10, the effect mentioned above can be enjoyed suitably.

  In the above description, the pixel electrode 9a and the common electrode 11 are provided on different layers while being provided on the TFT substrate 10, and the pixel electrode 9a and the common electrode 11 sandwich the insulating layer 12 therebetween. The liquid crystal device 100 adopting the FFS method having an opening in the pixel electrode 9a on the liquid crystal layer 50 side has been described, but the common electrode 11 having the opening is provided on the liquid crystal layer 50 side. Also good. Needless to say, the liquid crystal device adopting the IPS method in which the pixel electrode 9a and the common electrode 11 are provided in the same layer can also enjoy the various effects described above by adopting the above-described configuration. Further, not only a liquid crystal device adopting a horizontal electric field driving method, but also adopting a vertical electric field driving method such as a TN (twisted nematic) method, an ECB (birefringence field effect) method, a VA (vertical alignment) method, or the like. Also in the liquid crystal device, by adopting the above-described configuration, the various effects described above can be enjoyed accordingly.

(4) Electronic Device Next, an example of an electronic device including the liquid crystal device 100 described above will be described with reference to FIGS. 11 and 12.

  FIG. 11 is a perspective view of a mobile personal computer to which the liquid crystal device 100 described above is applied. In FIG. 11, a computer 1200 includes a main body 1204 provided with a keyboard 1202 and a liquid crystal display unit 1206 including the liquid crystal device 100 described above. The liquid crystal display unit 1206 is configured by adding a backlight to the back surface of the liquid crystal device 100.

  Next, an example in which the above-described liquid crystal device 100 is applied to a mobile phone will be described. FIG. 12 is a perspective view of a mobile phone which is an example of an electronic apparatus. In FIG. 12, a mobile phone 1300 includes a liquid crystal device 1005 that adopts a transflective display format and has the same configuration as the liquid crystal device 100 described above, together with a plurality of operation buttons 1302.

  Since these electronic devices also include the liquid crystal device 100 described above, the various effects described above can be suitably enjoyed.

  In addition to the electronic apparatus described with reference to FIGS. 11 and 12, a liquid crystal television, a viewfinder type or a monitor direct view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, a word processor, a workstation And a direct-view display device including a video phone, a POS terminal, and a touch panel, and a projection display device such as a liquid crystal projector. Needless to say, the present invention can be applied to these various electronic devices.

  The present invention is not limited to the above-described embodiments, and various modifications can be made as appropriate without departing from the spirit or concept of the invention that can be read from the claims and the entire specification. Devices and electronic devices are also included in the technical scope of the present invention.

It is a top view which shows the structure of the liquid crystal device which concerns on embodiment. It is H-H 'sectional drawing of FIG. It is a block diagram which shows notionally the electrical structure of the principal part of the liquid crystal device which concerns on this embodiment. It is a block diagram which shows notionally the structure of a common wiring drive circuit. It is a block diagram which shows notionally the structure of the latch circuit with which a common wiring drive circuit is provided. It is a block diagram which shows notionally the structure of the control signal output circuit with which a common wiring drive circuit is provided. It is a block diagram which shows notionally the structure of the voltage selection circuit with which a common wiring drive circuit is provided. It is a timing chart which shows operation | movement of a common wiring drive circuit. It is a block diagram which shows notionally the structure of the voltage selection circuit which concerns on a modification. It is a block diagram which shows notionally the structure of the control signal output circuit which concerns on a modification. It is a perspective view of a mobile personal computer to which a liquid crystal device is applied. 1 is a perspective view of a mobile phone to which a liquid crystal device is applied.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Liquid crystal device, 11 ... Common electrode, 101 ... Data line drive circuit, 104 ... Scanning line drive circuit, 110 ... Common wiring drive circuit, 111 ... Latch circuit, 112 ... Control signal output circuit, 113 ... Voltage selection circuit, Y1 ~ Yn ... scanning line, COM1-COMn ... common wiring, ZH ... first voltage supply line, ZL ... second voltage supply line

Claims (10)

Applied between the plurality of pixel electrodes constituting the display region, the plurality of common electrodes formed corresponding to the pixel electrodes for each of the one or more horizontal lines, and the plurality of pixel electrodes and the plurality of common electrodes. An electro-optic device comprising an electro-optic material driven in accordance with an electric field,
The first voltage is applied to two common electrodes adjacent to each other among the plurality of common electrodes such that a first voltage and a second voltage different from the first voltage are alternately supplied for each predetermined period. A connection circuit for alternately connecting a first voltage supply line to be supplied or a second voltage supply line to which the second voltage is supplied to each of the plurality of common electrodes;
Only one of the first voltage supply line and the second voltage supply line is fixedly connected to the plurality of common electrodes corresponding to a part of the display area of the display area. And a control circuit for controlling the connection circuit. A latch circuit that holds a polarity signal for selecting the first voltage or the second voltage;
The control circuit is configured to detect the polarity signal held by the latch circuit and the reference signal indicating whether the partial display area portion is scanned or not based on each of the display area portions. The connection circuit is controlled so that only one of the first voltage supply line and the second voltage supply line is fixedly connected to the corresponding common electrode. The electro-optical device described. The control circuit includes:
A first signal that is provided so as to correspond to either the even line or the odd line and outputs the fixed signal having the polarity signal or the fixed signal level held by the latch circuit according to the signal level of the reference signal. A control circuit unit;
A first signal is provided corresponding to the other of the even line and the odd line, and outputs an inverted signal of the polarity signal or the fixed signal held by the latch circuit according to the signal level of the reference signal. The electro-optical device according to claim 2, further comprising: 2 control circuit units. The reference signal becomes a low level at the timing when the partial display area portion is scanned, and the other display area portion other than the partial display area portion of the display area is scanned. High level at the timing,
The first control circuit unit includes a negative logical product circuit that outputs a negative logical product signal of the polarity signal held by the latch circuit and the reference signal, and an inverting circuit that inverts the polarity of the negative logical product signal. ,
The second control circuit unit includes a negative OR circuit that outputs a negative OR signal of the polarity signal held by the latch circuit and an inverted signal of the reference signal. Electro-optic device. The reference signal becomes a low level at the timing when the partial display area portion is scanned, and the other display area portion other than the partial display area portion of the display area is scanned. High level at the timing,
The first control circuit unit outputs a negative OR circuit that outputs a negative logical sum signal of the polarity signal held by the latch circuit and an inverted signal of the reference signal, and an inversion that inverts the polarity of the negative logical sum signal. With a circuit,
4. The electro-optic according to claim 3, wherein the second control circuit unit includes a negative logical product circuit that outputs a negative logical product signal of the polarity signal held by the latch circuit and the reference signal. apparatus.   The control circuit, when performing partial driving to stop display in the part of the display area part, the first voltage supply line and the second voltage to the common electrode corresponding to the part of the display area part. The electro-optical device according to claim 1, wherein the connection circuit is controlled so that only one of the voltage supply lines is fixedly connected.   The control circuit may: (i) during the period of scanning in the partial display region portion, the first voltage supply line and the second voltage supply to the common electrode corresponding to the partial display region portion. Controlling the connection circuit so that only one of the lines is fixedly connected, and (ii) performing a scan in a display area other than the partial display area of the display area The control circuit controls the connection circuit so that the first voltage supply line or the second voltage supply line is alternately connected to a common electrode corresponding to the other display region portion. Item 7. The electro-optical device according to any one of Items 1 to 6. The electro-optical device includes a first substrate on which each of the plurality of pixel electrodes and the plurality of common electrodes is formed, and a second substrate disposed so as to face the first substrate,
The electro-optical device according to claim 1, wherein the electro-optical material is sandwiched between the first substrate and the second substrate.   The electro-optical device according to claim 8, wherein the control circuit and the connection circuit are formed on the first substrate.   An electronic apparatus comprising the electro-optical device according to claim 1.

Images