JP2009134063A - Driver, electrooptical device and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a driver which permits further reduction of power consumption with respect to the driver of liquid crystal device or the like. <P>SOLUTION: The driver (110) comprises: supply circuits (111, 112) which respectively supply a first voltage (VCOMH) and a second voltage (VCOML) to a plurality of common electrodes such that the first voltage and the second voltage are respectively supplied to two common electrodes (11, Zk-1, Zk) adjoining each other among a plurality of common electrodes (11, Z1 to Zn) according to pixel electrodes every one or more horizontal lines; switching circuits (111, 112) which perform switching operation for switching a voltage supplied to one common electrode from the first voltage to the second voltage or from the second voltage to the first voltage every prescribed period and, at the same time, perform the switching operation for the plurality of common electrodes in the order; and a control circuit (113) which electrically connects an accumulated capacity element (130) having an electrostatic capacity larger than the electrostatic capacity of a common line corresponding to one common electrode before the voltages switched by the switching circuits are supplied to the one common electrode, and the one common electrode to each other. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a technical field of a driving device for driving an electro-optical device such as a liquid crystal device, an electro-optical device including such a driving device, and an electronic apparatus including such an electro-optical device.

  An example of this type of electro-optical device is a liquid crystal device in which a liquid crystal, which is an example of an electro-optical material, is sandwiched between a pair of element substrates and a counter substrate. In the pixel region where a plurality of pixels are arranged on the element substrate, a pixel portion including a pixel electrode corresponding to the intersection of the scanning line and the data line is formed, so that the plurality of pixel portions are planar in a matrix shape. Arranged. Each pixel unit includes, for example, a thin film transistor (hereinafter referred to as “TFT” as appropriate) as a pixel switching element. When the electro-optical device is driven, when a pixel switching element is turned on by supplying a scanning signal from the scanning line in each pixel unit, an image signal is supplied from the data line to the pixel electrode via the pixel switching element. . Further, typically, a common electrode (or a counter electrode) is formed in a solid shape in common with the plurality of pixel portions in almost the entire pixel region corresponding to the plurality of pixel electrodes. When the liquid crystal device is driven, an applied voltage based on a potential difference between the pixel electrode and the common electrode is applied to the liquid crystal. As a result, the orientation and order of the liquid crystals are controlled, and image display is possible.

  In such a liquid crystal device, in recent years, in order to realize low power consumption of the liquid crystal device, the common electrode is divided into one horizontal line (one row) (for example, divided along a direction parallel to the scanning line). Voltage of a certain potential level (for example, relatively high level) is supplied to the common electrode of the same row, and voltages of different potential levels (for example, relatively low level) are common to adjacent rows. A driving method has been developed in which the potential level of such a voltage is inverted by one row every horizontal scanning period while being supplied to the electrodes (see Patent Document 1). As a result, the power consumption is lower than that of a driving method in which the potential level of all the common electrodes is inverted at once in each horizontal scanning period while supplying the voltage of the same potential level to all the common electrodes. Can be achieved.

Japanese Patent Application No. 2006-261101

  However, in order to apply the above-described driving method in, for example, an FFS (Fringe field Switching) type liquid crystal device, the potential levels of two types of voltages alternately supplied to the common electrode are supplied to the data lines, respectively. It needs to be higher than the high level of the image signal or lower than the low level. As a result, the amplitude of the potential supplied to the common electrode (in other words, the potential level range) is increased. For this reason, the technical problem that the drive method mentioned above does not necessarily contribute to the reduction of power consumption has arisen. Of course, in other types of liquid crystal devices, it cannot be denied that similar technical problems may occur, although to a different extent.

  The present invention has been made in view of, for example, the conventional problems described above. For example, a driving device that realizes further reduction in power consumption, an electro-optical device including such a driving device, and such a driving device. It is an object to provide an electronic device including the above.

(Driver)
The driving device of the present invention includes a plurality of pixel electrodes, a plurality of common electrodes formed corresponding to the pixel electrodes for each of the one or more horizontal lines, and the plurality of pixel electrodes and the plurality of common electrodes. A driving device for driving an electro-optic device comprising an electro-optic material driven in accordance with an applied electric field, wherein two common electrodes adjacent to each other among the plurality of common electrodes have a first voltage and A supply circuit for supplying the first voltage and the second voltage to the plurality of common electrodes, respectively, so that a second voltage different from the first voltage is supplied; and the plurality of common electrodes at predetermined intervals. A switching operation for switching the voltage supplied to one common electrode from the first voltage to the second voltage or from the second voltage to the first voltage is performed. A switching circuit for sequentially performing common electrodes Before the voltage switched by the switching circuit is supplied to the one common electrode, the storage has a capacitance larger than the capacitance of the common line corresponding to the one common electrode among the plurality of common lines. And a control circuit that electrically connects the capacitive element and the one common electrode to each other.

  According to the driving device of the present invention, for example, the electro-optical device can be driven by supplying a voltage to the common electrode provided in the electro-optical device such as a liquid crystal device via the common line. The electro-optical device to be driven by the driving device according to the present invention includes, for example, a plurality of pixel electrodes provided so as to correspond to intersection positions of a data line to which an image signal is supplied and a scanning line to which a scanning signal is supplied. And a plurality of common electrodes provided for each of one or more horizontal lines (in other words, one for each scanning line or for each of two or more scanning lines). In other words, in the present invention, the common electrode that is normally formed in a solid shape is one horizontal line (for example, along a scanning line) or two or more horizontal lines (for example, along two or more scanning lines). It is divided electrically. Then, for each horizontal line, a voltage resulting from a potential difference between a part of the plurality of pixel electrodes belonging to each horizontal line and the common electrode is applied to the electro-optical material, whereby image display or the like is performed.

  In order to drive such an electro-optical device (in particular, to supply a voltage to the common electrode), the driving device according to the present invention includes a supply circuit and a switching circuit.

  For example, the supply circuit supplies a voltage to each of the plurality of common electrodes included in the electro-optical device via a plurality of common lines formed corresponding to the plurality of common electrodes. Here, the supply circuit according to the present invention supplies different voltages (that is, the first voltage and the second voltage) to two common electrodes adjacent to each other among the plurality of common electrodes. Specifically, one of the first voltage (for example, a relatively high level voltage) and the second voltage (for example, a relatively low level voltage) is supplied to the first common electrode. Thus, the other of the first voltage and the second voltage is supplied to the second common electrode adjacent to the first common electrode. Here, the “first common electrode” is one or a plurality of common electrodes belonging to the first group, and typically, for example, a common electrode belonging to an odd-numbered row or a part thereof is exemplified. In addition, the term “second common electrode” here refers to a common electrode adjacent to the first common electrode (in other words, one or more common electrodes belonging to a second group different from the first group). Typically, for example, a common electrode belonging to an even-numbered row or a part thereof is given as an example. Thus, in the supply circuit according to the present invention, for example, each of the first voltage and the second voltage is set so that the potential levels of the voltages supplied to the two adjacent common electrodes are different (in other words, inverted). Are supplied to a plurality of common electrodes. However, the state in which the potential levels of the voltages supplied to two adjacent common electrodes are not necessarily required to be realized in all the common electrodes included in the electro-optical device, and all the common electrodes included in the electro-optical device are included. You may comprise so that the electric potential level of the voltage supplied to the common electrode which adjoins at least 2 of the electrodes differs.

  The switching circuit switches the voltage supplied to one common electrode among the plurality of common electrodes from the first voltage to the second voltage or from the second voltage to the first voltage every predetermined period. Here, the “predetermined period” means a period set in advance corresponding to the driving method as a period for inverting the supplied image signal, and is, for example, one horizontal scanning period, a frame period, a field period, or the like. . Specifically, for example, when the first voltage is supplied to one common electrode, the voltage supplied to the one common electrode is switched from the first voltage to the second voltage by the operation of the switching circuit. It is done. Similarly, for example, when the second voltage is supplied to one common electrode, the voltage supplied to the one common electrode is switched from the second voltage to the first voltage by the operation of the switching circuit. This switching operation is sequentially performed for each of the plurality of common lines. For example, the switching operation may be performed on one common electrode every horizontal scanning period. That is, after a switching operation for a certain common electrode is performed in a certain horizontal scanning period, a switching operation for the next common electrode may be performed in the next horizontal scanning period. However, as far as switching operation is performed on one common electrode, typically, for example, it is performed every vertical scanning period (or every frame period), but of course, it is performed every other period. Also good. For this reason, even after switching, a state in which the potential levels of the voltages supplied to the two adjacent common electrodes are different is maintained.

  The drive device according to the present invention further includes a control circuit in order to realize further reduction in power consumption required for driving the electro-optical device. The control circuit includes a common electrode and a storage capacitor before the voltage switched by the switching circuit is supplied to the single common electrode (or before the switching operation of the voltage supplied to the single common voltage is performed). The elements are electrically connected to each other. Typically, one common electrode and the storage capacitor element are directly short-circuited to each other or indirectly to each other through a predetermined element. At this time, it is preferable that the single common electrode is electrically disconnected from the supply circuit. Since the operation by the control circuit is performed on one common electrode to which the supplied voltage is switched, the operation is sequentially performed on a plurality of common electrodes in the same manner as the switching operation by the switching circuit.

  Here, the storage capacitor element has a capacitance larger than the capacitance of the common line corresponding to at least one common electrode among the plurality of common lines. However, considering that the operation by the control circuit is sequentially performed on a plurality of common electrodes, the storage capacitor element has a capacitance larger than the capacitance of each of the plurality of common lines. Is preferred. In addition, a common electrode (in other words, a common line electrically connected to the common electrode) to which the first voltage and the second voltage are alternately supplied is sequentially electrically connected to the storage capacitor element. The potential of the storage capacitor element converges to an intermediate potential between the potential of the first voltage and the potential of the second voltage. For this reason, by electrically connecting the one common electrode and the storage capacitor element, the potential of the one common electrode becomes an intermediate potential between the potential of the first voltage and the potential of the second voltage. That is, the potential of one common electrode can be changed from the potential of the first voltage or the potential of the second voltage to the intermediate potential without supplying (or consuming) special power.

  Note that such a storage capacitor element can be formed on the substrate at the same time that various wirings, semiconductor layers, electrodes, insulating films, and the like are formed on the substrate in the pixel portion and the drive circuit portion. In this way, little or no increase in the number of processes is required to form the storage capacitor element. However, the storage capacitor element may be retrofitted or provided in a circuit to be retrofitted. Further, when the storage capacitor element is formed on the substrate, it may be formed in an area that does not interfere with other various wirings in the peripheral region and the pixel region, for example.

  Thus, in the present invention, in order to invert the potential of each of the plurality of common electrodes, the supply circuit calculates the potential difference between the intermediate potential and the first voltage potential or the potential difference between the intermediate potential and the second voltage potential. It is sufficient to consume a relatively small amount of power that can be given. In other words, the supply circuit needs to consume relatively large power to the extent that the potential difference between the potential of the first voltage and the potential of the second voltage or the potential difference between the potential of the second voltage and the potential of the first voltage is given. Absent. For this reason, according to the present invention, it is necessary to provide a potential difference between the potential of the first voltage and the potential of the second voltage or a potential difference between the potential of the second voltage and the potential of the first voltage (that is, the switching operation). Compared to the configuration in which the common electrode and the storage capacitor element are not electrically connected to each other), the power consumption required for driving the electro-optical device (particularly, the operation of writing a potential to the common line) is reduced. be able to.

  In one aspect of the driving apparatus of the present invention, the control circuit stores the one common electrode after the predetermined time has elapsed after electrically connecting the one common electrode and the storage capacitor element to each other. It is electrically disconnected from the capacitive element.

  According to this aspect, after the potential of the one common electrode becomes an intermediate potential between the potential of the first voltage and the potential of the second voltage, the potential of the one common electrode is changed to the potential of the first voltage or The potential of the second voltage can be set. Therefore, the various effects described above can be suitably enjoyed.

  In addition, it is preferable that the one common electrode is electrically connected to the supply circuit in accordance with the electrical separation of the one common electrode and the storage capacitor element.

  In addition, the “predetermined time” in the present invention means a period necessary for the potential of one common electrode to increase or decrease due to the action of the storage capacitor element. For example, the potential of one common electrode is As an example, a period required to become an intermediate potential between the potential of the first voltage and the potential of the second voltage is given. As will be described later, one horizontal scanning period, horizontal blanking period, and the like are also examples of “predetermined time”.

  In another aspect of the driving apparatus of the present invention, the electro-optical device is sequentially supplied with scanning signals for controlling electrical connection between the data lines to which image signals are supplied and the plurality of pixel electrodes. The scanning circuit is provided for each of one or more horizontal lines, and the control circuit is located on the same horizontal line as another common electrode adjacent to the previous stage of the one common electrode among the plurality of common electrodes. The one common electrode and the storage capacitor element are electrically connected to each other at a timing according to the scanning signal supplied to the scanning line.

  According to this aspect, since the scanning signal is a signal that controls the timing of applying the image signal to the pixel electrode, for example, one common electrode that has already been displayed one frame before is electrically connected to the storage capacitor element. Can be connected to each other. In other words, one common electrode and a storage capacitor element are electrically connected to each other at a timing according to a scanning signal of a horizontal line (that is, a row) to which another common electrode located further before the one common electrode belongs. Therefore, even if the scanning direction is the forward direction or the reverse direction, the one common electrode and the storage capacitor element can be electrically connected to each other immediately before the image display is performed. .

  The term “front stage” in the present invention is intended to indicate that the front side (that is, the scanning order is the front side or the fast side) with respect to the scanning direction (particularly, the vertical scanning direction) in the electro-optical device.

  In the aspect of the driving device in which one common electrode and the storage capacitor element are electrically connected to each other at the timing according to the scanning signal as described above, the control circuit is positioned on the same horizontal line as the other common electrode. The one common electrode and the storage capacitor element may be electrically connected to each other while the scanning signal supplied to the scanning line is at the selected state level.

  According to this configuration, one common electrode and the storage capacitor element can be electrically connected to each other at an appropriate timing based on the scanning signal. As a result, the various effects described above can be suitably enjoyed.

  The “selected state level” in the present invention refers to turning on a switching element such as a TFT that is electrically connected to the scanning line and whose state is switched according to the level of the scanning signal (in other words, the switching state level). This is to indicate a level at which a pixel portion including an element can be selected).

  In the aspect of the driving device in which one common electrode and the storage capacitor element are electrically connected to each other at the timing according to the scanning signal as described above, the control circuit is positioned on the same horizontal line as the other common electrode. The one common electrode may be electrically disconnected from the storage capacitor element while the scanning signal supplied to the scanning line is in the non-selection state level.

  According to this configuration, one common electrode can be electrically separated from the storage capacitor element at an appropriate timing based on the scanning signal. As a result, the various effects described above can be suitably enjoyed.

  The “non-selected state level” in the present invention refers to turning off a switching element such as a TFT that is electrically connected to the scanning line and whose state is switched according to the level of the scanning signal (in other words, This is to indicate a level at which a pixel portion including a switching element can be set in a non-selected state.

  In another aspect of the drive device of the present invention, the electro-optical device is disposed so as to face the first substrate on which the plurality of pixel electrodes and the plurality of common electrodes are formed, and the first substrate. And the electro-optical material is sandwiched between the first substrate and the second substrate.

  According to this aspect, for example, the above-described various effects can be obtained in an electro-optical device of a lateral electric field drive method such as an FFS method or an IPS method.

  Note that the plurality of common electrodes may be formed on the second substrate side.

(Electro-optical device)
In order to solve the above problems, an electro-optical device of the present invention includes the above-described driving device of the present invention (including various aspects thereof).

  According to the electronic device of the present invention, since the drive device (or various aspects thereof) of the present invention described above is provided, the same effects as the various effects enjoyed by the drive device of the present invention described above can be enjoyed. . That is, it is possible to realize various electro-optical devices such as a liquid crystal device that can enjoy the same effects as the various effects enjoyed by the drive device of the present invention described above.

(Electronics)
In order to solve the above problems, an electronic apparatus according to the present invention includes the above-described electro-optical device according to the present invention (including various aspects thereof).

  According to the electronic apparatus of the present invention, since the electro-optical device (or various aspects thereof) of the present invention described above is provided, the same effects as those received by the electro-optical device of the present invention described above can be obtained. Can do. In other words, the projection display device, television, mobile phone, electronic notebook, portable audio player, word processor, digital camera, viewfinder type that can enjoy the same effects as those obtained by the electro-optical device of the present invention described above. Alternatively, various electronic devices such as a monitor direct-view video recorder, a workstation, a videophone, a POS terminal, and a touch panel can be realized.

  The operation and other advantages of the present invention will become more apparent from the embodiments described below.

  The best mode for carrying out the present invention will be described below with reference to the drawings. In the following description, a liquid crystal device is used as an example of the electro-optical device according to the invention.

(1) Basic Configuration of Liquid Crystal Device First, the configuration of the liquid crystal device according to the present embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view showing the configuration of the liquid crystal device according to this embodiment, and FIG. 2 is a cross-sectional view taken along the line HH ′ of FIG.

  1 and 2, in the liquid crystal device 100 according to the present embodiment, the TFT array substrate 10 as an example of the “first substrate” according to the present invention and the counter substrate 20 as an example of the “second substrate” according to the present invention. Are arranged opposite to each other. A liquid crystal layer 50 is sealed between the TFT array substrate 10 and the counter substrate 20, and the TFT array substrate 10 and the counter substrate 20 are in a frame-shaped or frame-shaped seal region located around the image display region 10a. The sealing material 52 provided is bonded to each other.

  The sealing material 52 is made of, for example, an ultraviolet curable resin, a thermosetting resin, or the like for bonding the two substrates, and is applied on the TFT array substrate 10 in the manufacturing process and then cured by ultraviolet irradiation, heating, or the like. It is. In the sealing material 52, spacers such as glass fibers or glass beads for dispersing the distance between the TFT array substrate 10 and the counter substrate 20 (inter-substrate gap) to a predetermined value are dispersed.

  A light-shielding frame light-shielding film 53 that defines the frame area of the image display area 10a is provided on the counter substrate 20 side in parallel with the inside of the seal area where the sealing material 52 is disposed. A data line driving circuit 101 and an external circuit connection terminal 102 are provided along one side of the TFT array substrate 10 in a region located outside the sealing region in which the sealing material 52 is disposed in the peripheral region. However, the data line driving circuit 101 may be provided inside the seal region so that the data line driving circuit 101 is covered with the frame light shielding film 53. Further, the scanning line driving circuit 104 and the common line driving circuit 110 constituting a specific example of the “driving device” in the present invention are arranged on the frame light shielding film 53 inside the seal region along two sides adjacent to the one side. It is provided to be covered.

  In FIG. 2, on the TFT array substrate 10, there is formed a laminated structure in which pixel switching TFTs (Thin Film Transistors), which are driving elements, and wirings such as scanning lines and data lines are formed. Specifically, in the image display area 10a, the common electrode 11, the insulating layer 12, and the pixel electrode 9a are formed in this order on the upper layer of the pixel switching TFT, the scanning line, the data line, and the like. That is, the liquid crystal device 100 according to the present embodiment employs a lateral electric field driving method (particularly, an FFS method) in which the alignment state of the liquid crystal layer 50 is controlled by an electric field generated between the pixel electrode 9a and the common electrode 11. . Here, the pixel electrodes 9a are provided in a matrix so as to form each pixel constituting the image display region 10a. On the other hand, the common electrode 11 is provided with a common electrode corresponding to the pixel electrode 9a belonging to one row for each row. On the other hand, a light shielding film 23 is formed on the surface of the counter substrate 20 facing the TFT array substrate 10. The light shielding film 23 is formed of, for example, a light shielding metal film or the like, and is patterned, for example, in a lattice shape in the image display region 10a on the counter substrate 20. An alignment film 8 is formed on the light shielding film 23. Further, the liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several types of nematic liquid crystals are mixed, and takes a predetermined alignment state between the pair of alignment films.

  Although not shown here, in addition to the data line driving circuit 101 and the scanning line driving circuit 104, the TFT array substrate 10 is used for inspecting the quality, defects, and the like of the liquid crystal device during manufacturing or at the time of shipment. An inspection circuit, an inspection pattern, or the like may be formed.

(2) Detailed Configuration of Liquid Crystal Device Next, with reference to FIG. 3, an electrical configuration of a main part of the liquid crystal device 100 according to the present embodiment will be described. FIG. 3 is a block diagram conceptually showing the electrical configuration of the main part of the liquid crystal device 100 according to this embodiment.

  In FIG. 3, the liquid crystal device 100 according to the present embodiment includes a scanning line driving circuit 104, a data line driving circuit 101, and a common line driving circuit in a peripheral region located around the image display region 10 a on the TFT array substrate 10. A drive circuit such as 110 is formed.

  The scanning line driving circuit 104 sequentially supplies scanning signals to the scanning lines Y1 to Yn (where n is an integer of 1 or more). For example, when a high level scanning signal is supplied to a certain scanning line Ya (where a is an integer satisfying 1 ≦ a ≦ n), all TFTs 116 connected to the scanning line Ya are turned on, and this scanning is performed. All the pixel portions 70 corresponding to the line Ya are selected.

  The data line driving circuit 101 sequentially supplies an image signal to the data lines X1 to Xm (where m is an integer equal to or greater than 1), and an image voltage based on the image signal is supplied to the pixel electrode 9a via the TFT 116 in the on state. Write.

  As will be described in detail later, the common line driving circuit 110 supplies the first voltage VCOMH or the second voltage VCOML having a lower potential than the first voltage VCOMH to the common line Zn. More specifically, the common line driving circuit 110 alternately supplies the first voltage VCOMH and the second voltage VCOML to the common line Za in the a-th row every frame period. For example, when the first voltage VCOMH is supplied to the common line Za in one frame period, the common line driving circuit 110 supplies the second voltage VCOML to the common line Za in the next one frame period. On the other hand, when the second voltage VCOML is supplied to the common line Za in one frame period, the common line driving circuit 110 supplies the first voltage VCOMH to the common line Za in the next one frame period. Further, the common line driving circuit 110 supplies different voltages to the common line Za-1 and the common line Za adjacent to each other. In other words, the common line drive circuit 110 supplies the first voltage VCOMH (or the second voltage VCOML) to the common line Za-1, while the second voltage VCOML (to the common line Za adjacent to the common line Za-1. Alternatively, the first voltage VCOMH) is supplied. The configuration and detailed operation of the common line driving circuit 110 will be described later in detail (see FIGS. 4 to 7).

  In addition, a saving capacitor element 130 is electrically connected to the common line driving circuit 110 via a saving capacitor wiring 131. The evacuation capacitive element 130 has a capacitance sufficiently larger than the capacitances of the common lines Z1 to Zn. Preferably, the evacuation capacitive element 130 preferably has a capacitance on the order of several tens to several hundred times the capacitances of the common lines Z1 to Zn. The evacuation capacitive element 130 may be formed on the TFT substrate 10 or formed on an FPC (Flexible Print Circuit) that connects the liquid crystal panel including the TFT substrate 10 and the counter substrate 20 and an external control circuit. Or may be formed at any other location. The details of the electrical connection between the common line driving circuit 110 and the save capacitor 130 will be described later (see FIG. 4).

  The liquid crystal device 100 according to the present embodiment is further provided with a plurality of pixel units 70 arranged in a matrix in the image display region 10 a occupying the center of the TFT array substrate 10.

  The pixel unit 70 includes a pixel switching TFT 116, a pixel electrode 9 a, a liquid crystal element 118, a common electrode 11, and a storage capacitor 119.

  The TFT 116 has a source terminal electrically connected to one of the data lines X1 to Xm, a gate terminal electrically connected to one of the scanning lines Y1 to Yn, and a drain terminal electrically connected to the pixel electrode 9a. Has been. The pixel switching TFT 116 is switched between an on state and an off state by a scanning signal supplied from the scanning line driving circuit 104.

  The liquid crystal element 118 is composed of the pixel electrode 9 a, the common electrode 11, and a liquid crystal positioned between the pixel electrode 9 a and the common electrode 21. The pixel electrode 9a is electrically connected to one of the data lines X1 to Xm through the TFT 116. The common electrode 11 is electrically connected to any one of the common wirings Z1 to Zn. The pixel electrode 9a and the common electrode 11 are both provided on the TFT array substrate 10 as described above. During the operation of the liquid crystal device 100, the pixel electrode 9a having the potential of the image signal supplied from the data lines X1 to Xm and the TFT 116, and the first voltage VCOMH or the second voltage supplied from the common line Z1 to Zn. A lateral electric field along the substrate surface of the TFT array substrate 10 is generated between the common electrode 11 having a potential of VCOML. The liquid crystal is modulated in accordance with the lateral electric field, that is, by changing the orientation and order of the molecular assembly in accordance with the lateral electric field, thereby enabling gradation display.

  The storage capacitor 119 is added in parallel with the liquid crystal element 118 in order to prevent the held image signal from leaking. One electrode constituting the storage capacitor 119 is electrically connected to the pixel electrode 9 a, and the other electrode is electrically connected to the common electrode 11.

  The above liquid crystal device 100 operates as follows.

  First, by supplying a high level scanning signal from the scanning line driving circuit 104 to the scanning line Ya, all the TFTs 116 connected to the scanning line Ya are turned on, and all the pixel units 70 related to the scanning line Ya are turned on. select.

  Further, in synchronization with the selection of the pixel portion 70 related to the scanning line Ya, the positive polarity image signal and the negative polarity image signal are transferred from the data line driving circuit 101 to the data lines X1 to Xm and the potentials of the common lines Z1 to Zn. An image signal is alternately supplied every horizontal scanning period. Specifically, if the potential of the common line Za is the first voltage VCOMH, a negative image signal is supplied to the data lines X1 to Xm. On the other hand, if the potential of the common line Za is the second voltage VCOML, a positive image signal is supplied to the data lines X1 to Xm.

  As a result, image signals are supplied from the data line driving circuit 101 to the pixel units 70 selected by the scanning line driving circuit 104 via the data lines X1 to Xm and the TFT 116, and an image voltage based on this image signal is applied to the pixels. It is written in the electrode 9a. Thereby, a potential difference is generated between the pixel electrode 9a and the common electrode 11, and a driving voltage is applied to the liquid crystal.

(3) Specific Configuration and Operation of Common Line Drive Circuit Next, a specific configuration and operation of the common line drive circuit 110 will be described with reference to FIG. FIG. 4 is a block diagram conceptually showing the configuration of the common line driving circuit 110. As shown in FIG.

  As shown in FIG. 4, the common line driving circuit 110 includes a latch circuit 111 that constitutes a specific example of the “supply circuit” and the “switching circuit” in the present invention, and the “supply circuit” and the “switching circuit” in the present invention. The voltage selection circuit 112 that constitutes one specific example and the short-circuit control circuit 113 that constitutes one specific example of the “control circuit” in the present invention are provided.

  Further, the save capacitor element 130 is electrically connected to the short circuit control circuit 113 in the common line drive circuit 110 via the save capacitor line 131. Details of the manner of electrical connection between the short-circuit control circuit 113 and the evacuation capacitor 130 will be described later (see FIG. 7).

  Next, the configuration of the latch circuit 111 included in the common line driving circuit 110 will be described with reference to FIG. FIG. 5 is a block diagram conceptually showing the structure of the latch circuit 111 provided in the common line driving circuit 110.

  As shown in FIG. 5, the latch circuit 111 includes a first latch circuit portion 111 # 1 provided corresponding to the common line Z1 in the first row, and a common line Z2 from the second row to the n-th row to Zn. Second latch circuit portions 111 # 2 to 111 # n provided correspondingly (that is, second latch circuits provided corresponding to the common line Zk (where k is an integer satisfying 2 ≦ k ≦ n)) Part 111 # k).

  The second latch circuit unit 111 # k includes a first inverter U12, a second inverter U13, a first clocked inverter U14, a second clocked inverter U15, a third inverter U16, and a fourth inverter U17.

  The common line Zk corresponding to the second latch circuit unit 111 # k is connected to the input terminal of the first inverter U12, the non-inverting input control terminal of the first clocked inverter U14, and the inverting input terminal of the second clocked inverter U15. The scanning line Yk-1 in the previous stage (that is, the previous row) is electrically connected. The output terminal of the first inverter U12 is electrically connected to the inverting input control terminal of the first clocked inverter U14 and the non-inverting input terminal of the second clocked inverter U15.

  The polarity signal POL is input to the input terminal of the first clocked inverter U14. The polarity signal POL is a signal for switching the potential level from the high level to the low level or from the low level to the high level every vertical scanning period. The output terminal of the first clocked inverter U14 is electrically connected to the output terminal of the second clocked inverter U15 and the input terminal of the second inverter U13. The output terminal of the second inverter U13 and the input terminal of the third inverter U16 are electrically connected to the input terminal of the second clocked inverter U15. The output terminal of the third inverter U16 is electrically connected to the input terminal of the fourth inverter U17.

  The second latch circuit unit 111 # k described above operates as follows.

  First, when a high level scanning signal is supplied to the scanning line Yk-1, the high level scanning signal is input to the non-inverting input control terminal of the first clocked inverter U14. The high level scanning signal is inverted in polarity by the first inverter U12 and converted into a low level signal, and the low level signal is input to the inverting input control terminal of the first clocked inverter U14. For this reason, the first clocked inverter U14 is turned on, and the polarity signal POL is inverted in polarity and output. The polarity signal POL output with the polarity inverted from the first clocked inverter U14 is inverted again by the second inverter U13 and returned to the polarity signal POL. The waveform shaping is performed at the third inverter U16 and the fourth inverter U17. Is output as a latch signal LATk.

  On the other hand, when a low level scanning signal is supplied to the scanning line Yk-1, the low level scanning signal is input to the inverting input control terminal of the second clocked inverter U15. The low-level scanning signal is inverted in polarity by the first inverter U12 and converted into a high-level signal, and the high-level signal is input to the non-inverting input control terminal of the second clocked inverter U15. Therefore, the second clocked inverter U15 is turned on, and the polarity of the polarity signal POL output from the second inverter U13 is inverted and output. The polarity signal POL output with the polarity inverted from the second clocked inverter U15 is inverted again by the second inverter U13 and returned to the polarity signal POL. The waveform shaping is performed at the third inverter U16 and the fourth inverter U17. After that, the polarity signal POL is output as the latch signal LATk.

  That is, when a high level scan signal is supplied to the scan line Yk-1, the second latch circuit unit 111 # k takes in the polarity signal POL and outputs the fetched polarity signal POL as the latch signal LATk. In addition, when a low level scanning signal is supplied to the scanning line Yk−1, the second latch circuit unit 111 # k outputs the output while holding the latch signal LATk by the second inverter U13 and the second clocked inverter U15. To do. In other words, the second latch circuit unit 111 # k receives the polarity signal POL captured at the time when the high-level scanning signal is input to the scanning line Yk−1 for at least one vertical scanning period (or one frame period). Can continue to output.

  Next, the first latch circuit unit 111 # 1 will be described. The first latch circuit unit 111 # 1 is different from the second latch circuit unit 111 # k in that the high potential power source VHH is replaced with the input terminal of the first inverter U12 and the first clocked inverter instead of the scanning line Yk-1. The difference is that the non-inverting input control terminal of U14 and the inverting input terminal of the second clocked inverter U15 are electrically connected to each other. The operation of the first latch circuit unit 111 # 1 is the same as the operation of the second latch circuit unit 111 # k. That is, the first latch circuit unit 111 #! Then, the first clocked inverter U14 is always turned on, and the captured polarity signal POL can be continuously output.

  Next, the configuration of the voltage selection circuit 112 included in the common line driving circuit 110 will be described with reference to FIG. FIG. 6 is a block diagram conceptually showing the structure of the voltage selection circuit 112 provided in the common line driving circuit 110.

  As shown in FIG. 6, the voltage selection circuit 112 includes odd-numbered common lines Zi (where i is an odd number satisfying 1 ≦ i ≦ n, specifically 1, 3,... K−. 1,..., N−1) and the first voltage selection circuit unit 112-1 # i provided in correspondence with the even-numbered common line Zj (where j is an even number satisfying 1 ≦ i ≦ n) Specifically, the second voltage selection circuit unit 112-2 # j provided corresponding to 2, 4,..., K,. FIG. 6 illustrates an example in which k is an even number for simplification of description.

  The first voltage selection circuit unit 112-1 # i includes a TFT U22 and a TFT U23. The latch signal LATi output from the latch circuit 111 is input to each of the non-inverting input gate terminal of the TFT U22 and the inverting input gate terminal of the TFT U23. The first voltage VCOMH is supplied to the source terminal of the TFT U23. The second voltage VCOML is supplied to the source terminal of the TFT U22. Further, the drain terminal of the TFT U22 and the drain terminal of the TFT U23 are electrically connected to each other.

  The first voltage circuit selector 112-1 # i described above operates as follows.

  First, when a high level latch signal LATi is output from the latch circuit 111, the high level latch signal LATi is input to each of the non-inverting input gate terminal of the TFT U22 and the inverting input gate terminal of the TFT U23. Therefore, the TFT U22 is turned on and the TFT U23 is turned off. As a result, the second voltage VCOML is output as the voltage level signal VOUTi via the TFT U22 from the VCOML line that supplies the second voltage VCOML.

  On the other hand, when the low level latch signal LATi is output from the latch circuit 111, the low level latch signal LATi is input to each of the non-inverting input gate terminal of the TFT U22 and the inverting input gate terminal of the TFT U23. Therefore, the TFT U22 is turned off and the TFT U23 is turned on. As a result, the first voltage VCOMH is output as the voltage level signal VOUTi from the VCOMH line that supplies the first voltage VCOMH via the TFT U23.

  The second voltage selection circuit unit 112-2 # j further includes an inverter U21 in addition to the configuration included in the first voltage selection circuit unit 112-1 # i.

  The latch signal LATj output from the latch circuit 111 is input to the input terminal of the inverter U21. The non-inverting input gate terminal of the TFT U22 and the inverting input gate terminal of the TFT U23 are electrically connected to the output terminal of the inverter U21. Other configurations are the same as those of the first voltage selection circuit unit 112-1 # i.

  The second voltage circuit selector 112-2 # j described above operates as follows.

First, when a high level latch signal LATj is output from the latch circuit 111, the polarity of the high level latch signal LATj is inverted by the inverter U21 and converted into a low level signal. It is input to each of the non-inverting input gate terminal of the TFT U22 and the inverting input gate terminal of the TFT U23. Therefore, the TFT U22 is turned off and the TFT 23 is turned on. As a result, the first voltage VCOMH is output as the voltage level signal VOUTj from the VCOMH line that supplies the first voltage VCOMH via the TFT U23. On the other hand, when the latch signal LATj at the low level is output from the latch circuit 111, The low level latch signal LATj is converted into a high level signal by inverting the polarity in the inverter U21, and the high level signal is applied to each of the non-inverting input gate terminal of the TFT U22 and the inverting input gate terminal of the TFT U23. Entered. Therefore, the TFT U22 is turned on and the TFT 23 is turned off. As a result, the second voltage VCOML is output as the voltage level signal VOUTj from the VCOML line that supplies the second voltage VCOML via the TFT U22.

  Next, the configuration of the short-circuit control circuit 113 provided in the common line drive circuit 110 will be described with reference to FIG. FIG. 7 is a block diagram conceptually showing the structure of the short-circuit control circuit 113 provided in the common line drive circuit 110.

  As shown in FIG. 7, the short-circuit control circuit 113 includes a first short-circuit control circuit unit 113 # 1 provided corresponding to the common line Z1 in the first row and a common line Z2 from the second row to the n-th row. Second short circuit control circuit portions 113 # 2 to 111 # n (corresponding to common line Zk (where k is an integer satisfying 2 ≦ k ≦ n)) provided corresponding to Zn. 2 short circuit control circuit portion 113 # k).

  The second short circuit control circuit unit 113 # k includes a TFT U31 and a TFT U32. The voltage level signal VOUTk is input to the source terminal of the TFT U31. Each of the inverting input gate terminal of the TFT U31 and the non-inverting input gate terminal of the TFT U32 has a scanning line Yk-1 preceding the common line Zk corresponding to the second short-circuit control circuit unit 113 # k (that is, the previous row). Electrically connected. The common line Zk and the source terminal of the TFT U32 are electrically connected to the drain terminal of the TFT U31. A save capacitor wiring 131 is electrically connected to the drain terminal of the TFT U 32.

  The second short-circuit control circuit unit 113 # k described above operates as follows.

  First, when a high level scanning signal is supplied to the scanning line Yk-1, the high level scanning signal is input to the inverting input gate terminal of the TFT U31 and the inverting input gate terminal of the TFT U32. For this reason, the TFT U31 is turned off and the TFT U32 is turned on. As a result, the voltage level signal VOUTk is not supplied to the common line Zk. On the other hand, the common line Zk and the save capacitor line 131 are electrically connected to each other through the TFT U32. Here, the evacuation capacitive element 130 has a capacitance sufficiently larger than the capacitances of the common lines Z1 to Zn, and the common line Zk includes the first voltage VCOMH and the second voltage. Since VCOML is supplied alternately, the potential of the save capacitor 130 is an intermediate potential between the potential of the first voltage VCOMH and the potential of the second voltage VCOML (typically, the potential of the first voltage VCOMH). (Average value of the second voltage VCOML). Therefore, the common line Zk and the save capacitor 130 are electrically connected, so that the potential of the common line Zk becomes an intermediate potential between the potential of the first voltage VCOMH and the potential of the second voltage VCOML. Become. That is, the potential of the common line Zk is set to the potential of the first voltage VCOMH or the second voltage without supplying (or consuming) special power (in other words, without supplying voltage from the VCOMH line or the VCOML line). A transition from the potential of VCOML to the intermediate potential can be performed.

  On the other hand, when a low level scanning signal is supplied to the scanning line Yk-1, the low level scanning signal is input to each of the inverting input gate terminal of the TFT U31 and the inverting input gate terminal of the TFT U32. Therefore, the TFT U31 is turned on and the TFT U32 is turned off. As a result, the voltage level signal VOUTk is supplied to the common line Zk. On the other hand, the common line Zk and the save capacitor line 131 (in other words, the save capacitor element 130) are electrically separated from each other via the TFT U32. Accordingly, the first voltage VCOMH or the second voltage VCOML is supplied to the common line Zk that has been at the intermediate potential. As a result, the potential of the common line Zk becomes the potential of the first voltage VCOMH or the potential of the second voltage VCOML.

  Next, the first short circuit control circuit unit 113 # 1 will be described. The first short-circuit control circuit unit 113 # 1 is different from the second short-circuit control circuit unit 113 # k in that the scan line Yn is replaced with the inverting input gate terminal of the TFT U31 and the non-inverted TFT U32 instead of the scan line Yk-1. The difference is that each input gate terminal is electrically connected. The operation of the first short-circuit control circuit unit 113 # 1 is the same as the operation of the second short-circuit control circuit unit 113 # k. That is, the first short-circuit control circuit unit 113 # 1 electrically connects the common line Z1 and the comparison capacitor line 131 to each other when a high level scanning signal is supplied to the scanning line Yn. In addition, when the low level scanning signal is supplied to the scanning line Yn, the common line Z1 and the saving capacitor wiring 131 are electrically separated from each other and the voltage level signal VOUT1 is supplied to the scanning line Z1.

  Here, the operation of the common line driving circuit 110 performing the above operation will be described in more detail with reference to FIG. FIG. 8 is a timing chart showing the operation of the common line driving circuit 110.

  As shown in FIG. 8, it is assumed that the polarity signal POL is inverted from a low level to a high level at time t1. Since the polarity signal POL switches to the high level, the odd-numbered common line Zi (where i = 1, 3,..., N−1) to which the first voltage VCOMH was supplied in the previous frame (frame # 1). ), The second voltage VCOML is supplied in the next frame (frame # 2), and the common line Zj (where j = 2) in which the second voltage VCOML was supplied in the previous frame. 4,..., N), the first voltage VCOMH is supplied in the next frame.

  Here, at the time t0 before the polarity signal POL is inverted and at the time t0 when the scanning signal of the scanning line Yn becomes high level, the common line Z1 and the saving capacitor wiring 131 are electrically connected to each other. For this reason, the potential of the common line Z1 becomes an intermediate potential. That is, the potential of the common line Z1 transitions from the potential of the first voltage VCOMH to the intermediate potential. After that, when the scanning signal of the scanning line Yn becomes low level and the polarity signal POL is inverted at time t1, the second voltage VCOML is supplied to the common line Z1.

  Thereafter, when the scanning signal of the scanning line Y1 becomes a high level, the common line Z2 and the saving capacitor wiring 131 are electrically connected to each other. For this reason, the potential of the common line Z2 becomes an intermediate potential. That is, the potential of the common line Z2 changes from the potential of the second voltage VCOML to the intermediate potential. Thereafter, when the scanning signal of the scanning line Y1 becomes low level and the polarity signal POL is inverted, the first voltage VCOMH is supplied to the common line Z2.

  Thereafter, when the scanning signal of the scanning line Y2 becomes a high level, the common line Z3 and the save capacitor wiring 131 are electrically connected to each other. For this reason, the potential of the common line Z3 becomes an intermediate potential. That is, the potential of the common line Z3 transitions from the potential of the first voltage VCOMH to the intermediate potential. Thereafter, when the scanning signal of the scanning line Y2 becomes low level and the polarity signal POL is inverted, the second voltage VCOML is supplied to the common line Z3.

  Similarly, for the other common line Zk-1, when the scanning signal of the scanning line Yk-2 becomes high level, (i) the common line Zk-1 and the saving capacitor wiring 131 are electrically connected to each other. By being connected, the potential of the common line Zk-1 changes from the potential of the first voltage VCOMH to the intermediate potential, and (ii) the inverted polarity signal POL is output as the latch signal LATk-1, and the potential level signal VOUTk −1 switches from the first voltage VCOMH to the second voltage VCOML. Thereafter, when the scanning signal of the scanning line Yk-1 becomes a low level, the common line Zk-1 and the saving capacitor wiring 131 are electrically disconnected, so that the potential of the common line Zk-1 becomes an intermediate potential. Makes a transition to the potential of the second voltage VCOML.

  Similarly, for the other common lines Zk, when the scanning signal of the scanning line Yk-1 becomes high level, (i) the common line Zk and the saving capacitance wiring 131 are electrically connected to each other. As a result, the potential of the common line Zk changes from the potential of the second voltage VCOML to the intermediate potential, and (ii) the inverted polarity signal POL is output as the latch signal LATk, and the potential level signal VOUTk is changed from the second voltage VCOML. Switching to the first voltage VCOMH. Thereafter, when the scanning signal of the scanning line Yk becomes a low level, the common line Zk and the saving capacitor wiring 131 are electrically disconnected, so that the potential of the common line Zk is changed from the intermediate potential to the first voltage VCOMH. Transition to potential.

  When the display operation for frame # 3 is performed after the display operation for frame # 2 is completed, the same operation is generally performed.

  Specifically, at time t3 when the display operation of frame # 2 ends, the polarity signal POL is inverted from the high level to the low level. Since the polarity signal POL switches to the low level, the odd-numbered common line Zi (where i = 1, 3,..., N−1) to which the second voltage VCOML was supplied in the previous frame (frame # 2). ), The first voltage VCOMH is supplied in the next frame (frame # 3), and the common line Zj (where j = 2) in which the first voltage VCOMH was supplied in the previous frame. 4,..., N) is supplied with the second voltage VCOML in the next frame.

  Here, at the time t2 before the polarity signal POL is inverted and at the time t2 when the scanning signal of the scanning line Yn becomes high level, the common line Z1 and the saving capacitor wiring 131 are electrically connected to each other. For this reason, the potential of the common line Z1 is an intermediate potential. That is, the potential of the common line Z1 changes from the potential of the second voltage VCOML to the intermediate potential. Thereafter, when the scanning signal of the scanning line Yn becomes low level and the polarity signal POL is inverted at time t3, the first voltage VCOMH is supplied to the common line Z1.

  Similarly, for the other common line Zk-1, when the scanning signal of the scanning line Yk-2 becomes high level, (i) the common line Zk-1 and the saving capacitor wiring 131 are electrically connected to each other. By being connected, the potential of the common line Zk-1 changes from the potential of the second voltage VCOML to the intermediate potential, and (ii) the inverted polarity signal POL is output as the latch signal LATk-1, and the potential level signal VOUTk −1 switches from the second voltage VCOML to the first voltage VCOMH. Thereafter, when the scanning signal of the scanning line Yk-2 becomes a low level, the common line Zk-1 and the saving capacitor wiring 131 are electrically disconnected, so that the potential of the common line Zk-1 becomes an intermediate potential. Makes a transition to the potential of the first voltage VCOMH.

  Similarly, for the other common lines Zk, when the scanning signal of the scanning line Yk-1 becomes high level, (i) the common line Zk and the saving capacitance wiring 131 are electrically connected to each other. As a result, the potential of the common line Zk changes from the potential of the first voltage VCOMH to the intermediate potential, and (ii) the inverted polarity signal POL is output as the latch signal LATk, and the potential level signal VOUTk is changed from the first voltage VCOMH. The voltage is switched to the second voltage VCOML. After that, when the scanning signal of the scanning line Yk−1 becomes low level, the common line Zk and the saving capacitor wiring 131 are electrically disconnected, so that the potential of the common line Zk is changed from the intermediate potential to the second voltage. Transition to the potential of VCOML.

  Thus, according to the present embodiment, in order to invert the potential of the common line Z1 to Zn from the first voltage VCOMH to the second voltage VCOML or from the second voltage VCOML to the first voltage VCOMH, It is sufficient to consume relatively small electric power that can provide a potential difference between the potential of the first voltage VCOMH or an intermediate potential and a potential difference between the second voltage VCOML. In other words, it is necessary to consume relatively large power to the extent that the potential difference between the potential of the first voltage VCOMH and the potential of the second voltage VCOML or the potential difference between the potential of the second voltage VCOML and the potential of the first voltage VCOMH is given. Absent. Therefore, according to the present embodiment, the potential difference between the potential of the first voltage VCOMH and the potential of the second voltage VCOML or the potential difference between the potential of the second voltage VCOML and the potential of the first voltage VCOMH is determined only for the VCOMH line and the VCOML line. Reduction of power consumption required for the operation of writing the potential from the common line Z1 to Zn (for example, approximately) Reduction of about half).

  In addition, since the common line Zk is electrically connected to the evacuation capacitor 130 at the timing when the scanning signal of the previous row (specifically, the (k−1) th row) becomes high level, the common line is actually connected. When a voltage is applied to the liquid crystal using the common electrode 11 electrically connected to Zk (that is, when the scanning signal of the scanning line Yk becomes high level), the potential of the common electrode 11 is originally intended. It is a potential. In other words, the common line Zk is electrically connected to the evacuation capacitor element 130 before the voltage is applied to the liquid crystal using the common electrode 11 that is actually electrically connected to the common line Zk. There is no particular influence on the image display.

  In the above description, the pixel electrode 9a and the common electrode 11 are provided on different layers while being provided on the TFT substrate 10, and the pixel electrode 9a and the common electrode 11 sandwich the insulating layer 12 therebetween. The liquid crystal device 100 adopting the FFS method having an opening in the pixel electrode 9a on the liquid crystal layer 50 side has been described, but the common electrode 11 having the opening is provided on the liquid crystal layer 50 side. Also good. Needless to say, the liquid crystal device adopting the IPS method in which the pixel electrode 9a and the common electrode 11 are provided in the same layer can also enjoy the various effects described above by adopting the above-described configuration. Further, not only a liquid crystal device adopting a horizontal electric field driving method, but also adopting a vertical electric field driving method such as a TN (twisted nematic) method, an ECB (birefringence field effect) method, a VA (vertical alignment) method, or the like. Also in the liquid crystal device, by adopting the above-described configuration, the various effects described above can be enjoyed accordingly.

(4) Modified Example Next, with reference to FIGS. 9 and 10, a modified example (common line drive circuit 120) of the common line drive circuit included in the liquid crystal device 100 according to the present embodiment will be described. FIG. 9 is a block diagram conceptually showing the configuration of the latch circuit 121 included in the common line drive circuit 120 according to the modification. FIG. 10 is a short circuit control included in the common line drive circuit 120 according to the modification. 3 is a block diagram conceptually showing the structure of a circuit 123. FIG. Note that the same components as those of the common line driving circuit 110 described above are denoted by the same reference numerals, and detailed description thereof is omitted.

  As shown in FIG. 9, the latch circuit 121 according to the modified example includes a first latch circuit unit 121 # 1 provided corresponding to the common line Z1 in the first row, and the common lines in the second to nth rows. Second latch circuit sections 121 # 2 to 121 # n (corresponding to common line Zk (where k is an integer satisfying 2 ≦ k ≦ n)) provided corresponding to Z2 to Zn Second latch circuit portion 121 # k).

  The first latch circuit unit 121 # 1 includes a NAND circuit U18, a NAND circuit U19, and a NAND circuit U20 in addition to the configuration included in the first latch circuit unit 111 # 1 described above.

  The output terminal of the NAND circuit U18 is electrically connected to the input terminal of the first inverter U12, the non-inverting input control terminal of the first clocked inverter U14, and the inverting input terminal of the second clocked inverter U15. The two input terminals of the NAND circuit U18 are electrically connected to the output terminal of the NAND circuit U19 and the output terminal of the NAND circuit U20, respectively. The two input terminals of the NAND circuit U19 are supplied with a signal XCSV, which is a signal obtained by inverting the scan direction control signal CSV, and a scanning signal supplied to the scanning line Y2. A high level signal and a scan direction control signal CSV output from the high potential power supply VHH are input to the two input terminals of the NAND circuit U20, respectively.

  The scan direction control signal CSV is a high-level signal when the scan direction is the forward direction (specifically, when the scan signals are sequentially supplied from the scan lines Y1 to Yn), and the scan direction is reversed. When the signal is in the direction (specifically, when the scanning signal is sequentially supplied from the scanning line Yn toward Y1), the signal becomes a low level signal.

  When the scan direction is the forward direction, the output of the NAND circuit U19 is always at a high level, and the output of the NAND circuit U20 is a signal obtained by inverting the high level signal output from the high potential power supply VHH (that is, , A low level signal). As a result, the output of the NAND circuit 18 becomes a high level signal output from the high potential power supply VHH.

  On the other hand, when the scanning direction is the reverse direction, the output of the NAND circuit U19 is a signal obtained by inverting the scanning signal supplied to the scanning line Y2, and the output of the NAND circuit U20 is always a high level signal. Become. As a result, the output of the NAND circuit 18 becomes a scanning signal supplied to the scanning line Y2.

  Similarly, the second latch circuit unit 121 # k includes a NAND circuit U18, a NAND circuit U19, and a NAND circuit U20 in addition to the configuration included in the second latch circuit unit 111 # k described above.

  The output terminal of the NAND circuit U18 is electrically connected to the input terminals of the first inverter U12, the non-inverting input control terminal of the first clocked inverter U14, and the inverting input terminal of the second clocked inverter U15. The two input terminals of the NAND circuit U18 are electrically connected to the output terminal of the NAND circuit U19 and the output terminal of the NAND circuit U20, respectively. The two input terminals of the NAND circuit U19 are supplied with a signal XCSV, which is a signal obtained by inverting the scan direction control signal CSV, and a scanning signal supplied to the scanning line Yk + 1, respectively. The scanning signal supplied to the scanning line Yk-1 and the scanning direction control signal CSV are input to the two input terminals of the NAND circuit U20, respectively.

  When the scanning direction is the forward direction, the output of the NAND circuit U19 is always at a high level, and the output of the NAND circuit U20 is a signal obtained by inverting the scanning signal supplied to the scanning line Yk-1. As a result, the output of the NAND circuit 18 becomes a scanning signal supplied to the scanning line Yk-1.

  On the other hand, when the scanning direction is the reverse direction, the output of the NAND circuit U19 is a signal obtained by inverting the scanning signal supplied to the scanning line Yk + 1, and the output of the NAND circuit U20 is always a high level signal. Become. As a result, the output of the NAND circuit 18 becomes a scanning signal supplied to the scanning line Yk + 1.

  Since the latch circuit 121 according to the modified example has the above-described configuration, the scanning signal of the previous row in the scanning direction can be specified in each latch circuit unit 121 # k, and the specified scanning signal The polarity signal POL can be captured at a timing when becomes high level. Therefore, regardless of whether the scan direction is the forward direction or the reverse direction, the above-described operation can be suitably performed, and as a result, the above-described various effects can be suitably enjoyed.

  As shown in FIG. 10, the short-circuit control circuit 123 according to the modified example includes a first short-circuit control circuit unit 123 # 1 provided corresponding to the common line Z1 in the first row, and the second to n-th rows. Corresponding to the second short circuit control circuit parts 123 # 2 to 123 # n provided corresponding to the common lines Z2 to Zn (that is, k is an integer satisfying 2 ≦ k ≦ n). Second short circuit control circuit portion 123 # k) provided.

  The first short-circuit control circuit unit 123 # 1 includes a NAND circuit U38, a NAND circuit U39, and a NAND circuit U40 in addition to the configuration included in the first short-circuit control circuit unit 113 # 1 described above.

  The output terminal of the NAND circuit U38 is electrically connected to the inverting input gate terminal of the TFT U31 and the non-inverting input gate terminal of the TFT U32. The two input terminals of the NAND circuit U38 are electrically connected to the output terminal of the NAND circuit U39 and the output terminal of the NAND circuit U40, respectively. The two input terminals of the NAND circuit U39 are supplied with a signal XCSV, which is an inverted version of the scan direction control signal CSV, and a scanning signal supplied to the scanning line Y2. The scanning signal supplied to the scanning line Yn and the scanning direction control signal CSV are input to the two input terminals of the NAND circuit U40, respectively.

  When the scanning direction is the forward direction, the output of the NAND circuit U39 is always at a high level, and the output of the NAND circuit U40 is a signal obtained by inverting the scanning signal supplied to the scanning line Yn. As a result, the output of the NAND circuit 38 becomes a scanning signal supplied to the scanning line Yn.

  On the other hand, when the scanning direction is the reverse direction, the output of the NAND circuit U39 is a signal obtained by inverting the scanning signal supplied to the scanning line Y2, and the output of the NAND circuit U40 is always a high level signal. Become. As a result, the output of the NAND circuit 38 becomes a scanning signal supplied to the scanning line Y2.

  Similarly, the second short circuit control circuit unit 123 # k includes a NAND circuit U38, a NAND circuit U39, and a NAND circuit U40 in addition to the configuration included in the second short circuit control circuit unit 113 # k described above.

  The output terminal of the NAND circuit U38 is electrically connected to the inverting input gate terminal of the TFT U31 and the non-inverting input gate terminal of the TFT U32. The two input terminals of the NAND circuit U38 are electrically connected to the output terminal of the NAND circuit U39 and the output terminal of the NAND circuit U40, respectively. The two input terminals of the NAND circuit U39 receive a signal XCSV that is an inverted version of the scan direction control signal CSV and a scanning signal supplied to the scanning line Yk + 1, respectively. The scanning signal supplied to the scanning line Yk-1 and the scanning direction control signal CSV are input to the two input terminals of the NAND circuit U40, respectively.

  When the scanning direction is the forward direction, the output of the NAND circuit U39 is always at a high level, and the output of the NAND circuit U40 is a signal obtained by inverting the scanning signal supplied to the scanning line Yk-1. As a result, the output of the NAND circuit 38 becomes a scanning signal supplied to the scanning line Yk-1.

  On the other hand, when the scanning direction is the reverse direction, the output of the NAND circuit U39 is a signal obtained by inverting the scanning signal supplied to the scanning line Yk + 1, and the output of the NAND circuit U40 is always a high level signal. Become. As a result, the output of the NAND circuit 38 becomes a scanning signal supplied to the scanning line Yk + 1.

  Since the short-circuit control circuit 123 according to the modified example has the above-described configuration, the scanning signal of the previous row in the scan direction can be specified in each short-circuit control circuit unit 123 # k and specified. The common line Zk can be electrically connected to the save capacitor element 130 at the timing when the scanning signal becomes high level. Therefore, regardless of whether the scan direction is the forward direction or the reverse direction, the above-described operation can be suitably performed, and as a result, the above-described various effects can be suitably enjoyed.

  Of the second latch circuits 121 # k described above, the second latch circuit 121 # n is supplied to the input terminal of the NAND circuit U19 to the scanning line Yk + 1 (that is, when k = n). It is preferable that a high level signal output from the high potential power supply VHH is input instead of the scanning signal. Among the second short-circuit control circuits 123 # k described above, the second short-circuit control circuit 123 # n (that is, when k = n) is connected to the input terminal of the NAND circuit U19 at the scanning line Yk + 1. It is preferable that a scanning signal supplied to the scanning line Y1 is input instead of the scanning signal supplied to.

(5) Electronic Device Next, an example of an electronic device including the liquid crystal device 100 described above will be described with reference to FIGS. 11 and 12.

  FIG. 11 is a perspective view of a mobile personal computer to which the liquid crystal device 100 described above is applied. In FIG. 11, a computer 1200 includes a main body 1204 provided with a keyboard 1202 and a liquid crystal display unit 1206 including the liquid crystal device 100 described above. The liquid crystal display unit 1206 is configured by adding a backlight to the back surface of the liquid crystal device 100.

  Next, an example in which the above-described liquid crystal device 100 is applied to a mobile phone will be described. FIG. 12 is a perspective view of a mobile phone which is an example of an electronic apparatus. In FIG. 12, a mobile phone 1300 includes a liquid crystal device 1005 that employs a transflective display format and has the same configuration as the liquid crystal device 1 described above, together with a plurality of operation buttons 1302.

  Since these electronic devices also include the liquid crystal device 100 described above, the various effects described above can be suitably enjoyed.

  In addition to the electronic apparatus described with reference to FIGS. 11 and 12, a liquid crystal television, a viewfinder type or a monitor direct view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, a word processor, a workstation And a direct-view display device including a video phone, a POS terminal, and a touch panel, and a projection display device such as a liquid crystal projector. Needless to say, the present invention can be applied to these various electronic devices.

  The present invention is not limited to the above-described embodiments, and can be changed as appropriate without departing from the spirit or concept of the invention that can be read from the claims and the entire specification, and the drive device accompanying such changes Electro-optical devices and electronic devices are also included in the technical scope of the present invention.

It is a top view which shows the structure of the liquid crystal device which concerns on embodiment. It is H-H 'sectional drawing of FIG. It is a block diagram which shows notionally the electrical structure of the principal part of the liquid crystal device which concerns on this embodiment. It is a block diagram which shows notionally the structure of a common line drive circuit. It is a block diagram which shows notionally the structure of the latch circuit with which a common line drive circuit is provided. It is a block diagram which shows notionally the structure of the voltage selection circuit with which a common line drive circuit is provided. It is a block diagram which shows notionally the structure of the short circuit control circuit with which a common line drive circuit is provided. It is a timing chart which shows operation | movement of a common line drive circuit. It is a block diagram which shows notionally the structure of the latch circuit with which the common line drive circuit which concerns on a modification is provided. It is a block diagram which shows notionally the structure of the short circuit control circuit with which the common line drive circuit which concerns on a modification is provided. It is a perspective view of a mobile personal computer to which a liquid crystal device is applied. 1 is a perspective view of a mobile phone to which a liquid crystal device is applied.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Liquid crystal device, 11 ... Common electrode, 101 ... Data line drive circuit, 104 ... Scan line drive circuit, 110 ... Common line drive circuit, 111 ... Latch circuit, 112 ... Voltage selection circuit, 113 ... Short-circuit control circuit, 130 ... Capacitance elements for retraction, Y1 to Yn: scanning lines, Z1 to Zn: common lines

Claims (8)

In response to a plurality of pixel electrodes, a plurality of common electrodes formed corresponding to the pixel electrodes for each of the one or more horizontal lines, and an electric field applied between the plurality of pixel electrodes and the plurality of common electrodes A driving device for driving an electro-optical device comprising an electro-optical material to be driven,
The first voltage and the plurality of common electrodes are supplied to the two common electrodes adjacent to each other among the plurality of common electrodes, respectively, such that the first voltage and a second voltage different from the first voltage are supplied. A supply circuit for supplying each of the second voltages;
A switching operation for switching a voltage supplied to one common electrode of the plurality of common electrodes from the first voltage to the second voltage or from the second voltage to the first voltage every predetermined period. And a switching circuit that sequentially performs the switching operation on the plurality of common electrodes;
Before the voltage switched by the switching circuit is supplied to the one common electrode, the storage has a capacitance larger than the capacitance of the common line corresponding to the one common electrode among the plurality of common lines. And a control circuit that electrically connects the capacitive element and the one common electrode to each other.   The control circuit electrically disconnects the one common electrode and the storage capacitor element after a predetermined time has elapsed after electrically connecting the one common electrode and the storage capacitor element to each other. The drive device according to claim 1. The electro-optical device includes a scanning line for sequentially supplying a scanning signal for controlling an electrical connection between a data line to which an image signal is supplied and the plurality of pixel electrodes for each of one or more horizontal lines. Has
The control circuit has a timing according to the scanning signal supplied to the scanning line located on the same horizontal line as the other common electrode adjacent to the previous stage of the one common electrode among the plurality of common electrodes, 3. The driving apparatus according to claim 1, wherein the one common electrode and the storage capacitor element are electrically connected to each other.   The control circuit is configured to connect the one common electrode and the storage capacitor element while the scanning signal supplied to the scanning line located on the same horizontal line as the other common electrode is at a selected state level. The drive device according to claim 3, wherein the drive devices are electrically connected to each other.   The control circuit removes the one common electrode from the storage capacitor element while the scanning signal supplied to the scanning line located on the same horizontal line as the other common electrode is at a non-selected state level. The drive device according to claim 3 or 4, wherein the drive device is electrically disconnected. The electro-optical device includes a first substrate on which each of the plurality of pixel electrodes and the plurality of common electrodes is formed, and a second substrate disposed so as to face the first substrate,
6. The driving device according to claim 1, wherein the electro-optical material is sandwiched between the first substrate and the second substrate. 7.   An electro-optical device comprising the drive device according to claim 1.   An electronic apparatus comprising the electro-optical device according to claim 7.

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