JP2007134491A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2007134491A
JP2007134491A JP2005325957A JP2005325957A JP2007134491A JP 2007134491 A JP2007134491 A JP 2007134491A JP 2005325957 A JP2005325957 A JP 2005325957A JP 2005325957 A JP2005325957 A JP 2005325957A JP 2007134491 A JP2007134491 A JP 2007134491A
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semiconductor device
lead
circuit board
sealing resin
resin
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JP4945116B2 (en
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Hiroyuki Kano
裕之 加納
Ryosuke Kondo
亮介 近藤
Naotaka Adachi
直隆 足立
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Stanley Electric Co Ltd
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Stanley Electric Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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Abstract

<P>PROBLEM TO BE SOLVED: To inexpensively provide a highly reliable semiconductor device that is mountable to a circuit board while reducing optical-axis deviations without occurrence of blowholes at a soldered part when applying soldering to the circuit board in the semiconductor device mounted to the circuit board. <P>SOLUTION: The semiconductor device 1 is composed by sealing an LED chip 3, a bonding wire 4, and each one end part of a pair of lead frames 2a, 2b with a sealing resin 5. The bottom face 10 of the sealing resin 5 is inclined at a prescribed angle α to a face vertical to an optical axis (A) of the LED chip 3. A lead stopper 11 protruding in a direction vertical to an extended direction of the lead frame 2a is formed in one lead frame 2a of the lead frames 2a, 2b extended from the bottom face 10 of the sealing resin 5. The lower side 13 of the flat side face 9 of the sealing resin 5 and the lower face 12 of the lead stopper 11 are located on almost the same plane on the face vertical to the optical axis (A) of the LED chip 3. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は半導体装置に関するものであり、詳しくは、略平行に配設され複数本のリードフレームの一方の端部に載設された半導体発光素子あるいは半導体受光素子を封止樹脂によって樹脂封止した半導体装置に関する。   The present invention relates to a semiconductor device, and more specifically, a semiconductor light-emitting element or a semiconductor light-receiving element disposed substantially parallel and mounted on one end of a plurality of lead frames is sealed with a sealing resin. The present invention relates to a semiconductor device.

半導体装置の発光源となる半導体発光素子（例えば、ＬＥＤチップ）は、一辺の長さが０．５ｍｍ程度の６面体（サイコロ状）の形状をしており、小さくて発光光量が少なく、点光源に近い光学特性を有している。したがって、このような特性のＬＥＤチップを光源にした半導体装置を設計・製作するにあたっては、ＬＥＤチップの活性層で発光された光の量に対するＬＥＤチップから出射される光の量の割合（光取り出し効率）を高め、且つＬＥＤチップから出射されてＬＥＤランプの外部（大気中）に放出される光を一方向に集めてＬＥＤの軸上光度を高めるような手法が施されている。   A semiconductor light-emitting element (for example, an LED chip) serving as a light-emitting source of a semiconductor device has a hexahedron (dice-like) shape with a side length of about 0.5 mm, is small, has a small amount of light emission, and is a point light source. It has optical characteristics close to. Therefore, when designing and manufacturing a semiconductor device using an LED chip having such characteristics as a light source, the ratio of the amount of light emitted from the LED chip to the amount of light emitted from the active layer of the LED chip (light extraction) The efficiency is improved, and the light emitted from the LED chip and emitted to the outside (in the atmosphere) of the LED lamp is collected in one direction to increase the on-axis luminous intensity of the LED.

具体的には、リードフレームやプリント基板等の基材に実装されたＬＥＤチップを透光性樹脂によって樹脂封止するものである。その場合、透光性樹脂はＬＥＤチップを水分、塵埃及びガス等の外部環境から保護し、且つボンディングワイヤを振動及び衝撃等の機械的応力から保護する。また、ＬＥＤチップの光出射面と透光性樹脂とが界面を形成することになるため、ＬＥＤチップの光出射面を形成する半導体材料の屈折率に近い屈折率の透光性樹脂を採用することによってＬＥＤチップの発光光を透光性樹脂内に効率良く導入することができる。   Specifically, an LED chip mounted on a base material such as a lead frame or a printed board is resin-sealed with a translucent resin. In that case, the translucent resin protects the LED chip from an external environment such as moisture, dust and gas, and protects the bonding wire from mechanical stresses such as vibration and impact. In addition, since the light emitting surface of the LED chip and the light transmitting resin form an interface, a light transmitting resin having a refractive index close to the refractive index of the semiconductor material forming the light emitting surface of the LED chip is employed. As a result, the light emitted from the LED chip can be efficiently introduced into the translucent resin.

また、ＬＥＤチップの発光光の出射方向の位置に透光性樹脂を球面または非球面等のレンズ形状に成形することによって、ＬＥＤチップから出射されて半導体装置の外部に放出される光の集光及び／又は配光制御を行なうことができる。   Further, by forming a translucent resin into a lens shape such as a spherical surface or an aspherical surface at a position in the emission direction of the emitted light of the LED chip, the light emitted from the LED chip and emitted to the outside of the semiconductor device is condensed. And / or light distribution control.

ところで、リードフレームの一方の端面にＬＥＤチップを実装し、該ＬＥＤチップを砲弾形に成形した透光性樹脂で樹脂封止するタイプの半導体装置には、従来種々の形状のものが提案されており、それらを回路基板に実装することによって夫々の半導体装置の優れた点や問題点が明らかになる。   By the way, various types of semiconductor devices have been proposed in the past in which an LED chip is mounted on one end surface of a lead frame and the LED chip is resin-sealed with a translucent resin formed into a bullet shape. By mounting them on a circuit board, the excellent points and problems of each semiconductor device become clear.

図６は従来の半導体装置を回路基板に実装した状態を示したものである。この半導体装置５０は、平行に配置された一対のリードフレーム５１ａ、５１ｂの一方の端面に導電性部材（図示せず）を介してＬＥＤチップ５２が載設され、ＬＥＤチップ５２の下側電極と該ＬＥＤチップ５２が載設されたリードフレーム５１ａとの電気的導通が図られている。ＬＥＤチップ５２の上側電極はボンディングワイヤ５３を介して他方のリードフレーム５１ｂの端面に接続され、ＬＥＤチップ５２の上側電極とボンディングワイヤ５３が接続されたリードフレーム５１ｂとの電気的導通が図られている。そしてＬＥＤチップ５２とボンディングワイヤ５３とを覆うように透光性樹脂５４によって樹脂封止されている。   FIG. 6 shows a state where a conventional semiconductor device is mounted on a circuit board. In this semiconductor device 50, an LED chip 52 is mounted on one end face of a pair of lead frames 51a and 51b arranged in parallel via a conductive member (not shown), and a lower electrode of the LED chip 52 and Electrical continuity with the lead frame 51a on which the LED chip 52 is mounted is achieved. The upper electrode of the LED chip 52 is connected to the end face of the other lead frame 51b through the bonding wire 53, and electrical connection between the upper electrode of the LED chip 52 and the lead frame 51b to which the bonding wire 53 is connected is achieved. Yes. And it is resin-sealed with a translucent resin 54 so as to cover the LED chip 52 and the bonding wire 53.

この場合、リードフレームに載設されたＬＥＤチップ及び架空配線されたボンディングワイヤを透光性樹脂で樹脂封止する一般的な方法は、夫々の端面にＬＥＤチップ及びボンディングワイヤが載設されたリードフームをリードフレーム固定治具に取り付けると共に、注型金型に設けられた注型キャビティに透光性樹脂を注入する。そして、リードフレーム固定治具を注型金型の上方から徐々に下降させてリードフレームのＬＥＤチップが実装された部分を注型キャビティに挿入して透光性樹脂内に埋設させる。注型キャビティとリードフレームとは注型金型にリードフレーム固定治具を固定することによって所定の位置関係を保持することになる。そして、その状態で透光性樹脂を加熱硬化させ、硬化後に注型キャビティから取り出すと半導体装置が完成する（例えば、特許文献１参照。）。   In this case, a general method of resin-sealing the LED chip mounted on the lead frame and the overhead wired bonding wire with a translucent resin is a lead humor in which the LED chip and the bonding wire are mounted on each end face. Is attached to the lead frame fixing jig, and a translucent resin is injected into a casting cavity provided in the casting mold. Then, the lead frame fixing jig is gradually lowered from above the casting mold, and the portion of the lead frame where the LED chip is mounted is inserted into the casting cavity and embedded in the translucent resin. The casting mold cavity and the lead frame maintain a predetermined positional relationship by fixing a lead frame fixing jig to the casting mold. Then, the translucent resin is heated and cured in that state, and after curing, the semiconductor device is completed (see, for example, Patent Document 1).

また、砲弾形に樹脂封止された上記半導体装置５０を回路基板５５に実装する場合は、回路基板５５のリード孔５６にリードフレーム５１ａ、５１ｂ部を挿入し、砲弾形に成形された透光性樹脂５４の底面が回路基板５５の部品面（部品を実装する側の面）５７に当接した状態で半導体装置５０を回路基板上に載置する。そして、回路基板５５の半導体装置５０が載置された部品面５７の反対面（はんだ面５８）にフラックスを塗布し、はんだ面５８を噴流はんだ槽等に浸漬してリードフレーム５１ａ、５１ｂを回路基板５５にはんだ５９によってはんだ付け接続する。   Further, when mounting the semiconductor device 50 resin-sealed in a bullet shape on the circuit board 55, the lead frames 51 a and 51 b are inserted into the lead holes 56 of the circuit board 55, and the translucent shaped into the bullet shape is inserted. The semiconductor device 50 is placed on the circuit board in a state where the bottom surface of the functional resin 54 is in contact with the component surface (surface on which components are mounted) 57 of the circuit substrate 55. Then, a flux is applied to the surface (solder surface 58) opposite to the component surface 57 on which the semiconductor device 50 of the circuit board 55 is placed, and the solder surface 58 is immersed in a jet solder bath or the like to connect the lead frames 51a and 51b to the circuit. The substrate 55 is soldered and connected with solder 59.

図７は従来の他の半導体装置を回路基板に実装した状態を示したものである。この半導体装置７０は、構成及び製造方法は上記図６で示した半導体装置５０とほぼ同様であるが、封止樹脂７１から延出したリードフレーム７２ａ、７２ｂに該リードフレーム７２ａ、７２ｂの延出方向に垂直な方向に突出したタイバー７３が形成されていることが異なる（例えば、特許文献２参照。）。そしてこの半導体装置７０を回路基板７４に実装する場合は、回路基板７４のリード孔７５にリードフレーム７２ａ、７２ｂを挿入し、リードフレーム７２ａ、７２ｂに成形されたタイバー７３が回路基板７４の部品面７６に当接した状態で半導体装置７０を回路基板７４上に載置する。そして、回路基板７４のはんだ面７７にフラックスを塗布し、はんだ面を噴流はんだ槽等に浸漬してリードフレーム７２ａ、７２ｂを回路基板７４にはんだ７８によってはんだ付け接続する。   FIG. 7 shows a state in which another conventional semiconductor device is mounted on a circuit board. This semiconductor device 70 has substantially the same configuration and manufacturing method as the semiconductor device 50 shown in FIG. 6, but the lead frames 72a and 72b extend to the lead frames 72a and 72b extending from the sealing resin 71. A difference is that a tie bar 73 protruding in a direction perpendicular to the direction is formed (see, for example, Patent Document 2). When the semiconductor device 70 is mounted on the circuit board 74, the lead frames 72 a and 72 b are inserted into the lead holes 75 of the circuit board 74, and the tie bars 73 formed on the lead frames 72 a and 72 b are the component surfaces of the circuit board 74. The semiconductor device 70 is placed on the circuit board 74 in a state where it abuts on the circuit board 76. Then, flux is applied to the solder surface 77 of the circuit board 74, and the solder surface is immersed in a jet solder bath or the like, and the lead frames 72a and 72b are soldered and connected to the circuit board 74 by the solder 78.

図８は従来の更なる他の半導体装置を回路基板に実装した状態を示したものである。この半導体装置９０は、構成は上記図６及び図７で示した半導体装置５０、７０とほぼ同様であるが、封止樹脂９１の底面にリードフレーム９２ａ、９２ｂの延出位置を通過してリードフレーム９２ａ、９２ｂの配列方向に延びる貫通溝９３が形成されていることが異なる。また、製造方法は、ＬＥＤチップ及びボンディングワイヤが載設されたリードフレームの端部を成形金型にセットし、封止樹脂によるトランスファー成形方法によってインサート成形される（例えば、特許文献３参照。）。そしてこの半導体装置９０を回路基板９４に実装する場合は、回路基板９４のリード孔９５にリードフレーム９２ａ、９２ｂを挿入し、貫通溝９３で分離された封止樹脂９１の最底面９６が回路基板９４の部品面９７に当接した状態に半導体装置９０を回路基板９４上に載置する。そして、回路基板９４のはんだ面９８にフラックスを塗布し、はんだ面９８を噴流はんだ槽等に浸漬してリードフレーム９２ａ、９２ｂを回路基板９４にはんだ９９によってはんだ付け接続する。
特開２００２−９３４８号公報 特開２００４−２４１４０１号公報 特開２００１−２１０８７６号公報 FIG. 8 shows a state in which another conventional semiconductor device is mounted on a circuit board. This semiconductor device 90 has substantially the same configuration as the semiconductor devices 50 and 70 shown in FIGS. 6 and 7, but the lead passes through the extended positions of the lead frames 92a and 92b on the bottom surface of the sealing resin 91. A difference is that a through groove 93 extending in the arrangement direction of the frames 92a and 92b is formed. In addition, in the manufacturing method, the end portion of the lead frame on which the LED chip and the bonding wire are mounted is set in a molding die, and insert molding is performed by a transfer molding method using a sealing resin (see, for example, Patent Document 3). . When the semiconductor device 90 is mounted on the circuit board 94, the lead frames 92 a and 92 b are inserted into the lead holes 95 of the circuit board 94, and the bottom surface 96 of the sealing resin 91 separated by the through groove 93 is the circuit board. The semiconductor device 90 is placed on the circuit board 94 in contact with the component surface 97 of 94. Then, flux is applied to the solder surface 98 of the circuit board 94, and the solder surface 98 is immersed in a jet solder bath or the like, and the lead frames 92a and 92b are soldered and connected to the circuit board 94 with solder 99.
JP 2002-9348 A JP 2004-241401 A JP 2001-210876 A

しかしながら、上記図６に示した半導体装置５０は、製造上リードフレーム５１ａ、５１ｂには封止樹脂５４がリードフレーム５１ａ、５１ｂの表面に沿って這い上がってできた樹脂フィレット６０が形成され、回路基板５５のリード孔５６の部品面６７側の開口部６１を樹脂フィレット６０が塞いだ状態でリードフレーム５１ａ、５１ｂが回路基板５５にはんだ付けされる。   However, in the semiconductor device 50 shown in FIG. 6, a resin fillet 60 is formed on the lead frames 51a and 51b due to the sealing resin 54 scooping up along the surfaces of the lead frames 51a and 51b. The lead frames 51 a and 51 b are soldered to the circuit board 55 with the resin fillet 60 closing the opening 61 on the component surface 67 side of the lead hole 56 of the board 55.

ところが、はんだ付けを行なう前に塗布されたフラックスが一方の開口部を樹脂フィレットで塞がれたリード孔内に残留しており、他方のリード孔開口部がはんだ付けによって塞がれるときの熱によってリード孔内に閉じ込められたフラックスが気化してリード孔内の気圧が上昇し、高圧フラックスガスはリード孔を塞ぐ溶融したはんだ付け部から外部に噴出することになる。その結果、はんだ付け部にブローホールを生じることになり、はんだ付けの信頼性を損なう要因となるものである。   However, the heat applied when the flux applied before soldering remains in the lead hole in which one opening is blocked by the resin fillet and the other lead hole opening is blocked by soldering. As a result, the flux confined in the lead hole is vaporized and the pressure in the lead hole is increased, and the high-pressure flux gas is ejected to the outside from the melted soldering portion that closes the lead hole. As a result, a blow hole is generated in the soldering portion, which is a factor that impairs the reliability of soldering.

また、上記図７に示した半導体装置７０は、封止樹脂７１から延出したリードフレーム７２ａ、７２ｂに形成されたタイバー７３が回路基板７４の部品面７６に当接した状態ではんだ付けされるためにブローホールの問題は生じない。但し、半導体装置７０を該半導体装置７０の光軸Ａが回路基板面７４に垂直な方向を向くように回路基板７４に実装する場合、リードフレーム７２ａ、７２ｂの配列方向（Ｙ―Ｙ方向）は半導体装置７０の傾きが生じないために光軸Ａずれは生じない。それに対し、リードフレーム７２ａ、７２ｂの配列方向に直角な方向（Ｘ―Ｘ方向）は半導体装置７０の傾きが生じ易いために光軸Ａずれが生じ易くなる。その結果、半導体装置の照射方向が正規の方向とはならず、よって照射方向の再現性も確保できないために照明品位に劣るものとなってしまう。   Further, the semiconductor device 70 shown in FIG. 7 is soldered in a state in which the tie bars 73 formed on the lead frames 72 a and 72 b extending from the sealing resin 71 are in contact with the component surface 76 of the circuit board 74. Therefore, the problem of blow holes does not occur. However, when the semiconductor device 70 is mounted on the circuit board 74 so that the optical axis A of the semiconductor device 70 faces the direction perpendicular to the circuit board surface 74, the arrangement direction (YY direction) of the lead frames 72a and 72b is Since the semiconductor device 70 is not tilted, the optical axis A is not shifted. On the other hand, in the direction perpendicular to the arrangement direction of the lead frames 72a and 72b (XX direction), the semiconductor device 70 is likely to be inclined, so that the optical axis A is likely to be shifted. As a result, the irradiation direction of the semiconductor device does not become a normal direction, and therefore the reproducibility of the irradiation direction cannot be ensured, resulting in poor illumination quality.

また、上記図８に示した半導体装置９０は、封止樹脂９１の最底面９６が回路基板９４の部品面９７に当接した状態ではんだ付けされるためにはんだ付け部が貫通溝９３内に形成され、ブローホールの問題は生じない。同時に半導体装置９０が該半導体装置９０の最底面９６が回路基板９４の部品面９７に平面状に接するように回路基板９４に実装されているために回路基板９４に対する光軸ずれはほとんど生じない。但し、貫通溝９３を形成するため、変形加工した金型を用いたトランスファー成形やインジェクション成形によるか、キャスティングによる成形後に溝部を除くことになる。封止樹脂の成形方法がトランスファー成形方法によるインサート成形によると、成形金型に高い精度が要求されると共に必要な成形金型の型数が多くなり、樹脂封止部分に対してランナなどの樹脂封止に寄与しない部分の樹脂も必要となる。従って、金型費及び材料費が高くなり製造コストが上昇することになる。更に、トランスファー成形時の樹脂の成形圧力によって電極からボンディングワイヤが剥離したり、ボンディングワイヤが断線したり、ボンディングワイヤの変形によって短絡したりすることによる電気的な不具合を生じる可能性がある。   Further, since the semiconductor device 90 shown in FIG. 8 is soldered in a state where the bottom surface 96 of the sealing resin 91 is in contact with the component surface 97 of the circuit board 94, the soldering portion is in the through groove 93. Formed and no blowhole problems occur. At the same time, since the semiconductor device 90 is mounted on the circuit board 94 so that the bottom surface 96 of the semiconductor device 90 is in contact with the component surface 97 of the circuit board 94 in a planar manner, optical axis deviation with respect to the circuit board 94 hardly occurs. However, in order to form the through groove 93, the groove portion is removed by transfer molding or injection molding using a deformed mold or after molding by casting. When the molding method of the sealing resin is the insert molding by the transfer molding method, a high precision is required for the molding die, and the number of molding molds required is increased. A portion of resin that does not contribute to sealing is also required. Accordingly, the mold cost and the material cost are increased, and the manufacturing cost is increased. Furthermore, there is a possibility that an electrical failure may occur due to peeling of the bonding wire from the electrode due to the molding pressure of the resin during transfer molding, disconnection of the bonding wire, or short-circuiting due to deformation of the bonding wire.

そこで、本発明は上記問題に鑑みて創案なされたもので、その目的とするところは、回路基板に実装する半導体装置において、回路基板にはんだ付けする際にはんだ付け部にブローホールが発生することなく、回路基板に対して光軸ずれを低減した実装が可能であり、安価な製造コストで信頼性の高い半導体装置を提供することにある。   Therefore, the present invention was devised in view of the above problems, and the object of the present invention is to generate a blow hole in a soldered portion when soldering to a circuit board in a semiconductor device mounted on the circuit board. In addition, an object of the present invention is to provide a highly reliable semiconductor device that can be mounted with reduced optical axis deviation on a circuit board and that is inexpensive to manufacture.

上記課題を解決するために、本発明の請求項１に記載された発明は、略平行に配設され複数本のリードフレームのうちの少なくとも一本のリードフレームの端部に半導体素子が載設され、前記半導体素子の電極と該半導体素子が載設されたリードフレーム以外の少なくとも一本のリードフレームの端部とがボンディングワイヤによって架空配線され、前記半導体素子と前記ボンディングワイヤとを含む前記複数本のリードフレームの端部が封止樹脂によって樹脂封止された半導体装置であって、
前記封止樹脂は、平側面と、前記リードフレームが延出した底面と、前記平側面と前記底面との交線部を有し、
前記底面は、前記半導体素子の光軸に垂直な面に対して所定の角度で傾斜し、
前記底面において、前記交線部が前記リードフレームの延出方向に位置することを特徴とするものである。 In order to solve the above-mentioned problem, according to a first aspect of the present invention, a semiconductor element is mounted on an end portion of at least one lead frame of a plurality of lead frames arranged substantially in parallel. The plurality of electrodes including the semiconductor element and the bonding wire, wherein an electrode of the semiconductor element and an end of at least one lead frame other than the lead frame on which the semiconductor element is mounted are aerial wired by a bonding wire A semiconductor device in which an end portion of a lead frame is sealed with a sealing resin,
The sealing resin has a flat side surface, a bottom surface from which the lead frame extends, and an intersection portion of the flat side surface and the bottom surface,
The bottom surface is inclined at a predetermined angle with respect to a plane perpendicular to the optical axis of the semiconductor element;
In the bottom surface, the intersecting line portion is located in the extending direction of the lead frame.

また、本発明の請求項２に記載された発明は、請求項１において、前記封止樹脂の底面から延出したリードフレームのうちの少なくとも一本のリードフレームには、該リードフレームの延出方向に垂直な方向に突出したリードストッパーが形成されており、前記封止樹脂は、前記交線部と前記リードストッパーの下面とは前記半導体素子の光軸に垂直な面上の略同一平面上に位置していることを特徴とするものである。   Further, in the invention described in claim 2 of the present invention, in claim 1, at least one of the lead frames extending from the bottom surface of the sealing resin has an extension of the lead frame. A lead stopper projecting in a direction perpendicular to the direction is formed, and the sealing resin is formed on a substantially coplanar surface on a plane perpendicular to the optical axis of the semiconductor element between the intersecting line portion and the lower surface of the lead stopper. It is characterized by being located.

また、本発明の請求項３に記載された発明は、請求項１または２の何れか１項において、前記半導体素子は、ＬＥＤチップ、フォトダイオードチップ、ＰＩＮフォトダイオードチップ及びフォトトランジスタチップの群の中から選ばれた少なくとも１つであることを特徴とするものである。   According to a third aspect of the present invention, in any one of the first or second aspect, the semiconductor element is an LED chip, a photodiode chip, a PIN photodiode chip, or a phototransistor chip. It is at least one selected from the inside.

また、本発明の請求項４に記載された発明は、請求項１〜３の何れか１項において、前記樹脂封止は、キャスティングによって行なわれることを特徴とするものである。   According to a fourth aspect of the present invention, in any one of the first to third aspects, the resin sealing is performed by casting.

本発明の半導体装置は、半導体素子とボンディングワイヤと複数本のリードフレームの一方の端部とを封止樹脂によって樹脂封止した半導体装置において、封止樹脂の底面を半導体素子の光軸に垂直な面に対して所定の角度で傾斜させ、封止樹脂の底面から延出したリードフレームのうちの少なくとも一本のリードフレームに、該リードフレームの延出方向に垂直な方向に突出したリードストッパーを形成し、封止樹脂の底面縁部の一部の線部分と前記リードストッパーの下面とが半導体素子の光軸に垂直な面上の略同一平面上に位置するようにした。   The semiconductor device of the present invention is a semiconductor device in which a semiconductor element, a bonding wire, and one end of a plurality of lead frames are sealed with a sealing resin, and the bottom surface of the sealing resin is perpendicular to the optical axis of the semiconductor element. A lead stopper projecting in a direction perpendicular to the direction in which the lead frame extends from at least one of the lead frames extending from the bottom surface of the sealing resin. The part of the bottom edge of the sealing resin and the lower surface of the lead stopper are positioned on substantially the same plane on the plane perpendicular to the optical axis of the semiconductor element.

すると、半導体装置を回路基板に実装する場合、半導体装置は回路基板に対して、封止樹脂の底面縁部の一部の線部分との接触と、リードストッパーの下面との接触との２箇所で接触することになる。   Then, when the semiconductor device is mounted on the circuit board, the semiconductor device is in contact with the circuit board at two locations, that is, contact with a part of the line portion of the bottom edge of the sealing resin and contact with the lower surface of the lead stopper. Will come in contact.

その結果、回路基板に対する半導体装置の光軸ずれはほとんど生じることはない。また、封止樹脂の底面は底面縁部の一部の線部分のみが回路基板に接触しており、その他の部分は回路基板の上方に浮いた状態に支持されている。従って、製造過程でリードフレームの表面に沿って封止樹脂が這い上がって樹脂フィレットが形成されたとしても、実装時に回路基板のリード孔の開口部を樹脂フィレットが塞ぐことはない。よって、はんだ付け部におけるブローホールの発生はなく、はんだ接合の高い信頼性を確保することができる。   As a result, the optical axis of the semiconductor device with respect to the circuit board hardly occurs. In addition, the bottom surface of the sealing resin is supported such that only a part of the line portion of the bottom edge is in contact with the circuit board, and the other part is floated above the circuit board. Therefore, even if the sealing resin crawls up along the surface of the lead frame during the manufacturing process to form a resin fillet, the resin fillet does not block the opening of the lead hole of the circuit board during mounting. Therefore, no blowhole is generated in the soldering portion, and high reliability of solder joint can be ensured.

更に、樹脂封止は注型成形（キャスティング）によって行なわれるものである。そのため、トランスファー成形に比べて金型数が少なく金型精度もトランスファー成形金型ほどの高い精度は要求されない。よって、注型金型が安価で且つ短期間で作製でき、成形時に使用する成形樹脂にむだを生じることがない。また、架空配線されたボンディングワイヤが成形時にトランスファー成形の成形圧力のような力をうけることがない。そのため、製造体制を迅速に構築できると共に製造コストを安価にでき、電気的に信頼性の高い半導体装置を実現することが可能となる。   Furthermore, the resin sealing is performed by casting (casting). Therefore, the number of molds is small compared to transfer molding, and the mold accuracy is not required to be as high as that of transfer molding dies. Therefore, the casting mold can be manufactured at a low cost and in a short period of time, and the molding resin used at the time of molding will not be wasted. In addition, the overhead wired bonding wires are not subjected to forces such as transfer molding pressure during molding. Therefore, it is possible to quickly build a manufacturing system, reduce manufacturing costs, and realize a highly reliable semiconductor device.

以下、この発明の好適な実施形態を図１から図５を参照しながら、詳細に説明する（同一部分については同じ符号を付す）。尚、以下に述べる実施形態は、本発明の好適な具体例であるから、技術的に好ましい種々の限定が付されているが、本発明の範囲は、以下の説明において特に本発明を限定する旨の記載がない限り、これらの実施形態に限られるものではない。   Hereinafter, preferred embodiments of the present invention will be described in detail with reference to FIG. 1 to FIG. 5 (the same parts are given the same reference numerals). The embodiments described below are preferable specific examples of the present invention, and thus various technically preferable limitations are given. However, the scope of the present invention particularly limits the present invention in the following description. Unless stated to the effect, the present invention is not limited to these embodiments.

図１は本発明の半導体装置に係わる実施形態の斜視図、図２は断面図である。本実施形態は上記「背景技術」で説明した従来例の構成と同様の部分もあるが、再度詳細に説明する。   FIG. 1 is a perspective view of an embodiment of a semiconductor device according to the present invention, and FIG. 2 is a sectional view. Although the present embodiment has the same parts as the configuration of the conventional example described in the “Background Art”, it will be described in detail again.

本実施形態の半導体装置１は、略平行に配置された一対のリードフレーム２ａ、２ｂの一方の端面に導電性部材（図示せず）を介してＬＥＤチップ３が載設され、ＬＥＤチップ３の下側電極と該ＬＥＤチップ３が載設されたリードフレーム２ａとの電気的導通が図られている。また、一方の端部がＬＥＤチップ３の上側電極に接続されたボンディングワイヤ４の他方の端部が他方のリードフレーム２ｂの端面に接続され、ＬＥＤチップ３の上側電極とボンディングワイヤ４が接続されたリードフレーム２ｂとがボンディングワイヤ４を介して電気的導通が図られている。そしてＬＥＤチップ３とボンディングワイヤ４とを覆うように封止樹脂５によって樹脂封止されている。   In the semiconductor device 1 of the present embodiment, the LED chip 3 is mounted on one end face of a pair of lead frames 2a and 2b arranged substantially in parallel via a conductive member (not shown). Electrical conduction between the lower electrode and the lead frame 2a on which the LED chip 3 is mounted is achieved. The other end of the bonding wire 4 whose one end is connected to the upper electrode of the LED chip 3 is connected to the end face of the other lead frame 2b, and the upper electrode of the LED chip 3 and the bonding wire 4 are connected. The lead frame 2 b is electrically connected to the lead frame 2 b through the bonding wire 4. The resin is sealed with a sealing resin 5 so as to cover the LED chip 3 and the bonding wire 4.

なお、ＬＥＤチップの替わりに、フォトダイオードチップ、ＰＩＮフォトダイオードチップ、フォトトランジスタチップなどの半導体受光素子を使用することも可能である。   Instead of the LED chip, a semiconductor light receiving element such as a photodiode chip, a PIN photodiode chip, or a phototransistor chip can be used.

封止樹脂はエポキシ樹脂、シリコーン樹脂等の透光性樹脂からなっており、ＬＥＤチップ３を水分、塵埃及びガス等の外部環境から保護し、且つボンディングワイヤ４を振動及び衝撃等の機械的応力から保護する。また、ＬＥＤチップ３の光出射面と封止樹脂５とが界面を形成することになるため、ＬＥＤチップ３の光出射面を形成する半導体材料の屈折率に近い屈折率の封止樹脂５を採用することによってＬＥＤチップ３の発光光を封止樹脂５内に効率良く導入することができる。   The sealing resin is made of a translucent resin such as an epoxy resin or a silicone resin, protects the LED chip 3 from an external environment such as moisture, dust and gas, and mechanical stress such as vibration and impact. Protect from. Further, since the light emitting surface of the LED chip 3 and the sealing resin 5 form an interface, the sealing resin 5 having a refractive index close to the refractive index of the semiconductor material forming the light emitting surface of the LED chip 3 is used. By adopting, the light emitted from the LED chip 3 can be efficiently introduced into the sealing resin 5.

封止樹脂５は台座部６と凸状レンズ部７とからなり、凸状レンズ部７にはＬＥＤチップ３の光出射方向の前方に球面または非球面等のレンズ面８が形成されており、ＬＥＤチップ３から出射されて半導体装置１の外部に放出される光の集光及び／又は配光制御が行なわれる。   The sealing resin 5 includes a pedestal portion 6 and a convex lens portion 7, and a lens surface 8 such as a spherical surface or an aspheric surface is formed on the convex lens portion 7 in front of the light emitting direction of the LED chip 3. Condensation and / or light distribution control of light emitted from the LED chip 3 and emitted to the outside of the semiconductor device 1 is performed.

封止樹脂５の台座部６は、側面の少なくとも一部がＬＥＤチップ３の光軸Ａに対して略平行な平側面９からなり、底面（レンズ面８と対向する側の面）１０はＬＥＤチップ３の光軸Ａに垂直な面Ｂに対して所定の角度αで傾いている。   The pedestal portion 6 of the sealing resin 5 includes a flat side surface 9 having at least a part of the side surface substantially parallel to the optical axis A of the LED chip 3, and a bottom surface (surface facing the lens surface 8) 10 is an LED. It is inclined at a predetermined angle α with respect to a plane B perpendicular to the optical axis A of the chip 3.

封止樹脂５の底面１０から延出した一対のリードフレーム２ａ、２ｂのうち、一方のリードフレーム２ａには封止樹脂５の底面１０の延出部近傍に該リードフレーム２ａの延出方向に垂直な方向に突出したリードストッパー１１が形成されており、リードストッパー１１の下面１２と平側面９の下辺１３とはＬＥＤチップ３の光軸Ａに垂直な面Ｂ上の略同一平面上に位置している。また、平側面９は、その下辺１３が、リードストッパー１１の突出方向（下面１２の長手方向）に対して、垂直となるように形成されている。   Of the pair of lead frames 2 a and 2 b extending from the bottom surface 10 of the sealing resin 5, one lead frame 2 a is near the extension portion of the bottom surface 10 of the sealing resin 5 in the extending direction of the lead frame 2 a. A lead stopper 11 protruding in a vertical direction is formed, and the lower surface 12 of the lead stopper 11 and the lower side 13 of the flat side surface 9 are located on substantially the same plane on the surface B perpendicular to the optical axis A of the LED chip 3. is doing. Further, the flat side surface 9 is formed such that the lower side 13 thereof is perpendicular to the protruding direction of the lead stopper 11 (longitudinal direction of the lower surface 12).

なお、リードストッパー１１は半導体装置１の極性マークとして活用することもできる。   The lead stopper 11 can also be used as a polarity mark of the semiconductor device 1.

以上、本発明の半導体装置に係わる実施形態を説明してきたが、次に製造工程について図３を参照しながら説明する。   The embodiment of the semiconductor device according to the present invention has been described above. Next, the manufacturing process will be described with reference to FIG.

まず、（ａ）の工程において、複数個の注型キャビティ２０を設けた注型金型２１を作製する。夫々の注型キャビティ２０は半導体装置の樹脂封止の形状に対応した凹形状を有しており、夫々の注型キャビティ２０の中心軸Ｃが略平行に一直線上に所定の間隔を保った状態に配置されている。そして、上記構成の注型金型２１を注型キャビティ２０の中心軸Ｃが水平面Ｄに垂直な線Ｅに対して角度α傾いた状態に支持する。このとき、注型キャビティ２０の傾斜方向は、図１及び図２で示した封止樹脂５の平側面９に対応する面が傾斜した注型キャビティ２０の下方に位置するような方向となっている。   First, in the step (a), a casting mold 21 provided with a plurality of casting cavities 20 is produced. Each casting cavity 20 has a concave shape corresponding to the shape of the resin sealing of the semiconductor device, and the center axis C of each casting cavity 20 is substantially parallel and kept at a predetermined interval on a straight line. Is arranged. The casting mold 21 configured as described above is supported in a state where the center axis C of the casting cavity 20 is inclined at an angle α with respect to a line E perpendicular to the horizontal plane D. At this time, the inclination direction of the casting cavity 20 is such that the surface corresponding to the flat side surface 9 of the sealing resin 5 shown in FIGS. 1 and 2 is positioned below the inclined casting cavity 20. Yes.

次に、（ｂ）の工程において、注型キャビティ２０内にディスペンサ（液体定量吐出装置）によって所定量の封止樹脂５を注入する。封止樹脂５の注入量は、図１及び図２で示した封止樹脂５の平側面９の下辺１３に対応する注型キャビティ２０の開口縁部２２に封止樹脂５の上面が略一致するように設定される。   Next, in the step (b), a predetermined amount of the sealing resin 5 is injected into the casting cavity 20 by a dispenser (liquid dispensing device). The injection amount of the sealing resin 5 is substantially the same as the opening edge 22 of the casting cavity 20 corresponding to the lower side 13 of the flat side surface 9 of the sealing resin 5 shown in FIGS. 1 and 2. Set to do.

次に、（ｃ）の工程において、夫々の端面にＬＥＤチップ３及びボンディングワイヤ４が載設された一対のリードフーム２ａ、２ｂが複数個タイバー２３を介して平行に一直線上に所定の間隔を保つように配置された多数個取りリードフレーム２４を準備する。そして前記多数個取りリードフレーム２４を注型金型２１の上方から徐々に下降させて夫々の一対のリードフレーム２ａ、２ｂのＬＥＤチップ３及びボンディングワイヤ４が載設された部分を注型キャビティ２０に挿入して封止樹脂５中に埋設させる。このとき、注型金型２１に対する多数個取りリードフレーム２４の方向及び深さは、ＬＥＤチップ３の光軸Ａと注型キャビティ２０の中心軸Ｃとが略一致し、リードストッパー１１が傾斜した注型キャビティ２０の上方に位置し、リードストッパー１１の下面１２と封止樹脂５の平側面９の下辺１３に対応する注型キャビティ２０の開口縁部２２とが注型キャビティ２０の開口面２５上の略同一平面上に位置するようになっている。   Next, in the step (c), a plurality of pairs of lead foms 2a and 2b each having the LED chip 3 and the bonding wire 4 mounted on their respective end faces are maintained in parallel on a straight line via a tie bar 23. A multi-piece lead frame 24 arranged as described above is prepared. Then, the multiple lead frame 24 is gradually lowered from above the casting mold 21 so that the portion where the LED chip 3 and the bonding wire 4 of the pair of lead frames 2a and 2b are mounted is cast cavity 20. And embedded in the sealing resin 5. At this time, the direction and depth of the multi-cavity lead frame 24 with respect to the casting mold 21 are substantially the same as the optical axis A of the LED chip 3 and the central axis C of the casting cavity 20, and the lead stopper 11 is inclined. An opening surface 25 of the casting cavity 20 is located above the casting cavity 20, and the opening edge 22 of the casting cavity 20 corresponding to the lower surface 13 of the lead stopper 11 and the lower side 13 of the flat side surface 9 of the sealing resin 5. It is located on the substantially same plane above.

最後に、（ｄ）の工程において、封止樹脂５を加熱硬化した後、注型キャビティ２０から多数個取りリードフレーム２４を取り外してタイバーカットを施して分離すると、図１及び図２に示すような半導体装置が完成する。   Finally, in the step (d), after the sealing resin 5 is heat-cured, the lead frame 24 is removed from the casting cavity 20 and separated by tie bar cutting, as shown in FIG. 1 and FIG. A simple semiconductor device is completed.

上記製造方法の他に、注型キャビティを注型金型の底面の垂直線に対して該注型キャビティの中心軸を予め所定の角度に傾けた状態で設け、後の工程を注型金型を直接水平面に置いた状態で進めることができるようにすることも可能である。   In addition to the above manufacturing method, the casting cavity is provided in a state where the center axis of the casting cavity is inclined at a predetermined angle with respect to the vertical line of the bottom surface of the casting mold, and the subsequent process is performed. It is also possible to make it possible to proceed in a state where is placed directly on a horizontal plane.

また、同様に上記製造工程において、注型キャビティは直接注型金型に掘り込まれていたが、複数個のキャビティが設けられた多連の樹脂型を使用することもできる。それにより、キャビティ内面に封止樹脂や離型剤などの汚れが付着したときに簡単に交換でき、多数の半導体装置を製造するにあたって、表面状態が良好な封止樹脂を有する半導体装置を歩留まり良く大量に製造することができる。   Similarly, in the above manufacturing process, the casting cavity is directly dug into the casting mold, but a multiple resin mold provided with a plurality of cavities can also be used. As a result, when dirt such as sealing resin or a release agent adheres to the cavity inner surface, it can be easily replaced, and in manufacturing a large number of semiconductor devices, a semiconductor device having a sealing resin with a good surface condition can be obtained with a high yield. Can be manufactured in large quantities.

樹脂型を使用する場合も、直接キャビティを設ける注型金型と同様に、キャビティを樹脂型に対して該キャビティの中心軸の角度を適宜設定した状態に設けることができる。   In the case of using a resin mold, the cavity can be provided in a state in which the angle of the central axis of the cavity is appropriately set with respect to the resin mold, similarly to the casting mold in which the cavity is directly provided.

図４及び図５に、上記製造工程を経て製造された半導体装置を回路基板に実装したときの状態を示している。回路基板３０のリード孔３１に回路基板３０の部品面３２側から半導体装置１のリードフレーム２ａ、２ｂが挿入され、回路基板３０のはんだ面３３側からリードフレーム２ａ、２ｂとリード孔３１に形成されたランドとがはんだ付けされてはんだ３４による接合がなされている。   4 and 5 show a state where the semiconductor device manufactured through the above manufacturing process is mounted on a circuit board. The lead frames 2a and 2b of the semiconductor device 1 are inserted into the lead holes 31 of the circuit board 30 from the component surface 32 side of the circuit board 30 and formed in the lead frames 2a and 2b and the lead holes 31 from the solder surface 33 side of the circuit board 30. The land formed is soldered and joined by the solder 34.

このとき、半導体装置１は回路基板３０に対して、封止樹脂５の平側面９の下辺１３との線状部分の接触と、リードフレーム２ａのリードストッパー１１の下面１２との接触の２箇所で接している。従って、平側面９の下辺１３と回路基板３０との接触部でＸ−Ｘ方向の光軸Ａのずれを防止すると共に、リードストッパー下面１２と回路基板３０との接触部でＹ−Ｙ方向の光軸Ａのずれを抑えることができるため、回路基板３０に対する半導体装置１の光軸ＡずれはＸ−Ｘ方向及びＹ−Ｙ方向ともほとんど生じることはない。   At this time, the semiconductor device 1 is in contact with the circuit board 30 at two locations, the contact of the linear portion with the lower side 13 of the flat side surface 9 of the sealing resin 5 and the contact with the lower surface 12 of the lead stopper 11 of the lead frame 2a. It touches with. Accordingly, the contact portion between the lower side 13 of the flat side surface 9 and the circuit board 30 prevents the optical axis A from shifting in the XX direction, and the contact portion between the lower surface 12 of the lead stopper 12 and the circuit board 30 extends in the YY direction. Since the deviation of the optical axis A can be suppressed, the deviation of the optical axis A of the semiconductor device 1 with respect to the circuit board 30 hardly occurs in the XX direction and the YY direction.

また、封止樹脂５の底面１０は平側面９の下辺１３のみが回路基板３０に接しており、その他の部分は回路基板３０の上方に浮いた状態に支持されている。従って、製造過程でリードフレーム２ａ、２ｂの表面に沿って封止樹脂５が這い上がって樹脂フィレットが形成されたとしても、実装時に回路基板３０のリード孔３１の開口部３５を樹脂フィレットが塞ぐことはない。よって上記「背景技術」で述べたようなはんだ付け部におけるブローホールの発生はなく、はんだ接合の高い信頼性を確保することができる。   Further, only the lower side 13 of the flat side surface 9 of the bottom surface 10 of the sealing resin 5 is in contact with the circuit board 30, and the other part is supported in a state of floating above the circuit board 30. Accordingly, even if the sealing resin 5 crawls up along the surfaces of the lead frames 2a and 2b during the manufacturing process and a resin fillet is formed, the resin fillet blocks the opening 35 of the lead hole 31 of the circuit board 30 during mounting. There is nothing. Therefore, no blowhole is generated in the soldering portion as described in the above “Background Art”, and high reliability of solder joint can be ensured.

本発明の半導体装置は、上述の製造方法の他にトランスファー成形による製造方法も可能である。しかしながら、注型成形（キャスティング）で製造することによってトランスファー成形に比べて金型数が少なく金型精度もトランスファー成形金型ほどの高い精度は要求されない。よって、注型金型が安価で且つ短期間で作製でき、成形時に使用する成形樹脂にむだが生じることがない。また、架空配線されたボンディングワイヤが成形時にトランスファー成形の成形圧力のような力をうけることがない。その結果、製造体制を迅速に構築できると共に製造コストを安価にでき、電気的に信頼性の高い半導体装置を実現することが可能となる。   The semiconductor device of the present invention can be manufactured by transfer molding in addition to the above manufacturing method. However, by manufacturing by casting (casting), the number of molds is small compared to transfer molding, and the mold accuracy is not required to be as high as that of transfer molding dies. Therefore, the casting mold can be manufactured at a low cost and in a short period of time, and there is no waste in the molding resin used at the time of molding. In addition, the overhead wired bonding wires are not subjected to forces such as transfer molding pressure during molding. As a result, it is possible to quickly build a manufacturing system, reduce manufacturing costs, and realize an electrically reliable semiconductor device.

本発明の半導体装置に係わる実施形態の斜視図である。It is a perspective view of the embodiment concerning the semiconductor device of the present invention. 同じく、本発明の半導体装置に係わる実施形態の断面図である。Similarly, it is sectional drawing of embodiment concerning the semiconductor device of this invention. 同じく、本発明の半導体装置に係わる実施形態の製造工程図である。Similarly, it is a manufacturing-process figure of embodiment concerning the semiconductor device of this invention. 本発明の半導体装置に係わる実施形態を回路基板に実装したときの断面図である。It is sectional drawing when embodiment concerning the semiconductor device of this invention is mounted in the circuit board. 同じく、本発明の半導体装置に係わる実施形態を回路基板に実装したときの底面図である。Similarly, it is a bottom view when the embodiment related to the semiconductor device of the present invention is mounted on a circuit board. 従来の半導体装置を回路基板に実装したときの断面図である。It is sectional drawing when the conventional semiconductor device is mounted in the circuit board. 従来の他の半導体装置を回路基板に実装したときの断面図である。It is sectional drawing when another conventional semiconductor device is mounted on a circuit board. 従来の更に他の半導体装置を回路基板に実装したときの断面図である。It is sectional drawing when another conventional semiconductor device is mounted on a circuit board.

符号の説明Explanation of symbols

１ 半導体装置
２ａ、２ｂ リードフレーム
３ ＬＥＤチップ
４ ボンディングワイヤ
５ 封止樹脂
６ 台座部
７ レンズ部
８ レンズ面
９ 平側面
１０ 底面
１１ リードストッパー
１２ 下面
１３ 下辺
２０ 注型キャビティ
２１ 注型金型
２２ 開口縁部
２３ タイバー
２４ 多数個取りリードフレーム
２５ 開口面
３０ 回路基板
３１ リード孔
３２ 部品面
３３ はんだ面
３４ はんだ
３５ 開口部 DESCRIPTION OF SYMBOLS 1 Semiconductor device 2a, 2b Lead frame 3 LED chip 4 Bonding wire 5 Sealing resin 6 Base part 7 Lens part 8 Lens surface 9 Flat side surface 10 Bottom surface 11 Lead stopper 12 Bottom surface 13 Lower side 20 Casting cavity 21 Casting mold 22 Opening Edge 23 Tie bar 24 Multiple lead frame 25 Opening surface 30 Circuit board 31 Lead hole 32 Component surface 33 Solder surface 34 Solder 35 Opening

Claims (4)

略平行に配設され複数本のリードフレームのうちの少なくとも一本のリードフレームの端部に半導体素子が載設され、前記半導体素子の電極と該半導体素子が載設されたリードフレーム以外の少なくとも一本のリードフレームの端部とがボンディングワイヤによって架空配線され、前記半導体素子と前記ボンディングワイヤとを含む前記複数本のリードフレームの端部が封止樹脂によって樹脂封止された半導体装置であって、
前記封止樹脂は、平側面と、前記リードフレームが延出した底面と、前記平側面と前記底面との交線部を有し、
前記底面は、前記半導体素子の光軸に垂直な面に対して所定の角度で傾斜し、
前記底面において、前記交線部が前記リードフレームの延出方向に位置することを特徴とする半導体装置。 A semiconductor element is mounted on an end portion of at least one of the plurality of lead frames arranged in parallel, and at least other than the electrode of the semiconductor element and the lead frame on which the semiconductor element is mounted An end portion of one lead frame is aerial wired with a bonding wire, and the end portion of the plurality of lead frames including the semiconductor element and the bonding wire is resin-sealed with a sealing resin. And
The sealing resin has a flat side surface, a bottom surface from which the lead frame extends, and an intersection portion of the flat side surface and the bottom surface,
The bottom surface is inclined at a predetermined angle with respect to a plane perpendicular to the optical axis of the semiconductor element;
In the bottom surface, the intersecting line portion is located in an extending direction of the lead frame. 前記封止樹脂の底面から延出したリードフレームのうちの少なくとも一本のリードフレームには、該リードフレームの延出方向に垂直な方向に突出したリードストッパーが形成されており、前記封止樹脂は、前記交線部と前記リードストッパーの下面とは前記半導体素子の光軸に垂直な面上の略同一平面上に位置していることを特徴とする請求項１に記載の半導体装置。   At least one of the lead frames extending from the bottom surface of the sealing resin is provided with a lead stopper protruding in a direction perpendicular to the extending direction of the lead frame, and the sealing resin 2. The semiconductor device according to claim 1, wherein the intersecting line portion and the lower surface of the lead stopper are located on substantially the same plane on a plane perpendicular to the optical axis of the semiconductor element. 前記半導体素子は、ＬＥＤチップ、フォトダイオードチップ、ＰＩＮフォトダイオードチップ及びフォトトランジスタチップの群の中から選ばれた少なくとも１つであることを特徴とする請求項１または２のいずれか１項に記載の半導体装置。   3. The semiconductor device according to claim 1, wherein the semiconductor element is at least one selected from the group of an LED chip, a photodiode chip, a PIN photodiode chip, and a phototransistor chip. 4. Semiconductor device. 前記樹脂封止は、キャスティングによって行なわれることを特徴とする請求項１〜３のいずれか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the resin sealing is performed by casting.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009246343A (en) * 2008-03-11 2009-10-22 Rohm Co Ltd Semiconductor light-emitting apparatus and method of manufacturing the same
JP2011249433A (en) * 2010-05-25 2011-12-08 Nichia Chem Ind Ltd Light-emitting device and method for manufacturing the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0444171A (en) * 1990-06-11 1992-02-13 Matsushita Graphic Commun Syst Inc Information file system
JPH05243620A (en) * 1992-02-27 1993-09-21 Rohm Co Ltd Light-emitting diode device and its manufacture
JPH06310764A (en) * 1993-04-27 1994-11-04 Sanyo Electric Co Ltd Led lamp
JP2003204086A (en) * 2001-10-23 2003-07-18 Sharp Corp Light emitting diode lamp and its manufacturing method
JP2004319591A (en) * 2003-04-11 2004-11-11 Sharp Corp Semiconductor light emitting device and its manufacturing method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0444171A (en) * 1990-06-11 1992-02-13 Matsushita Graphic Commun Syst Inc Information file system
JPH05243620A (en) * 1992-02-27 1993-09-21 Rohm Co Ltd Light-emitting diode device and its manufacture
JPH06310764A (en) * 1993-04-27 1994-11-04 Sanyo Electric Co Ltd Led lamp
JP2003204086A (en) * 2001-10-23 2003-07-18 Sharp Corp Light emitting diode lamp and its manufacturing method
JP2004319591A (en) * 2003-04-11 2004-11-11 Sharp Corp Semiconductor light emitting device and its manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009246343A (en) * 2008-03-11 2009-10-22 Rohm Co Ltd Semiconductor light-emitting apparatus and method of manufacturing the same
JP2011249433A (en) * 2010-05-25 2011-12-08 Nichia Chem Ind Ltd Light-emitting device and method for manufacturing the same

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