JP2007134365A - Manufacturing method of semiconductor substrate and of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor substrate and that of a semiconductor device capable of etching a first semiconductor layer fully and preventing its etching residue. <P>SOLUTION: An SiGe layer 3 and an Si layer 5 are formed successively on an Si substrate 1, and a hole (h) for exposing the Si substrate 1 is formed on the Si layer 5 and the SiGe layer 3. Then, a support 7' for supporting the Si layer 5 on the Si substrate 1 is formed on the Si substrate 1 so that the hole (h) is buried and the Si layer 5 is covered. Then, a prescribed region including the hole (h) is covered, and a resist pattern 9 for exposing a region other than the prescribed region is formed on a support 7'. Then, with the resist pattern 9 as a mask; the support 7', the Si layer 5, and the SiGe layer 3 are subjected to dry etching successively, and an open surface H for exposing the side of the SiGe layer 3 is formed under the support 7'. Further, after the open surface H is formed; the resist pattern 9 is removed from the Si substrate 1, and the Si substrate 1 is cleaned by dilute hydrofluoric acid. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor substrate and a method for manufacturing a semiconductor device. In particular, the first semiconductor layer can be sufficiently etched and the etching residue can be prevented.

  Field effect transistors formed on an SOI substrate are attracting attention because of their ease of element isolation, latch-up freeness, and low source / drain junction capacitance. In particular, since a fully depleted SOI transistor can operate at low power consumption and at high speed and can be easily driven at a low voltage, research for operating the SOI transistor in a fully depleted mode has been actively conducted.

  As a method for producing an SOI substrate, for example, a SIMOX (Separation by Implanted Oxgen) substrate, a bonded substrate, or the like is used. For this reason, an SBSI (Separation by Bonding Silicon Island) method, which is a method for producing an SOI structure from an ordinary bulk silicon wafer by an ordinary CMOS process, is known.

  3A to 9C are views showing a method for manufacturing the semiconductor device 200 according to the conventional example. Specifically, FIG. 3A to FIG. 9A are plan views showing a method for manufacturing the semiconductor device 200 according to the conventional example. Moreover, (B) of each figure of FIGS. 3-9 is sectional drawing when each of the said top view is cut | disconnected by a3-a'3-a9-a'9 line, (C) of each figure is FIG. 4 is a cross-sectional view when the above plan view is cut along line b3-b′3-b9-b′9.

In the conventional example, as shown in FIGS. 3A to 3C, first, the SiGe layer 3 is formed on the Si substrate 1 which is a bulk silicon wafer, and the Si layer 5 is formed thereon. . The SiGe layer 3 and the Si layer 5 are formed by an epitaxial growth method.
Next, as shown in FIGS. 4A to 4C, support holes h are formed in the Si layer 5 and the SiGe layer 3. That is, a first resist pattern (not shown) that opens the hole forming region and covers the other region is formed on the Si layer 5. Then, using the resist pattern as a mask, the Si layer 5 and the SiGe layer 3 are sequentially etched to expose the surface of the Si substrate 1 from below the resist pattern. Thereby, the hole h is formed. Thereafter, the resist pattern is removed from the Si layer 5.

Next, as shown in FIGS. 5A to 5C, the support 7 is formed over the entire upper portion of the Si substrate 1 after the holes h are formed. The support 7 is, for example, a SiO ₂ film and is formed by a method such as CVD. The film thickness of the support 7 is, for example, about 4000 [Å].
Next, as shown in FIGS. 5A to 5C, a second region that covers a predetermined region including the region where the SOI structure is formed and the hole h and exposes other regions (that is, does not cover) is provided. A resist pattern 9 is formed on the support 7. Then, using the resist pattern 9 as a mask, the support 7, the Si layer 5, and the SiGe layer 3 are sequentially etched. These etchings are performed using an anisotropic dry etching apparatus. Thereby, as shown in FIGS. 6A to 6C, an opening surface H exposing a part of the side surface of the SiGe layer 3 and a part of the side surface of the Si layer 5 is formed under the support 7. .

Next, the second resist pattern is removed using sulfuric acid. Then, the SiGe layer 3 and the Si layer 5 are brought into contact with an etching solution such as hydrofluoric acid through the opening surface H formed under the support 7, so that only the SiGe layer 3 is etched and removed. As shown in (A) to (C), a cavity 11 is formed between the Si substrate 1 and the Si layer 5. Next, the Si substrate 1 is thermally oxidized. At this time, the oxidized species such as O ₂ reaches not only the surface of the Si substrate 1 exposed from below the support 7 but also the inside of the cavity 11 through the opening surface. Therefore, as shown in FIGS. 8A to 8C, the SiO ₂ film 13 is formed in the cavity.

Thereafter, a SiO ₂ film for element isolation is formed on the entire upper surface of the Si substrate 1 by a method such as CVD. Then, as shown in FIGS. 9A to 9C, the entire upper surface of the Si substrate 1 is planarized by CMP, and the element isolation SiO ₂ film 15 and the support 7 are formed from above the Si layer 5. remove. As a result, the Si substrate 1 is completed with a structure (ie, SOI structure) in which the upper surface of the Si layer 5 is exposed and the lower and sides thereof are separated by the SiO ₂ films 13 and 15 and the support 7. After the completion of the SOI structure, an SOI transistor is manufactured by a normal process.
T.A. Sakai et al. , Second International SiGe Technology and Device Meeting, Meeting Abstract, pp. 230-231, May (2004)

  However, when manufacturing is performed in such a process, a process problem may occur. One of the problems is an etching deposit (polymer) that occurs when the support 7 / Si layer 5 / SiGe layer 3 is dry-etched using the resist pattern 9 as a mask in FIGS. 5A to 5C. Occurrence. In the etching of the support 7 / Si layer 5 / SiGe layer 3 in FIGS. 5A to 5C, after the second resist pattern 9 is formed, the support 7 is changed to the Si layer 5 in 2nd STEP. The SiGe layer 3 is etched.

  However, although the etching STEP is different, the same resist pattern 9 is used as it is for the etching mask, so in 2nd STEP in particular, the etching gas reacts with the Si layer 5 / SiGe layer 3 to be etched to form a polymer, As shown in FIG. 10A, the phenomenon that the polymer 21 adheres to the side surface of the resist pattern 9 occurs.

  Here, the resist pattern 9 can be almost completely removed by sulfuric acid peeling in the next step, but the polymer 21 cannot be removed because it does not dissolve in sulfuric acid. Therefore, the polymer 21 that has lost its origin by removing the resist pattern 9 often falls on the Si substrate 1 from the support 7 as shown by the arrow in FIG. It was.

  In this way, when the polymer 21 remains on the Si substrate and the remaining polymer 21 is blocked even at a part of the opening as shown in FIG. 10C, for example, SiGe by hydrofluoric acid in the next step is used. In the wet etching process of the layer 3, the nitric acid did not sufficiently enter the opening surface side, and there was a risk that the etching amount of the SiGe layer 3 was less than usual. As a result, the SiGe layer 3 (hereinafter also referred to as “first semiconductor layer”) remains in the cavity 21, and a desired SOI structure may not be formed.

  Accordingly, the present invention has been made in view of such circumstances, and a semiconductor substrate manufacturing method and a semiconductor device capable of sufficiently etching the first semiconductor layer and preventing the etching residue. It aims at providing the manufacturing method of this.

[Invention 1] In order to achieve the above object, a method of manufacturing a semiconductor substrate according to Invention 1 includes a step of forming a first semiconductor layer on a semiconductor substrate and a wet etching selectivity over the first semiconductor layer. Forming a small second semiconductor layer on the first semiconductor layer; forming a hole exposing the semiconductor substrate in the second semiconductor layer and the first semiconductor layer; and Forming a support on the semiconductor substrate on the semiconductor substrate such that the hole is embedded and the second semiconductor layer is covered; and covering a predetermined region including the hole; Forming a resist pattern that exposes a region other than the substrate on the support, and sequentially dry-etching the support, the second semiconductor layer, and the first semiconductor layer using the resist pattern as a mask, and the support under Forming an opening surface exposing a side surface of the first semiconductor layer; removing the resist pattern from the semiconductor substrate after forming the opening surface; and removing the resist pattern; A step of performing a cleaning process on the semiconductor substrate using dilute hydrofluoric acid; and, after performing the cleaning process on the semiconductor substrate, wet etching the first semiconductor layer through the opening surface, The method includes a step of forming a cavity between the second semiconductor layer and the semiconductor substrate, and a step of forming an insulating film in the cavity.

Here, the “semiconductor substrate” is, for example, a bulk silicon (Si) substrate. The “first semiconductor layer” is, for example, a silicon germanium (SiGe) layer obtained by epitaxial growth, and the “second semiconductor layer” is, for example, an Si layer obtained by epitaxial growth. Further, the support is, for example, a silicon oxide film (SiO ₂ ).
The “dilute hydrofluoric acid” of the present invention includes not only a chemical solution containing only hydrofluoric acid but also a chemical solution containing components other than hydrofluoric acid (for example, buffered hydrofluoric acid). The HF concentration of “dilute hydrofluoric acid” is, for example, about 0.5 to 5.0 [wt%].

Further, for example, CF ₄ is used as an etching gas for the (dry) etching process of SiO ₂ , and a mixed gas containing, for example, Cl ₂ and O ₂ is used as the etching gas for the dry etching process of the Si layer and the SiGe layer. . Further, for example, hydrofluoric acid is used for wet etching of the SiGe layer through the opening surface.
According to the method for manufacturing a semiconductor substrate of the invention 1, even when a polymer is generated on the side surface of the resist pattern by dry etching the second semiconductor layer and the first semiconductor layer, the generated polymer uses dilute hydrofluoric acid. It is removed by the washing process that was. Therefore, regardless of the presence or absence of polymer adhesion, the etching solution easily enters the first semiconductor layer side through the opening surface, and can sufficiently etch the first semiconductor layer. Thereby, the etching residue of the first semiconductor layer can be prevented.

[Invention 2] A method of manufacturing a semiconductor substrate according to Invention 2 includes a step of forming a first semiconductor layer on a semiconductor substrate, and a second semiconductor layer having a wet etching selectivity smaller than that of the first semiconductor layer. A step of forming on one semiconductor layer, a step of forming a hole exposing the semiconductor substrate in the second semiconductor layer and the first semiconductor layer, and supporting the second semiconductor layer on the semiconductor substrate. Forming a support on the semiconductor substrate so that the hole is embedded and the second semiconductor layer is covered; and a resist pattern covering a predetermined region including the hole and exposing the other region Forming on the support, etching the support using the resist pattern as a mask, removing the support from regions other than the predetermined region, and using the resist pattern as a mask A step of removing the resist pattern from the semiconductor substrate after etching the support; and after removing the resist pattern, the second semiconductor layer and the first semiconductor layer using the support as a mask, By sequentially dry-etching the first semiconductor layer under the support so as to expose the side surface of the first semiconductor layer, and wet etching the first semiconductor layer through the opening surface. And a step of forming a cavity between the two semiconductor layers and the semiconductor substrate, and a step of forming an insulating film in the cavity.

  In such a configuration, after removing the resist pattern, the second semiconductor layer and the first semiconductor layer are dry-etched, so that the phenomenon that the polymer adheres to the side surface of the resist pattern does not occur (that is, the polymer No residue occurs). Therefore, the etching solution easily enters the first semiconductor layer side through the opening surface, and the first semiconductor layer can be sufficiently etched. Thereby, the etching residue of the first semiconductor layer can be prevented.

[Invention 3] The semiconductor substrate manufacturing method of Invention 3 is the semiconductor substrate manufacturing method of Invention 1 or Invention 2, wherein the first insulating film is formed in the cavity when the insulating film is a first insulating film. Forming a second insulating film on the entire upper surface of the semiconductor substrate after forming the substrate, and performing a planarization process on the entire upper surface of the semiconductor substrate after forming the second insulating film. And a step of removing the second insulating film and the support from the second semiconductor layer.
With such a configuration, since the surface of the second semiconductor layer is exposed from under the support, it is possible to form an element such as a transistor in the second semiconductor layer.

[Invention 4] The method for manufacturing a semiconductor device according to Invention 4 includes performing the method for manufacturing a semiconductor substrate according to Invention 3, and removing the second insulating film and the support from the second semiconductor layer. Forming a transistor in the second semiconductor layer.
With such a configuration, since the semiconductor substrate manufacturing method is applied, it is easy for the etchant to enter the first semiconductor layer side through the opening surface, and the first semiconductor layer is sufficiently etched. be able to. Therefore, the remaining etching of the first semiconductor layer can be prevented, so that a transistor having an SOI structure (that is, an SOI transistor) can be formed with good reproducibility.

  The present invention is very suitable when applied to a so-called SBSI technique in which an SOI structure is formed only in a desired region of a bulk semiconductor substrate.

Embodiments of the present invention will be described below with reference to the drawings.
(1) First Embodiment FIGS. 1A to 1F are cross-sectional views showing a method for manufacturing a semiconductor device 100 according to a first embodiment of the present invention. 1A to 1F, parts having the same functions and the same configurations as those in FIGS. 3A to 8C according to the conventional example are denoted by the same reference numerals, and detailed description thereof is provided. Is omitted. In this embodiment, the process up to the step of selectively etching the Si layer 5 and the SiGe layer 3 sequentially to form the hole h for the support is the same as the conventional example.

  That is, as shown in FIG. 1A, first, the SiGe layer 3 is formed on the Si substrate 1 which is a bulk silicon wafer, and the Si layer 5 is formed thereon. The SiGe layer 3 and the Si layer 5 are each formed by epitaxial growth. The film thickness of the SiGe layer 3 is, for example, about 10 to 200 [nm], and the film thickness of the Si layer 5 is, for example, about 10 to 200 [nm].

Next, the Si layer 5 and the SiGe layer 3 are sequentially etched using the first resist pattern as a mask to form a support hole h (see FIGS. 4A and 4C). Then, a support 7 ′ is formed over the entire upper portion of the Si substrate 1 after the hole h is formed. The support 7 ′ is, for example, a SiO ₂ film, and is formed by a method such as CVD. The film thickness of the support 7 ′ is, for example, about 5000 [Å] (the film thickness of the support 7 described in the conventional example is about 4000 [Å]).

  Next, as shown in FIG. 1B, a second resist pattern 9 that covers a predetermined region including the region where the SOI structure is formed and the hole h and exposes other regions (that is, does not cover) is formed. Formed on the support 7 '. Then, as shown in FIGS. 1C and 1D, the support 7 ′, the Si layer 5 and the SiGe layer 3 are sequentially dry etched using the resist pattern 9 as a mask.

In this etching step, the etching process may be continued up to the Si substrate 1 without stopping at the SiGe layer 3 (that is, overetching may be performed). For example, a gas containing CF ₄ is used as an etching gas for etching the support 7 ′, and a gas containing Cl ₂ and O ₂ is used as an etching gas for etching the Si layer 5 / SiGe layer 3. As a result, as shown in FIG. 1D, an opening surface H exposing a part of the side surface of the SiGe layer 3 and a part of the side surface of the Si layer 5 is formed under the support 7 '.

Here, in the first embodiment, as in the conventional example, during dry etching of the Si layer 5 and the SiGe layer 3, an etching gas containing Cl ₂ and O ₂ and the Si layer 5 / SiGe layer 3 that is an etching object are used. Reacts to generate polymer 21. And this polymer (namely, deposit formation) 21 adheres to the side wall of the resist pattern 9, as shown in FIG.1 (D).
Next, the Si substrate 1 is washed with, for example, sulfuric acid (H ₂ SO ₄ ), and the resist pattern 9 is removed (that is, the sulfuric acid is peeled off). Here, the resist pattern 9 is dissolved in sulfuric acid, but the polymer 21 is not dissolved in sulfuric acid. Therefore, as shown in FIG. It falls on the Si substrate 1.

Next, the Si substrate 1 is washed with, for example, diluted hydrofluoric acid (HF) to remove the polymer 21. The concentration of HF in the liquid is, for example, about 0.5 to 5.0 [wt%] (that is, a concentration of 50 [wt%] HF solution diluted about 10 to 100 times with pure water). The polymer 21 is dissolved in such dilute hydrofluoric acid and removed from the Si substrate 1.
In the cleaning process using dilute hydrofluoric acid, when the support 7 ′ is a SiO ₂ film, the support 7 ′ is also wet etched, and the force for supporting the Si layer 5 (ie, the support force) is reduced. There is a possibility. For example, in this cleaning step, the support 7 ′ is etched by about 1000 [Å]. However, in the first embodiment, the wet etching amount of the support 7 ′ in this cleaning process is predicted, and the support 7 ′ is formed thicker in advance (the support 7 ′ compared to the conventional example). For example, the thickness of the support 7 ′ is satisfactory even after the cleaning treatment with dilute hydrofluoric acid, and a sufficient supporting force can be maintained.

The process after the polymer 21 is removed using dilute hydrofluoric acid is the same as the conventional example. That is, only the SiGe layer 3 is etched and removed by bringing an etching solution such as hydrofluoric acid into contact with the SiGe layer 3 and the Si layer 5 through the opening formed in the support 7 ′. As a result, a cavity 11 (see FIGS. 7B and 7C) is formed between the Si substrate 1 and the Si layer 5. Next, the Si substrate 1 is thermally oxidized. At this time, the oxidized species such as O ₂ reaches not only the surface of the Si substrate 1 exposed from below the support 7 ′ but also the cavity 11 through the opening surface. Therefore, the SiO ₂ film 13 (see FIGS. 8B and 8C) is formed in the cavity 11. The SiO ₂ film 13 formed in the cavity 11 becomes a BOX layer which is a part of the SOI structure.

Next, an SiO ₂ film 15 (see FIGS. 9B and 9C) for element isolation is formed on the entire upper surface of the Si substrate 1 by a method such as CVD. Then, the entire upper surface of the Si substrate 1 is planarized by CMP, and the element isolating SiO ₂ film 15 and the support 7 ′ are removed from above the Si layer 5. As a result, a structure in which the upper surface of the Si layer 5 is exposed and the lower and side portions of the Si layer 5 are separated by the SiO ₂ films 13 and 15 and the support 7 ′ (that is, the SOI structure) is formed on the Si substrate 1. Finalize.

  Next, a gate insulating film is formed on the surface of the Si layer 5 by performing thermal oxidation of the surface of the Si layer 5, for example. Then, a gate electrode is formed on the Si layer 5 on which the gate insulating film is formed. Further, using this gate electrode or the like as a mask, impurities such as As, P, and B are ion-implanted into the Si layer 5 to form a source / drain, and an SOI structure field effect transistor (ie, SOI transistor). To complete.

  As described above, according to the first embodiment of the present invention, even when the polymer 21 is generated on the side surface of the resist pattern 9 by dry etching the Si layer 5 / SiGe layer 3, the generated polymer 21 is diluted with the diluted fluorine. Removed by washing with acid. Therefore, regardless of whether the polymer 21 is attached or not, the fluorinated nitric acid easily enters the SiGe layer 3 side through the opening surface, and the SiGe layer 3 can be sufficiently etched. Thereby, the etching residue of the SiGe layer 3 can be prevented, so that the SOI transistor can be formed with good reproducibility.

(2) Second Embodiment In the first embodiment, the case where the Si layer 5 and the polymer 21 generated when the Si substrate 1 is etched is etched with dilute hydrofluoric acid and removed is described. However, if the resist pattern 9 does not remain on the Si substrate 1 when the Si layer 5 and the SiGe layer 3 are etched, the polymer 21 does not depend on the first place, and the polymer 21 does not adhere. In the second embodiment, a case will be described in which the resist pattern 9 is removed immediately after the dry etching of the support 7 ′, and then the Si layer 5 and the SiGe layer 3 are dry etched using the support 7 ′ as a hard mask.

2A and 2B are cross-sectional views illustrating a method for manufacturing a semiconductor device 100 according to the second embodiment of the present invention. The second embodiment is the same as the first embodiment up to the step of dry etching the support 7 ′ using the resist pattern 9 as a mask.
That is, as shown in FIG. 2A, the support 7 ′ is dry-etched using the resist pattern 9 as a mask, and the support is taken from a region other than the “predetermined region including the region where the SOI structure is formed and the hole h”. Remove 7 '. By this dry etching, the shape of the support 7 ′ in plan view is the same as that of the resist pattern 9 in plan view. Similar to the first embodiment, in this dry etching, a gas containing, for example, CF ₄ is used as an etching gas.

Next, the Si substrate 1 is washed with, for example, sulfuric acid (H ₂ SO ₄ ), and the resist pattern 9 is removed from the support 7 ′ as shown in FIG. 2B (that is, a polymer is generated). The resist pattern 9 is removed before.) Then, as shown in FIG. 2C, the Si layer 5 and the SiGe layer 3 are sequentially dry etched using the support 7 'as a mask. In this etching step, the etching process may be continued up to the Si substrate 1 without stopping at the SiGe layer 3 (that is, overetching may be performed). Similarly to the first embodiment, for etching the Si layer 5 / SiGe layer 3, for example, an etching gas containing Cl ₂ and O ₂ is used. As a result, as shown in FIG. 2C, an opening surface H exposing a part of the side surface of the SiGe layer 3 and a part of the side surface of the Si layer 5 is formed under the support 7 '. The subsequent steps are the same as in the first embodiment.

  According to the second embodiment of the present invention, after removing the resist pattern 9, the Si layer 5 / SiGe layer 3 is dry-etched using the support 7 ′ as a hard mask, so that the polymer 21 is formed on the side surface of the resist pattern 9. The phenomenon of adhesion does not occur (that is, the polymer 21 does not remain). Therefore, regardless of whether the polymer 21 is attached or not, the fluorinated nitric acid easily enters the SiGe layer 3 side through the opening surface, and the SiGe layer 3 can be sufficiently etched. Thereby, the etching residue of the SiGe layer 3 can be prevented.

Further, when the support 7 ′ is a SiO ₂ film, the support 7 ′ is also etched during the dry etching of the Si layer 5 / SiGe layer 3, and the support force may be reduced. Therefore, in this second embodiment as well, the support 7 'is formed thicker by predicting the etching amount when used as a hard mask for the support 7'.
For example, when the estimated etching amount of the support 7 ′ is about 1000 [Å], the support 7 ′ is formed thicker by about 1000 [Å] than in the conventional example. Thereby, even after the dry etching of the Si layer 5 / SiGe layer 3, there is no problem in the thickness of the support 7 ', and a sufficient supporting force can be maintained.

In the first and second embodiments, the Si substrate 1 corresponds to the “semiconductor substrate” of the present invention, and the SiGe layer 3 corresponds to the “first semiconductor layer” of the present invention. The Si layer corresponds to the “second semiconductor layer” of the present invention, and the second resist pattern 9 corresponds to the “resist pattern” of the present invention. Further, the SiO ₂ film 13 corresponds to the “(first) insulating film” of the present invention, and the SiO ₂ film 15 corresponds to the “second insulating film” of the present invention.

FIG. 6 is a view showing a method for manufacturing the semiconductor device 100 according to the first embodiment. The figure which shows the manufacturing method of the semiconductor device 100 which concerns on 2nd Embodiment. FIG. 10 is a diagram illustrating a method for manufacturing a semiconductor device 200 according to a conventional example (part 1); FIG. 6 is a diagram (No. 2) illustrating a method for manufacturing a semiconductor device 200 according to a conventional example. FIG. 6 is a diagram (No. 3) illustrating a method for manufacturing a semiconductor device 200 according to a conventional example. FIG. 4 is a diagram (part 4) illustrating the method for manufacturing the semiconductor device 200 according to the conventional example. FIG. 5 is a diagram (No. 5) illustrating a method for manufacturing a semiconductor device 200 according to a conventional example. FIG. 6 illustrates a method for manufacturing a semiconductor device 200 according to a conventional example (No. 6). FIG. 7 is a view showing a method for manufacturing a semiconductor device 200 according to a conventional example (part 7); The figure which shows the trouble of a prior art example.

Explanation of symbols

1 Si substrate, 3 SiGe layer, 5 Si layer, 7, 7 ′ support, 9 resist pattern, 11 cavity, 13, 15 SiO ₂ film, 21 polymer, 100 semiconductor device, h hole, H opening surface

Claims (4)

Forming a first semiconductor layer on a semiconductor substrate;
Forming a second semiconductor layer having a lower wet etching selectivity than the first semiconductor layer on the first semiconductor layer;
Forming a hole exposing the semiconductor substrate in the second semiconductor layer and the first semiconductor layer;
Forming a support for supporting the second semiconductor layer on the semiconductor substrate on the semiconductor substrate so that the hole is embedded and the second semiconductor layer is covered;
Forming a resist pattern on the support that covers a predetermined region including the hole and exposes the other region;
Using the resist pattern as a mask, sequentially dry-etching the support, the second semiconductor layer, and the first semiconductor layer to form an opening that exposes a side surface of the first semiconductor layer under the support; ,
Removing the resist pattern from the semiconductor substrate after forming the opening surface;
After removing the resist pattern, applying a cleaning process to the semiconductor substrate using dilute hydrofluoric acid;
A cavity is formed between the second semiconductor layer and the semiconductor substrate by wet-etching the first semiconductor layer through the opening after the cleaning treatment is performed on the semiconductor substrate. And a process of
And a step of forming an insulating film in the cavity. Forming a first semiconductor layer on a semiconductor substrate;
Forming a second semiconductor layer having a lower wet etching selectivity than the first semiconductor layer on the first semiconductor layer;
Forming a hole exposing the semiconductor substrate in the second semiconductor layer and the first semiconductor layer;
Forming a support for supporting the second semiconductor layer on the semiconductor substrate on the semiconductor substrate so that the hole is embedded and the second semiconductor layer is covered;
Forming a resist pattern on the support that covers a predetermined region including the hole and exposes the other region;
Etching the support using the resist pattern as a mask to remove the support from a region other than the predetermined region;
Removing the resist pattern from the semiconductor substrate after etching the support using the resist pattern as a mask;
After removing the resist pattern, the second semiconductor layer and the first semiconductor layer are sequentially dry-etched using the support as a mask to expose the side surfaces of the first semiconductor layer under the support Forming a surface;
Forming a cavity between the second semiconductor layer and the semiconductor substrate by wet-etching the first semiconductor layer through the opening surface;
And a step of forming an insulating film in the cavity. When the insulating film is a first insulating film,
Forming a second insulating film on the entire upper surface of the semiconductor substrate after forming the first insulating film in the cavity;
After forming the second insulating film, performing a planarization process on the entire upper surface of the semiconductor substrate to remove the second insulating film and the support from the second semiconductor layer; The method of manufacturing a semiconductor substrate according to claim 1, wherein: After removing the second insulating film and the support from the second semiconductor layer by performing the method for manufacturing a semiconductor substrate according to claim 3,
Forming a transistor in the second semiconductor layer. A method for manufacturing a semiconductor device, comprising:

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