JP2007081031A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device, capable of inexpensively forming a SOI structure on part of a semiconductor substrate without using selective epitaxial growth. <P>SOLUTION: A first single crystal semiconductor layer 3a and a second single crystal semiconductor layer 4a are sequentially formed on a SOI (Silicon-On-Insulator) structure formation region R2 on the semiconductor substrate 1 by means of epitaxial growth, and in addition, a first amorphous semiconductor layer 3b and a second amorphous semiconductor layer 4b are sequentially formed on a bulk structure formation region R1 and an element separation oxide film 2 on the semiconductor substrate 1. Thereafter, the second single crystal semiconductor layer 4a, the second amorphous semiconductor layer 4b, the first single crystal semiconductor layer 3a and the first amorphous semiconductor layer 3b are etched with a resist pattern R1 as a mask, thereby forming an aperture 7 for exposing part of the semiconductor substrate 1 on the SOI structure formation region R2. In addition, the first amorphous semiconductor layer 3b and the second amorphous semiconductor layer 4b on the bulk structure formation region R1 and the element separation oxide film 2 are removed. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and is particularly suitable for application to a method for manufacturing a field effect transistor formed on an SOI (Silicon On Insulator) substrate.

  Field effect transistors formed on an SOI substrate are attracting attention because of their ease of element isolation, latch-up freeness, and low source / drain junction capacitance. In particular, since a fully depleted SOI transistor can operate at low power consumption and at high speed and can be easily driven at a low voltage, research for operating the SOI transistor in a fully depleted mode has been actively conducted. Here, as the SOI substrate, for example, as disclosed in Patent Documents 1 and 2, a SIMOX (Separation by Implanted Oxgen) substrate or a bonded substrate is used.

Non-Patent Document 1 discloses a method by which an SOI transistor can be formed at a low cost by forming an SOI layer over a bulk substrate. In the method disclosed in Non-Patent Document 1, a Si / SiGe layer is formed on a Si substrate, and a first groove is formed in the Si / SiGe layer. And after embedding a support body in the 1st groove | channel, the 2nd groove | channel which exposes a SiGe layer from a support body is formed, and only a SiGe layer is selectively utilized using the difference in the selection ratio of Si and SiGe. By removing, a cavity is formed between the Si substrate and the Si layer. Then, by performing thermal oxidation of Si exposed in the cavity, an SiO ₂ layer is embedded between the Si substrate and the Si layer, and a BOX layer is formed between the Si substrate and the Si layer.

If the method disclosed in Non-Patent Document 1 is applied, an SOI transistor and a bulk transistor can be simultaneously formed in one wafer. In this case, the SiGe layer is not formed on the entire surface of the wafer, but is formed only on the SOI transistor formation region by selective epitaxial growth. Here, in selective epitaxial growth, chlorine gas is required to remove the amorphous semiconductor deposited outside the SOI transistor formation region. Here, since used chlorine gas is harmful, detoxification treatment is required. In this detoxification treatment, for example, used chlorine gas can be absorbed by causing the following reaction using ZnO as an excluding agent.
Cl ₂ + ZnO → ZnCl ₂ + 1 / 2O ₂
Also, the excluding agent that has become waste is disposed of by being incinerated.
JP 2002-299951 A Japanese Patent Application Laid-Open No. 2000-124092 T.A. Sakai et al. “Separation by Bonding Si Islands (SBSI) for LSI Applications”, Second International GiGe Technology and Device Meeting, Meeting Abstracts, p. 230 -231, May (2004)

  However, in order to manufacture a SIMOX substrate, it is necessary to ion-implant high concentration oxygen into a silicon wafer. In order to manufacture a bonded substrate, it is necessary to polish the surface of the silicon wafer after bonding two silicon wafers. For this reason, the SOI transistor has a problem that the cost is increased as compared with a field effect transistor formed in a bulk semiconductor.

Also, in ion implantation and polishing, the variation in the thickness of the SOI layer is large, and it is difficult to stabilize the characteristics of the field effect transistor when the SOI layer is thinned in order to produce a fully depleted SOI transistor. Further, in the method disclosed in Non-Patent Document 1, selective epitaxial growth is used to form a SiGe layer only in the SOI transistor formation region, so that it is necessary to exclude chlorine gas. There was a problem that the negative effect on energy and the environment was great.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that can form an SOI structure in a partial region on a semiconductor substrate at low cost without using selective epitaxial growth.

  In order to solve the above-described problem, according to a method for manufacturing a semiconductor device according to one embodiment of the present invention, a step of forming an insulating layer having an opening on a semiconductor substrate, and a first amorphous semiconductor by epitaxial growth Forming a first single crystal semiconductor layer on a semiconductor substrate exposed through the opening while depositing a layer on the insulating layer; and epitaxially growing a second amorphous semiconductor layer on the first amorphous semiconductor layer. Forming a second single crystal semiconductor layer made of a material having an etching rate lower than that of the first single crystal semiconductor layer on the first single crystal semiconductor layer while being deposited on the layer; and Forming a first exposed portion that exposes sidewalls of the crystalline semiconductor layer and the second single crystal semiconductor layer, and a first amorphous semiconductor layer deposited on the insulating layer; 2 removing the amorphous semiconductor layer, forming a support embedded in the first exposed portion and supporting the second single crystal semiconductor layer on the semiconductor substrate, and forming the first single crystal semiconductor layer Forming a second exposed portion that exposes a part of the support and the second single crystal semiconductor layer, and selectively etching the first single crystal semiconductor layer through the second exposed portion, Forming a cavity from which the first single crystal semiconductor layer has been removed between the semiconductor substrate and the second single crystal semiconductor layer; and forming a buried insulating layer embedded in the cavity. It is characterized by providing.

  Thereby, even when the second single crystal semiconductor layer is stacked on the first single crystal semiconductor layer, the etching gas or the etchant can be brought into contact with the first single crystal semiconductor layer through the second exposed portion. Thus, the first single crystal semiconductor layer can be removed using the difference in the selection ratio between the first and second single crystal semiconductor layers while the second single crystal semiconductor layer remains, and the second single crystal semiconductor layer can be removed. A buried insulating layer buried in the cavity under the crystalline semiconductor layer can be formed. In addition, by providing a support that supports the second single crystal semiconductor layer on the semiconductor substrate, the second single crystal semiconductor layer is formed on the semiconductor substrate even when a cavity is formed below the second single crystal semiconductor layer. Can be prevented from falling off. Furthermore, by depositing the first amorphous semiconductor layer on the insulating layer by epitaxial growth and forming the first single crystal semiconductor layer on the semiconductor substrate exposed through the opening, a part of the semiconductor substrate is formed. Even when the first single crystal semiconductor layer and the second single crystal semiconductor layer are formed in the region, it is not necessary to use selective epitaxial growth. In addition, even when the first amorphous semiconductor layer and the second amorphous semiconductor layer are deposited on the insulating layer, the first amorphous semiconductor layer and the second amorphous semiconductor layer are collectively etched when forming the first exposed portion. Can be removed.

  Therefore, it is possible to dispose the second single crystal semiconductor layer on the buried insulating layer while reducing the occurrence of defects in the second single crystal semiconductor layer, and without damaging the quality of the second single crystal semiconductor layer, When it is possible to achieve insulation between the second single crystal semiconductor layer and the semiconductor substrate, and the second single crystal semiconductor layer disposed on the buried insulating layer is formed in a partial region on the semiconductor substrate In this case, it is not necessary to use chlorine gas. As a result, an SOI transistor can be formed on the second single crystal semiconductor layer without using an SOI substrate, so that the SOI transistor can be reduced in price and chlorine gas is excluded. Can reduce the adverse effects on the energy and the environment required.

  In addition, when the method for manufacturing a semiconductor device according to one embodiment of the present invention is applied, a step of forming an insulating layer having an opening formed over a semiconductor substrate, and a first amorphous semiconductor layer over the insulating layer by epitaxial growth And depositing a second amorphous semiconductor layer on the first amorphous semiconductor layer by epitaxial growth, and a step of forming a first single crystal semiconductor layer on the semiconductor substrate exposed through the opening. Forming a second single crystal semiconductor layer made of a material having an etching rate smaller than that of the first single crystal semiconductor layer on the first single crystal semiconductor layer; and the first single crystal semiconductor layer and the second single crystal semiconductor layer Forming a first exposed portion exposing a side wall of the single crystal semiconductor layer; and supporting the second single crystal semiconductor layer embedded in the first exposed portion on the semiconductor substrate. Forming a support; forming a second exposed portion for exposing a part of the first single crystal semiconductor layer from the support and the second single crystal semiconductor layer; and depositing on the insulating layer Removing the support, the first amorphous semiconductor layer, and the second amorphous semiconductor layer; and selectively etching the first single crystal semiconductor layer through the second exposed portion to thereby form the first single crystal semiconductor layer And a step of forming a cavity portion from which the semiconductor layer is removed between the semiconductor substrate and the second single crystal semiconductor layer, and a step of forming a buried insulating layer embedded in the cavity portion.

  Accordingly, even when the first single crystal semiconductor layer and the second single crystal semiconductor layer are formed in a part of the region on the semiconductor substrate, it is not necessary to use selective epitaxial growth, and the first amorphous semiconductor layer and the second amorphous semiconductor layer are eliminated. Even when the semiconductor layer is deposited on the insulating layer, the first amorphous semiconductor layer and the second amorphous semiconductor layer can be collectively removed by etching when the second exposed portion is formed. For this reason, even when the second single crystal semiconductor layer disposed on the buried insulating layer is formed in a partial region on the semiconductor substrate, it is not necessary to use chlorine gas, and it is necessary to exclude chlorine gas. The second single crystal semiconductor layer disposed on the buried insulating layer is formed in a partial region on the semiconductor substrate while reducing the adverse effects on the energy and the environment and suppressing the increase in cost. It becomes possible to do.

  In addition, according to the method for manufacturing a semiconductor device of one embodiment of the present invention, the step of forming an antioxidant film in the bulk structure forming region and the SOI structure forming region on the semiconductor substrate, and the semiconductor using the antioxidant film as a mask By performing thermal oxidation of the substrate, a step of forming an element isolation insulating film for isolating the bulk structure formation region and the SOI structure formation region, and leaving the antioxidant film on the bulk structure formation region, Removing the anti-oxidation film on the SOI structure formation region, and depositing the first amorphous semiconductor layer on the element isolation insulating film and the anti-oxidation film by epitaxial growth, and on the semiconductor substrate in the SOI structure formation region A step of forming a first single crystal semiconductor layer; and a second amorphous semiconductor layer formed by epitaxial growth to form the first amorphous semiconductor layer. Forming a second single crystal semiconductor layer made of a material having a lower etching rate than the first single crystal semiconductor layer on the first single crystal semiconductor layer while being deposited on the first single crystal semiconductor layer; Forming a first exposed portion exposing the side wall of the layer and the second single crystal semiconductor layer, and removing the first amorphous semiconductor layer and the second amorphous semiconductor layer deposited on the element isolation insulating film and the antioxidant film Forming a support that is embedded in the first exposed portion and supports the second single crystal semiconductor layer on the semiconductor substrate, and a part of the first single crystal semiconductor layer is the support. And forming a second exposed portion exposed from the second single crystal semiconductor layer, and selectively etching the first single crystal semiconductor layer through the second exposed portion, thereby Forming a cavity portion from which the crystal semiconductor layer has been removed between the semiconductor substrate and the second single crystal semiconductor layer, and forming a buried insulating layer embedded in the cavity portion. And

  Accordingly, even when the first single crystal semiconductor layer and the second single crystal semiconductor layer are formed in the SOI structure formation region on the semiconductor substrate, it is not necessary to use selective epitaxial growth, and the first amorphous semiconductor layer and the second amorphous semiconductor layer Even when the semiconductor layer is deposited on the bulk structure forming region, the first amorphous semiconductor layer and the second amorphous semiconductor layer can be collectively removed by etching when the first exposed portion is formed. For this reason, even when the second single crystal semiconductor layer disposed on the buried insulating layer is formed in the SOI structure formation region, it is not necessary to use chlorine gas, and energy required to exclude chlorine gas, It is possible to reduce adverse effects on the environment and to form the SOI structure and the bulk structure on the same semiconductor substrate while suppressing an increase in cost.

  In addition, according to the method for manufacturing a semiconductor device of one embodiment of the present invention, the step of forming an antioxidant film in the bulk structure forming region and the SOI structure forming region on the semiconductor substrate, and the semiconductor using the antioxidant film as a mask By performing thermal oxidation of the substrate, a step of forming an element isolation insulating film for isolating the bulk structure formation region and the SOI structure formation region, and leaving the antioxidant film on the bulk structure formation region, Removing the anti-oxidation film on the SOI structure formation region, and depositing the first amorphous semiconductor layer on the element isolation insulating film and the anti-oxidation film by epitaxial growth, and on the semiconductor substrate in the SOI structure formation region A step of forming a first single crystal semiconductor layer; and a second amorphous semiconductor layer formed by epitaxial growth to form the first amorphous semiconductor layer. Forming a second single crystal semiconductor layer made of a material having a lower etching rate than the first single crystal semiconductor layer on the first single crystal semiconductor layer while being deposited on the first single crystal semiconductor layer; Forming a first exposed portion exposing the side walls of the layer and the second single crystal semiconductor layer, and a support embedded in the first exposed portion and supporting the second single crystal semiconductor layer on the semiconductor substrate. Forming a second exposed portion that exposes a part of the first single crystal semiconductor layer from the support and the second single crystal semiconductor layer, and on the element isolation insulating film and the antioxidant film. Removing the support, the first amorphous semiconductor layer, and the second amorphous semiconductor layer deposited on the substrate, and selectively etching the first single crystal semiconductor layer through the second exposed portion, Forming a cavity from which the first single crystal semiconductor layer is removed between the semiconductor substrate and the second single crystal semiconductor layer, and forming a buried insulating layer embedded in the cavity. It is characterized by that.

  Accordingly, even when the first single crystal semiconductor layer and the second single crystal semiconductor layer are formed in the SOI structure formation region on the semiconductor substrate, it is not necessary to use selective epitaxial growth, and the first amorphous semiconductor layer and the second amorphous semiconductor layer Even when the semiconductor layer is deposited on the bulk structure formation region, the first amorphous semiconductor layer and the second amorphous semiconductor layer can be collectively removed by etching when forming the second exposed portion. For this reason, even when the second single crystal semiconductor layer disposed on the buried insulating layer is formed in the SOI structure formation region, it is not necessary to use chlorine gas, and energy required to exclude chlorine gas, It is possible to reduce adverse effects on the environment and to form the SOI structure and the bulk structure on the same semiconductor substrate while suppressing an increase in cost.

The method for manufacturing a semiconductor device according to one aspect of the present invention further includes a step of removing the first amorphous semiconductor layer and the second amorphous semiconductor layer in the non-exposed region remaining in the peripheral portion of the wafer by wet etching. It is characterized by that.
As a result, since the resist remains in the non-exposed region of the wafer peripheral portion, the first amorphous semiconductor layer and the second amorphous semiconductor layer in the peripheral portion of the wafer cannot be removed when forming the first exposed portion and the second exposed portion. The first amorphous semiconductor layer and the second amorphous semiconductor layer at the periphery of the wafer can also be removed. Therefore, the second single crystal semiconductor layer disposed on the buried insulating layer can be formed in a partial region on the semiconductor substrate without using selective epitaxial growth, which is necessary to exclude chlorine gas. It is possible to reduce adverse effects on energy and the environment.

According to the method of manufacturing a semiconductor device of one embodiment of the present invention, the semiconductor substrate and the second single crystal semiconductor layer are single crystal Si, and the first single crystal semiconductor layer is single crystal SiGe. And
Accordingly, lattice matching between the semiconductor substrate, the second single crystal semiconductor layer, and the first single crystal semiconductor layer can be achieved, and the first single crystal semiconductor layer is etched more than the semiconductor substrate and the second single crystal semiconductor layer. It is possible to increase the selection ratio. Therefore, the second single crystal semiconductor layer with good crystal quality can be formed on the first single crystal semiconductor layer, and the second single crystal semiconductor layer and the semiconductor can be formed without deteriorating the quality of the second single crystal semiconductor layer. It is possible to achieve insulation from the substrate.

Hereinafter, a semiconductor device manufacturing method according to an embodiment of the present invention will be described with reference to the drawings.
FIGS. 1A to 12A are plan views showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention, and FIGS. 1B to 12B are FIGS. Sectional views cut along lines A1-A1 ′ to A12-A12 ′ in FIG. 12A, and FIGS. 1C to 12C are B1 in FIGS. 1A to 12A, respectively. It is sectional drawing cut | disconnected by the -B1'-B12-B12 'line | wire, respectively.

  In FIG. 1, a semiconductor substrate 1 is provided with a bulk structure forming region R1 for forming a bulk structure and an SOI structure forming region R2 for forming an SOI structure. Then, an antioxidant film is formed on the entire surface of the semiconductor substrate 1 by a method such as CVD. Then, by patterning the antioxidant film using a photolithography technique and an etching technique, the bulk structure forming region R1 and the SOI structure forming region R2 are covered with the antioxidant films 1a and 1b, respectively, and the bulk structure is formed. The antioxidant film around the formation region R1 and the SOI structure formation region R2 is removed.

Next, as shown in FIG. 2, by performing thermal oxidation of the semiconductor substrate 1 using the antioxidant films 1a and 1b as masks, an element isolation oxide film 2 is formed around the bulk structure formation region R1 and the SOI structure formation region R2. Form.
Next, as shown in FIG. 3, the first single crystal semiconductor layer 3a and the second single crystal semiconductor layer 4a are sequentially formed in the SOI structure formation region R2 on the semiconductor substrate 1 by performing epitaxial growth, and the semiconductor substrate A first amorphous semiconductor layer 3b and a second amorphous semiconductor layer 4b are sequentially formed on the bulk structure forming region R1 and the element isolation oxide film 2 on the first layer.

  Here, in the epitaxial growth, the first single crystal semiconductor layer 3a and the second single crystal are formed by thermal CVD while supplying source gases for forming the first single crystal semiconductor layer 3a and the second single crystal semiconductor layer 4a, respectively. The semiconductor layer 4a is formed in the SOI structure forming region R2 on the semiconductor substrate 1. Here, in the epitaxial growth, when the first single crystal semiconductor layer 3a and the second single crystal semiconductor layer 4a are formed in the SOI structure formation region R2 on the semiconductor substrate 1, the bulk structure formation region R1 and the element on the semiconductor substrate 1 are formed. A first amorphous semiconductor layer 3 b and a second amorphous semiconductor layer 4 b are sequentially formed on the isolation oxide film 2. When the first single crystal semiconductor layer 3a and the second single crystal semiconductor layer 4a are sequentially formed in the SOI structure formation region R2 on the semiconductor substrate 1, the first amorphous semiconductor layer 3b and the second amorphous semiconductor layer 4b are formed on the semiconductor substrate. 1 is left as it is on the bulk structure forming region R1 and the element isolation oxide film 2, so that it is not necessary to expose the first amorphous semiconductor layer 3b and the second amorphous semiconductor layer 4b to chlorine gas, and the chlorine gas is excluded. Therefore, it is possible to reduce the adverse effects on the energy and the environment required.

  The first single crystal semiconductor layer 3a can be made of a material having a higher etching rate than the semiconductor substrate 1 and the second single crystal semiconductor layer 4a, and the semiconductor substrate 1, the first single crystal semiconductor layer 3a, and the second single crystal semiconductor layer 3a can be used. As a material of the crystalline semiconductor layer 4a, for example, a combination selected from Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, ZnSe, and the like can be used. In particular, when the semiconductor substrate 1 is Si, it is preferable to use SiGe as the first single crystal semiconductor layer 3a and Si as the second single crystal semiconductor layer 4a. This makes it possible to achieve lattice matching between the first single crystal semiconductor layer 3a and the second single crystal semiconductor layer 4a, and between the first single crystal semiconductor layer 3a and the second single crystal semiconductor layer 4a. The selection ratio can be ensured. As the first single crystal semiconductor layer 3a, a polycrystalline semiconductor layer, an amorphous semiconductor layer, or a porous semiconductor layer may be used in addition to the single crystal semiconductor layer. Further, instead of the first single crystal semiconductor layer 3a, a metal oxide film such as γ-aluminum oxide capable of forming a single crystal semiconductor layer by epitaxial growth may be used. Moreover, the film thickness of the 1st single crystal semiconductor layer 3a and the 2nd single crystal semiconductor layer 4a can be about 1-100 nm, for example.

Next, as shown in FIG. 4, an opening R1a exposing a part of the surface of the second single crystal semiconductor layer 4a is provided by using a photolithography technique, and the entire surface of the second amorphous semiconductor layer 4b is provided. A resist pattern R1 that exposes is formed on the semiconductor substrate 1.
Next, as shown in FIG. 5, the second single crystal semiconductor layer 4a, the second amorphous semiconductor layer 4b, the first single crystal semiconductor layer 3a, and the first amorphous semiconductor layer 3b are etched by using the resist pattern R1 as a mask. In addition, an opening 7 exposing a part of the semiconductor substrate 1 in the SOI structure formation region R2 is formed, and the first amorphous semiconductor layer 3b and the second amorphous semiconductor layer 4b on the bulk structure formation region R1 and the element isolation oxide film 2 are formed. Remove. Then, an opening 7 for exposing a part of the semiconductor substrate 1 in the SOI structure forming region R2 is formed, and when the first amorphous semiconductor layer 3b and the second amorphous semiconductor layer 4b are removed, the resist pattern R1 is removed.

When a part of the semiconductor substrate 1 in the SOI structure formation region R2 is exposed, the etching may be stopped on the surface of the semiconductor substrate 1, or the semiconductor substrate 1 is over-etched to form a recess in the semiconductor substrate 1. You may make it do. The arrangement position of the opening 7 can correspond to a part of the element isolation region of the second single crystal semiconductor layer 4a.
Next, as shown in FIG. 6, a support 8 is formed on the entire surface of the semiconductor substrate 1 by a method such as CVD. The support 8 is also formed on the side walls of the first single crystal semiconductor layer 3a and the second single crystal semiconductor layer 4a in the opening 7, and supports the second single crystal semiconductor layer 4a on the semiconductor substrate 1. be able to. Further, as a material of the support 8, an insulator such as a silicon oxide film or a silicon nitride film can be used. Alternatively, a semiconductor such as polycrystalline silicon or single crystal silicon may be used as the material of the support 8.

Next, as shown in FIG. 7, an opening R2a for exposing a part of the first single crystal semiconductor layer 3a from the support 8 and the second single crystal semiconductor layer 4a is provided by using a photolithography technique. The formed resist pattern R2 is formed on the semiconductor substrate 1.
Next, as shown in FIG. 8, the support 8, the second single crystal semiconductor layer 4a, and the first single crystal semiconductor layer 3a are patterned using the resist pattern R2 as a mask, thereby forming one of the first single crystal semiconductor layers 3a. An exposed surface 9 for exposing the part is formed. Then, when the exposed surface 9 that exposes a part of the first single crystal semiconductor layer 3a is formed, the resist pattern R2 is removed.

  The arrangement position of the exposed surface 9 can correspond to a part of the element isolation region of the second single crystal semiconductor layer 4a. When a part of the first single crystal semiconductor layer 3a is exposed, the etching may be stopped at the surface of the first single crystal semiconductor layer 3a, or the first single crystal semiconductor layer 3a may be overetched to perform the etching. A recess may be formed in one single crystal semiconductor layer 3a. Alternatively, the surface of the semiconductor substrate 1 may be exposed through the first single crystal semiconductor layer 3a where the exposed surface 9 is formed. Here, it is possible to prevent the surface of the semiconductor substrate 1 from being exposed by stopping the etching of the first single crystal semiconductor layer 3a halfway. For this reason, when the first single crystal semiconductor layer 3a is removed by etching, the time during which the semiconductor substrate 1 is exposed to the etching solution or the etching gas can be reduced, and overetching of the semiconductor substrate 1 can be suppressed.

Next, as shown in FIG. 9, the first single crystal semiconductor layer 3 a is removed by etching by bringing an etching gas or an etchant into contact with the first single crystal semiconductor layer 3 a through the exposed surface 9. A cavity 10 is formed between the first single crystal semiconductor layer 4a and the second single crystal semiconductor layer 4a.
Here, by providing the support 8 in the opening 7, the second single crystal semiconductor layer 4 a can be supported on the semiconductor substrate 1 even when the first single crystal semiconductor layer 3 a is removed. In addition, by providing the exposed surface 9 separately from the opening 7, even when the second single crystal semiconductor layer 4a is stacked on the first single crystal semiconductor layer 3a, the exposed surface 9 is provided under the second single crystal semiconductor layer 4a. An etching gas or an etching solution can be brought into contact with the first single crystal semiconductor layer 3a.

For this reason, it becomes possible to arrange | position the 2nd single crystal semiconductor layer 4a on an insulator, reducing generation | occurrence | production of the defect of the 2nd single crystal semiconductor layer 4a, and impairing the quality of the 2nd single crystal semiconductor layer 4a. Insulation between the semiconductor substrate 1 and the second single crystal semiconductor layer 4a can be achieved.
When the semiconductor substrate 1 and the second single crystal semiconductor layer 4a are Si and the first single crystal semiconductor layer 3a is SiGe, hydrofluoric acid (a mixture of hydrofluoric acid, nitric acid, and water) is used as an etchant for the first single crystal semiconductor layer 3a. Liquid). As a result, a Si / SiGe selection ratio of about 1: 100 to 1000 can be obtained, and the first single crystal semiconductor layer 3a is removed while suppressing overetching of the semiconductor substrate 1 and the second single crystal semiconductor layer 4a. It becomes possible to do. Further, as an etching solution for the first single crystal semiconductor layer 3a, hydrofluoric acid overwater, ammonia overwater, or hydrofluoric acid overwater may be used.

  In addition, the first single crystal semiconductor layer 3a may be made porous by a method such as anodic oxidation before the first single crystal semiconductor layer 3a is etched away, or ions may be formed in the first single crystal semiconductor layer 3a. By performing the implantation, the first single crystal semiconductor layer 3a may be made amorphous. As a result, the etching rate of the first single crystal semiconductor layer 3a can be increased, and the etching area of the first single crystal semiconductor layer 3a can be increased while suppressing overetching of the second single crystal semiconductor layer 4a. Can do.

  Next, as shown in FIG. 10, the semiconductor substrate 1 and the second single crystal semiconductor layer 4a are thermally oxidized, so that the cavity 10 between the semiconductor substrate 1 and the second single crystal semiconductor layer 4a is buried and insulated. Layer 11 is formed. Note that after the buried insulating layer 11 is formed in the cavity 10, high-temperature annealing at 1000 ° C. or higher may be performed. As a result, the support 8 can be reflowed, stress is applied to hold down the second single crystal semiconductor layer 4a from above, and the buried insulating layer 11 can be formed without a gap. Further, the buried insulating layer 11 may be formed so as to fill the entire cavity 10 or may be formed so that a part of the cavity 10 remains.

  In the method shown in FIG. 10, the semiconductor substrate 1 and the second single crystal semiconductor layer 4a are thermally oxidized to fill the cavity 10 between the semiconductor substrate 1 and the second single crystal semiconductor layer 4a. The method of forming the semiconductor substrate 1 and the second single crystal semiconductor is described by forming an insulating film in the cavity 10 between the semiconductor substrate 1 and the second single crystal semiconductor layer 4a by the CVD method. The cavity 10 between the layer 4a and the insulating layer 11 may be embedded. This makes it possible to bury the cavity 10 between the semiconductor substrate 1 and the second single crystal semiconductor layer 4a with a material other than the oxide film while preventing the second single crystal semiconductor layer 4a from being reduced. For this reason, it is possible to increase the thickness of the buried insulating layer 11 disposed on the back side of the second single crystal semiconductor layer 4a, and to reduce the dielectric constant. The parasitic capacitance on the back side of 4a can be reduced.

  As a material of the buried insulating layer 11, for example, an FSG (fluorinated silicate glass) film or a silicon nitride film may be used in addition to the silicon oxide film. Further, as the buried insulating layer 11, in addition to an SOG (Spin On Glass) film, a PSG film, a BPSG film, a PAE (poly arylene ether) -based film, an HSQ (hydrogen silsesquioxane) -based film, an MSQ (methyl silsesquioxane) film, An organic lowk film such as a film, a CF-based film, a SiOC-based film, or a SiOF-based film, or a porous film thereof may be used.

  Next, as shown in FIG. 11, the support 8 is etched using a photolithographic technique and an etching technique while using a method such as etch back or CMP (Chemical Mechanical Polishing) as necessary. The surface of the second single crystal semiconductor layer 4a in the SOI structure formation region R2 is exposed. Further, the surface of the semiconductor substrate 1 in the bulk structure formation region R1 is exposed by removing the support 8 and the antioxidant film 1a on the bulk structure formation region R1.

  Next, as shown in FIG. 12, in the SOI structure formation region R2, the surface of the second single crystal semiconductor layer 4a is thermally oxidized to form the gate insulating film 20 on the surface of the second single crystal semiconductor layer 4a. To do. Then, a polycrystalline silicon layer is formed on the second single crystal semiconductor layer 4a on which the gate insulating film 20 is formed by a method such as CVD. Then, the gate electrode 21 is formed on the second single crystal semiconductor layer 4a by patterning the polycrystalline silicon layer using a photolithography technique and an etching technique.

  Next, using the gate electrode 21 as a mask, impurities such as As, P, and B are ion-implanted into the second single crystal semiconductor layer 4a, so that the low-concentration impurity introduction layers disposed on both sides of the gate electrode 21 respectively. An LDD layer to be formed is formed on the second single crystal semiconductor layer 4a. Then, an insulating layer is formed on the second single crystal semiconductor layer 4a on which the LDD layer is formed by a method such as CVD, and the insulating layer is etched back using anisotropic etching such as RIE. Side walls 22 are respectively formed on the side walls 21. Then, by using the gate electrode 21 and the side wall 22 as a mask, impurities such as As, P, and B are ion-implanted into the second single crystal semiconductor layer 4a, so that the high concentration disposed on the side of the side wall 22 is provided. Source / drain layers 23a and 23b made of an impurity introduction layer are formed in the second single crystal semiconductor layer 4a.

  In addition, the gate insulating film 30 is formed on the surface of the semiconductor substrate 1 by thermally oxidizing the surface of the semiconductor substrate 1 in the bulk structure formation region R1. Then, a polycrystalline silicon layer is formed on the semiconductor substrate 1 on which the gate insulating film 30 is formed by a method such as CVD. Then, a gate electrode 31 is formed on the semiconductor substrate 1 by patterning the polycrystalline silicon layer using a photolithography technique and an etching technique.

  Next, by using the gate electrode 31 as a mask, impurities such as As, P, and B are ion-implanted into the semiconductor substrate 1 to form LDD layers made of low-concentration impurity introduction layers respectively disposed on both sides of the gate electrode 31. Formed on the semiconductor substrate 1. Then, an insulating layer is formed on the semiconductor substrate 1 on which the LDD layer is formed by a method such as CVD, and the insulating layer is etched back using anisotropic etching such as RIE, so that the sidewall of the gate electrode 31 is formed. Sidewalls 32 are formed respectively. Then, impurities such as As, P, and B are ion-implanted into the semiconductor substrate 1 using the gate electrode 31 and the sidewall 32 as a mask, so that the high-concentration impurity introduction layers respectively disposed on the sides of the sidewall 32 are removed. Source / drain layers 33 a and 33 b are formed on the semiconductor substrate 1.

  Thus, even when the first single crystal semiconductor layer 3a and the second single crystal semiconductor layer 4a are formed in the SOI structure formation region R2 on the semiconductor substrate 1, it is not necessary to use selective epitaxial growth, and the first amorphous semiconductor layer Even when the 3b and the second amorphous semiconductor layer 4b are deposited on the bulk structure forming region R1, the first amorphous semiconductor layer 3b and the second amorphous semiconductor layer 4b are collectively removed by etching when the opening 7 is formed. can do. Therefore, even when the second single crystal semiconductor layer 4a disposed on the buried insulating layer 11 is formed in the SOI structure formation region R2, it is not necessary to use chlorine gas, and it is necessary to exclude chlorine gas. It is possible to reduce adverse effects on the energy and environment, and to form the SOI structure and the bulk structure on the same semiconductor substrate 1 while suppressing an increase in cost.

  FIGS. 13A to 17A are plan views showing a method for manufacturing a semiconductor device according to the second embodiment of the present invention, and FIGS. 13B to 17B are FIGS. -Sectional drawing cut | disconnected by A13-A13'-A17-A17 'line | wire of FIG. 17 (a), respectively, FIG.13 (c) -FIG.17 (c) is B13 of FIG.13 (a) -FIG.17 (a). It is sectional drawing cut | disconnected by the -B13'-B17-B17 'line | wire, respectively.

In FIG. 13, after the same steps as in FIGS. 1 to 3, an opening R <b> 11 a that exposes part of the surface of the second single crystal semiconductor layer 4 a is provided by using a photolithography technique, and the second A resist pattern R11 covering the entire surface of the amorphous semiconductor layer 4b is formed on the semiconductor substrate 1.
Next, as shown in FIG. 14, by etching the second single crystal semiconductor layer 4a and the first single crystal semiconductor layer 3a using the resist pattern R11 as a mask, a part of the semiconductor substrate 1 in the SOI structure formation region R2 is etched. An opening 7 to be exposed is formed. Then, when the opening 7 exposing a part of the semiconductor substrate 1 in the SOI structure forming region R2 is formed, the resist pattern R11 is removed.

Next, as shown in FIG. 15, a support 8 is formed on the entire surface of the semiconductor substrate 1 by a method such as CVD. The support 8 is also formed on the side walls of the first single crystal semiconductor layer 3a and the second single crystal semiconductor layer 4a in the opening 7, and supports the second single crystal semiconductor layer 4a on the semiconductor substrate 1. be able to.
Next, as shown in FIG. 16, by using a photolithography technique, it is arranged so as to avoid a part on the first single crystal semiconductor layer 3a, and the entire surface of the second amorphous semiconductor layer 4b is avoided. A resist pattern R12 arranged as described above is formed on the support 8.

  Next, as shown in FIG. 17, by patterning the support 8, the second single crystal semiconductor layer 4a, and the first single crystal semiconductor layer 3a using the resist pattern R12 as a mask, one of the first single crystal semiconductor layers 3a is patterned. The exposed surface 9 exposing the portion is formed, and the first amorphous semiconductor layer 3b and the second amorphous semiconductor layer 4b on the bulk structure forming region R1 and the element isolation oxide film 2 are removed. Then, the exposed surface 9 that exposes a part of the first single crystal semiconductor layer 3a is formed, and when the first amorphous semiconductor layer 3b and the second amorphous semiconductor layer 4b are removed, the resist pattern R12 is removed. Then, transistors are formed in the bulk structure formation region R1 and the SOI structure formation region R2 on the semiconductor substrate 1 through the same steps as in FIGS.

  Thus, even when the first single crystal semiconductor layer 3a and the second single crystal semiconductor layer 4a are formed in the SOI structure formation region R2 on the semiconductor substrate 1, it is not necessary to use selective epitaxial growth, and the first amorphous semiconductor layer Even when the 3b and the second amorphous semiconductor layer 4b are deposited on the bulk structure forming region R1, the first amorphous semiconductor layer 3b and the second amorphous semiconductor layer 4b are collectively removed by etching when the exposed surface 9 is formed. can do. Therefore, even when the second single crystal semiconductor layer 4a disposed on the buried insulating layer 11 is formed in the SOI structure formation region R2, it is not necessary to use chlorine gas, and it is necessary to exclude chlorine gas. It is possible to reduce adverse effects on the energy and environment, and to form the SOI structure and the bulk structure on the same semiconductor substrate 1 while suppressing an increase in cost.

FIG. 18 is a diagram showing a method of manufacturing a semiconductor device according to the third embodiment of the present invention.
In FIG. 18, a chip region 102 is disposed on a semiconductor wafer W, and an SOI structure forming region 103 is provided in each chip region 102. A peripheral exposure region 101 is provided around the semiconductor wafer W. Here, since the exposure process is performed in each chip region 102, the opening 7 or the exposed surface 9 is formed even when the first amorphous semiconductor layer 3 b and the second amorphous semiconductor layer 4 b are formed in each chip region 102. In this case, the first amorphous semiconductor layer 3b and the second amorphous semiconductor layer 4b in each chip region 102 can be removed.

Further, since the resist in the peripheral exposure region 101 is also removed when the exposure processing of each chip region 102 is performed, the first amorphous semiconductor layer 3b and the first amorphous semiconductor layer 3b in the peripheral exposure region 101 are formed when the opening 7 or the exposed surface 9 is formed. 2 The amorphous semiconductor layer 4b can be removed.
On the other hand, the area less than one chip in the peripheral part of the semiconductor wafer W becomes a non-exposure area 104, and the resist always remains in the non-exposure area 104 when the exposure process of each chip area 102 is performed. For this reason, in the non-exposed region 104, the first amorphous semiconductor layer 3b and the second amorphous semiconductor layer 4b cannot be removed when the opening 7 or the exposed surface 9 is formed.

  For this reason, the first amorphous semiconductor layer 3b and the second amorphous semiconductor layer 4b in the non-exposed region 104 remaining in the peripheral portion of the semiconductor wafer W can be removed by wet etching using hydrofluoric acid or the like. Here, since the first amorphous semiconductor layer 3b and the second amorphous semiconductor layer 4b have a higher etching rate than the first single crystal semiconductor layer 3a and the second single crystal semiconductor layer 4, the first single crystal semiconductor layer 3a and the second amorphous semiconductor layer 4b The first amorphous semiconductor layer 3b and the second amorphous semiconductor layer 4b can be removed while suppressing the etching of the second single crystal semiconductor layer 4.

The figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment of this invention.

Explanation of symbols

  R1 bulk structure formation region, R2, 103 SOI structure formation region, 1 semiconductor substrate, 1a, 1b antioxidant film, 2 element isolation oxide film, 3a first single crystal semiconductor layer, 4a second single crystal semiconductor layer, 3b first Amorphous semiconductor layer, 4b Second amorphous semiconductor layer, R1, R2, R11, R12 resist pattern, R1a, R2a, R11a opening, 7 opening, 8 support, 9 exposed surface, 10 cavity, 11 buried insulating layer, 20, 30 Gate insulating film, 21, 31 Gate electrode, 22, 32 Side wall spacer, 23a, 23b, 33a, 33b Source / drain layer, W semiconductor wafer, 101 peripheral exposure region, 102 chip region, 104 non-exposed region

Claims (6)

Forming an insulating layer having an opening on a semiconductor substrate;
Forming a first single crystal semiconductor layer on a semiconductor substrate exposed through the opening while depositing a first amorphous semiconductor layer on the insulating layer by epitaxial growth;
While depositing a second amorphous semiconductor layer on the first amorphous semiconductor layer by epitaxial growth, a second single crystal semiconductor layer made of a material having an etching rate smaller than that of the first single crystal semiconductor layer is formed on the first single crystal semiconductor layer. Forming on the crystalline semiconductor layer;
Forming a first exposed portion for exposing side walls of the first single crystal semiconductor layer and the second single crystal semiconductor layer, and removing the first amorphous semiconductor layer and the second amorphous semiconductor layer deposited on the insulating layer; Process,
Forming a support embedded in the first exposed portion and supporting the second single crystal semiconductor layer on the semiconductor substrate;
Forming a second exposed portion for exposing a part of the first single crystal semiconductor layer from the support and the second single crystal semiconductor layer;
By selectively etching the first single crystal semiconductor layer through the second exposed portion, the cavity from which the first single crystal semiconductor layer has been removed is formed between the semiconductor substrate and the second single crystal semiconductor layer. A process of forming between,
And a step of forming a buried insulating layer buried in the cavity. Forming an insulating layer having an opening on a semiconductor substrate;
Forming a first single crystal semiconductor layer on a semiconductor substrate exposed through the opening while depositing a first amorphous semiconductor layer on the insulating layer by epitaxial growth;
While depositing a second amorphous semiconductor layer on the first amorphous semiconductor layer by epitaxial growth, a second single crystal semiconductor layer made of a material having an etching rate smaller than that of the first single crystal semiconductor layer is formed on the first single crystal semiconductor layer. Forming on the crystalline semiconductor layer;
Forming a first exposed portion exposing sidewalls of the first single crystal semiconductor layer and the second single crystal semiconductor layer;
Forming a support embedded in the first exposed portion and supporting the second single crystal semiconductor layer on the semiconductor substrate;
Forming a second exposed portion for exposing a part of the first single crystal semiconductor layer from the support and the second single crystal semiconductor layer; and a support deposited on the insulating layer; a first amorphous semiconductor layer And removing the second amorphous semiconductor layer;
By selectively etching the first single crystal semiconductor layer through the second exposed portion, the cavity from which the first single crystal semiconductor layer has been removed is formed between the semiconductor substrate and the second single crystal semiconductor layer. A process of forming between,
And a step of forming a buried insulating layer buried in the cavity. Forming an antioxidant film in a bulk structure formation region and an SOI structure formation region on a semiconductor substrate;
Forming an element isolation insulating film for isolating the bulk structure formation region and the SOI structure formation region by thermally oxidizing the semiconductor substrate using the antioxidant film as a mask;
Removing the antioxidant film on the SOI structure forming region while leaving the antioxidant film on the bulk structure forming region;
Forming a first single crystal semiconductor layer on a semiconductor substrate in the SOI structure formation region while depositing a first amorphous semiconductor layer on the element isolation insulating film and the antioxidant film by epitaxial growth;
While depositing a second amorphous semiconductor layer on the first amorphous semiconductor layer by epitaxial growth, a second single crystal semiconductor layer made of a material having an etching rate smaller than that of the first single crystal semiconductor layer is formed on the first single crystal semiconductor layer. Forming on the crystalline semiconductor layer;
Forming a first exposed portion for exposing side walls of the first single crystal semiconductor layer and the second single crystal semiconductor layer; and a first amorphous semiconductor layer deposited on the element isolation insulating film and the antioxidant film; 2 removing the amorphous semiconductor layer;
Forming a support embedded in the first exposed portion and supporting the second single crystal semiconductor layer on the semiconductor substrate;
Forming a second exposed portion for exposing a part of the first single crystal semiconductor layer from the support and the second single crystal semiconductor layer;
By selectively etching the first single crystal semiconductor layer through the second exposed portion, the cavity from which the first single crystal semiconductor layer has been removed is formed between the semiconductor substrate and the second single crystal semiconductor layer. A process of forming between,
And a step of forming a buried insulating layer buried in the cavity. Forming an antioxidant film in a bulk structure formation region and an SOI structure formation region on a semiconductor substrate;
Forming an element isolation insulating film for isolating the bulk structure formation region and the SOI structure formation region by thermally oxidizing the semiconductor substrate using the antioxidant film as a mask;
Removing the antioxidant film on the SOI structure forming region while leaving the antioxidant film on the bulk structure forming region;
Forming a first single crystal semiconductor layer on a semiconductor substrate in the SOI structure formation region while depositing a first amorphous semiconductor layer on the element isolation insulating film and the antioxidant film by epitaxial growth;
While depositing a second amorphous semiconductor layer on the first amorphous semiconductor layer by epitaxial growth, a second single crystal semiconductor layer made of a material having an etching rate smaller than that of the first single crystal semiconductor layer is formed on the first single crystal semiconductor layer. Forming on the crystalline semiconductor layer;
Forming a first exposed portion exposing sidewalls of the first single crystal semiconductor layer and the second single crystal semiconductor layer;
Forming a support embedded in the first exposed portion and supporting the second single crystal semiconductor layer on the semiconductor substrate;
Forming a second exposed portion for exposing a part of the first single crystal semiconductor layer from the support and the second single crystal semiconductor layer, and a support deposited on the element isolation insulating film and the antioxidant film; Removing the body, the first amorphous semiconductor layer, and the second amorphous semiconductor layer;
By selectively etching the first single crystal semiconductor layer through the second exposed portion, the cavity from which the first single crystal semiconductor layer has been removed is formed between the semiconductor substrate and the second single crystal semiconductor layer. A process of forming between,
And a step of forming a buried insulating layer buried in the cavity.   5. The method according to claim 1, further comprising a step of removing the first amorphous semiconductor layer and the second amorphous semiconductor layer in the non-exposed region remaining in the peripheral portion of the wafer by wet etching. A method for manufacturing a semiconductor device.   The semiconductor device according to claim 1, wherein the semiconductor substrate and the second single crystal semiconductor layer are single crystal Si, and the first single crystal semiconductor layer is single crystal SiGe. Method.

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