JP2007133395A5 - - Google Patents

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Publication number
JP2007133395A5
JP2007133395A5 JP2006294951A JP2006294951A JP2007133395A5 JP 2007133395 A5 JP2007133395 A5 JP 2007133395A5 JP 2006294951 A JP2006294951 A JP 2006294951A JP 2006294951 A JP2006294951 A JP 2006294951A JP 2007133395 A5 JP2007133395 A5 JP 2007133395A5
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JP
Japan
Prior art keywords
edge
image transfer
based image
shapes
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2006294951A
Other languages
English (en)
Japanese (ja)
Other versions
JP4299853B2 (ja
JP2007133395A (ja
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Publication date
Priority claimed from US11/164,076 external-priority patent/US7346887B2/en
Application filed filed Critical
Publication of JP2007133395A publication Critical patent/JP2007133395A/ja
Publication of JP2007133395A5 publication Critical patent/JP2007133395A5/ja
Application granted granted Critical
Publication of JP4299853B2 publication Critical patent/JP4299853B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2006294951A 2005-11-09 2006-10-30 集積回路フィーチャを形成するための方法およびプログラム Expired - Fee Related JP4299853B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/164,076 US7346887B2 (en) 2005-11-09 2005-11-09 Method for fabricating integrated circuit features

Publications (3)

Publication Number Publication Date
JP2007133395A JP2007133395A (ja) 2007-05-31
JP2007133395A5 true JP2007133395A5 (enExample) 2008-12-18
JP4299853B2 JP4299853B2 (ja) 2009-07-22

Family

ID=38005232

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006294951A Expired - Fee Related JP4299853B2 (ja) 2005-11-09 2006-10-30 集積回路フィーチャを形成するための方法およびプログラム

Country Status (3)

Country Link
US (1) US7346887B2 (enExample)
JP (1) JP4299853B2 (enExample)
CN (1) CN1963666B (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090004573A1 (en) * 2007-06-29 2009-01-01 Aton Thomas J System and method for making photomasks
US7818711B2 (en) * 2007-06-29 2010-10-19 Texas Instruments Incorporated System and method for making photomasks
JP4789158B2 (ja) * 2008-08-18 2011-10-12 株式会社東芝 半導体装置の製造方法、及び半導体装置
US20100127331A1 (en) * 2008-11-26 2010-05-27 Albert Ratnakumar Asymmetric metal-oxide-semiconductor transistors
US8455364B2 (en) * 2009-11-06 2013-06-04 International Business Machines Corporation Sidewall image transfer using the lithographic stack as the mandrel
US8716133B2 (en) 2012-08-23 2014-05-06 International Business Machines Corporation Three photomask sidewall image transfer method

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4919768A (en) 1989-09-22 1990-04-24 Shipley Company Inc. Electroplating process
US5342501A (en) 1989-11-21 1994-08-30 Eric F. Harnden Method for electroplating metal onto a non-conductive substrate treated with basic accelerating solutions for metal plating
US6576976B2 (en) 1997-01-03 2003-06-10 Integrated Device Technology, Inc. Semiconductor integrated circuit with an insulation structure having reduced permittivity
US6083275A (en) * 1998-01-09 2000-07-04 International Business Machines Corporation Optimized phase shift design migration
AT405842B (de) 1998-06-19 1999-11-25 Miba Gleitlager Ag Verfahren zum aufbringen einer metallischen schicht auf eine polymeroberfläche eines werkstückes
US6440839B1 (en) 1999-08-18 2002-08-27 Advanced Micro Devices, Inc. Selective air gap insulation
MY128644A (en) 2000-08-31 2007-02-28 Georgia Tech Res Inst Fabrication of semiconductor devices with air gaps for ultra low capacitance interconnections and methods of making same
US6660154B2 (en) 2000-10-25 2003-12-09 Shipley Company, L.L.C. Seed layer
US6653231B2 (en) 2001-03-28 2003-11-25 Advanced Micro Devices, Inc. Process for reducing the critical dimensions of integrated circuit device features
US6609245B2 (en) * 2001-11-29 2003-08-19 International Business Machines Corporation Priority coloring for VLSI designs
US6713396B2 (en) 2002-04-29 2004-03-30 Hewlett-Packard Development Company, L.P. Method of fabricating high density sub-lithographic features on a substrate
AU2003256531A1 (en) * 2002-07-12 2004-02-02 Cadence Design Systems, Inc. Method and system for context-specific mask writing
US6901576B2 (en) * 2002-11-20 2005-05-31 International Business Machines Corporation Phase-width balanced alternating phase shift mask design
US7100134B2 (en) * 2003-08-18 2006-08-29 Aprio Technologies, Inc. Method and platform for integrated physical verifications and manufacturing enhancements

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